December 2013 - U-Boot

[U-Boot] [PATCH V2] arm: omap3: Enable clocks for peripherals only if they are used
by Michael Trimarchi 04 Dec '13

04 Dec '13

This patch change the per_clocks_enable() function used in OMAP3 code to enable peripherals clocks. Only required clock should be activated. So if the board use the uart(x) as a console we need to activate it. The Board's config should include define to enable every subsystem that the board use. For a complete list of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER should be checked. Right now the bootloader can enable and disable clocks for: uart(x) using CONFIG_SYS_NS16550 gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 } i2c bus using CONFIG_DRIVER_OMAP34XX_I2C. Not required gptimer(x) and mcbsp(x) for booting are disabled by default and are not supported by any define. Their activation need to included in the per_clocks_enable if the peripheral is included. Not booting board should enable the peripheral clock connected to their driver Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> Cc: Igor Grinberg <grinberg(a)compulab.co.il> Cc: Tom Rini <trini(a)ti.com> --- Changes in V2: add a better comment for describe the problems that could be raised on some boards arch/arm/cpu/armv7/omap3/clock.c | 2 -- arch/arm/include/asm/arch-omap3/clock.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 14fc7e8..1bc27bd 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -730,8 +730,6 @@ void per_clocks_enable(void) sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON); sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON); } - sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON); - sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON); sdelay(1000); } diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h index be669c1..1912cc9 100644 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -27,8 +27,6 @@ #define ICK_DSS_ON 0x00000001 #define FCK_CAM_ON 0x00000001 #define ICK_CAM_ON 0x00000001 -#define FCK_PER_ON 0x0003ffff -#define ICK_PER_ON 0x0003ffff /* Used to index into DPLL parameter tables */ typedef struct { -- 1.8.1.2

3 2

[U-Boot] [PATCH] am3517_evm: activate Ethernet PHY
by yegorslists＠googlemail.com 04 Dec '13

04 Dec '13

From: Yegor Yefremov <yegorslists(a)googlemail.com> Pin 30 is connected to PHY's RESET# signal, so it must be put to high. Otherwize PHY won't be found via MDIO interface. Signed-off-by: Yegor Yefremov <yegorslists(a)googlemail.com> --- board/logicpd/am3517evm/am3517evm.c | 34 ++++++++++++++++++++++++++++++++++ board/logicpd/am3517evm/am3517evm.h | 2 +- 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 1569905..80f7de0 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -22,6 +22,7 @@ #include <asm/arch/musb.h> #include <asm/mach-types.h> #include <asm/errno.h> +#include <asm/gpio.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> #include <linux/usb/musb.h> @@ -31,6 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define AM3517_IP_SW_RESET 0x48002598 +#define CPGMACSS_SW_RST (1 << 1) + /* * Routine: board_init * Description: Early hardware init. @@ -98,6 +102,9 @@ static void am3517_evm_musb_init(void) */ int misc_init_r(void) { + volatile unsigned int ctr; + u32 reset; + #ifdef CONFIG_SYS_I2C_OMAP34XX i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif @@ -106,6 +113,33 @@ int misc_init_r(void) am3517_evm_musb_init(); +#if defined(CONFIG_DRIVER_TI_EMAC) + /* activate PHY reset */ + gpio_direction_output(30, 0); + gpio_set_value(30, 0); + + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* deactivate PHY reset */ + gpio_set_value(30, 1); + + /* allow the PHY to stabilize and settle down */ + ctr = 0; + do { + udelay(1000); + ctr++; + } while (ctr < 300); + + /* ensure that the module is out of reset */ + reset = readl(AM3517_IP_SW_RESET); + reset &= (~CPGMACSS_SW_RST); + writel(reset,AM3517_IP_SW_RESET); +#endif + return 0; } diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index 704af84..d407d66 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -315,7 +315,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ /*SYS_nRESWARM */\ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ /* - GPIO30 */\ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ /* - PEN_IRQ */\ -- 1.7.7

2 1

[U-Boot] [[PATCH]pandaboard: 0/1] Modification of Elpida DDR2 RAM for Pandaboard-ES Rev B3
by Hardik 04 Dec '13

04 Dec '13

From: Hardik Patel <hardik.patel(a)volansystech.com> This patch adds Elpida DDR2 RAM support for Pandaboard-ES Rev-B3 board.Enable automatic sdram detection in pandaboard defconfig, so that Elpida DDR2 RAM gets detected on Pandaboard-ES Rev-B3 board. We verified that u-boot works on Panadaboard-ES Rev-B2 board with this patch. Hardik Patel (1): Modification of Elpida DDR2 RAM for Pandaboard-ES Rev B3 include/configs/omap4_common.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 1.7.9.5

8 23

[U-Boot] [PATCH] davinci: fix Master Priority Registers location
by Viktar Palstsiuk 04 Dec '13

04 Dec '13

MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at 0x01C14114 Signed-off-by: Viktar Palstsiuk <viktar.palstsiuk(a)promwad.com> --- arch/arm/include/asm/arch-davinci/hardware.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 7aaf4bf..27b1844 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -478,8 +478,9 @@ struct davinci_syscfg_regs { dv_reg rsvd[13]; dv_reg kick0; dv_reg kick1; - dv_reg rsvd1[53]; + dv_reg rsvd1[52]; dv_reg mstpri[3]; + dv_reg rsvd2; dv_reg pinmux[20]; dv_reg suspsrc; dv_reg chipsig; -- 1.8.4.3

2 1

[U-Boot] [PATCH] arm: am335x: Add DT (FDT) support to Siemens boards
by Stefan Roese 04 Dec '13

04 Dec '13

Enable FDT support for all Siemens AM335x boards. To support newer Linux kernels with DT booting. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> Cc: Roger Meier <r.meier(a)siemens.com> Cc: Lukas Stockmann <lukas.stockmann(a)siemens.com> Cc: Tom Rini <trini(a)ti.com> --- include/configs/siemens-am33x-common.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 745e3be..b6534cc 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -455,4 +455,8 @@ #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ "press \"<Esc><Esc>\" to stop\n", bootdelay +/* Enable Device-Tree (FDT) support */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_FDT + #endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */ -- 1.8.4.3

3 2

[U-Boot] [PATCH] pcm051: Support for revision 3
by Lars Poeschel 04 Dec '13

04 Dec '13

From: Lars Poeschel <poeschel(a)lemonage.de> Phytec sells revision or version 3 of pcm051. It is labeled 1358.3 on the board. The difference for u-boot is that is has other DDR3 RAM on it: 1 x MT41K256M16HA125E instead of 2 x MT41J256M8HX15E on revisions 1 and 2. Both configurations are 512 MiB. Configure your u-boot build with pcm051_rev3 for the new RAM and pcm051_rev1 for the old RAM configuration. Board revision 2 has to use pcm051_rev1 also. Signed-off-by: Lars Poeschel <poeschel(a)lemonage.de> --- board/phytec/pcm051/board.c | 53 ++++++++++++++++++++++++++++++++++++++++----- boards.cfg | 3 ++- 2 files changed, 49 insertions(+), 7 deletions(-) diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index e40b0bd..629bc52 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -49,6 +49,7 @@ const struct dpll_params *get_dpll_ddr_params(void) return &dpll_ddr; } +#ifdef CONFIG_REV1 static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J256M8HX15E_RD_DQS, .datawdsratio0 = MT41J256M8HX15E_WR_DQS, @@ -82,6 +83,52 @@ static struct emif_regs ddr3_emif_reg_data = { PHY_EN_DYN_PWRDN, }; +void sdram_init(void) +{ + config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#else +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +void sdram_init(void) +{ + config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); +} +#endif + void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -95,12 +142,6 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } - -void sdram_init(void) -{ - config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} #endif /* diff --git a/boards.cfg b/boards.cfg index 9fc77fb..c2e24d6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -244,7 +244,8 @@ Active arm armv7 - armltd vexpress Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel(a)linaro.org> Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel(a)linaro.org> Active arm armv7 am33xx isee igep0033 igep0033 - Enric Balletbo i Serra <eballetbo(a)iseebcn.com> -Active arm armv7 am33xx phytec pcm051 pcm051 pcm051 Lars Poeschel <poeschel(a)lemonage.de> +Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel(a)lemonage.de> +Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel(a)lemonage.de> Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier(a)siemens.com> Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier(a)siemens.com> Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier(a)siemens.com> -- 1.8.4.2

3 4

[U-Boot] [PATCH] am335x_evm: Update nandboot to use partitions and DT
by Tom Rini 04 Dec '13

04 Dec '13

Signed-off-by: Tom Rini <trini(a)ti.com> --- include/configs/am335x_evm.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index f35ed6f..a1a5096 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -42,12 +42,11 @@ "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ "nandrootfstype=ubifs rootwait=1\0" \ - "nandsrcaddr=0x280000\0" \ - "nandboot=echo Booting from nand ...; " \ + "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ - "bootz ${loadaddr}\0" \ - "nandimgsize=0x500000\0" + "nand read ${fdtaddr} u-boot-spl-os; " \ + "nand read ${loadaddr} kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" #else #define NANDARGS "" #endif -- 1.7.9.5

1 1

[U-Boot] [PATCH] arm: omap3: Add uart4 omap3 adddress
by Michael Trimarchi 04 Dec '13

04 Dec '13

This patch add the OMAP34XX_UART4 memory address Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- arch/arm/include/asm/arch-omap3/omap3.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 7fb549a..65a5995 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -55,6 +55,7 @@ struct control_prog_io { #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) #define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) +#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000) /* General Purpose Timers */ #define OMAP34XX_GPT1 0x48318000 -- 1.8.1.2

2 6

[U-Boot] [PATCH] ARM: OMAP5+: Remove unnecessary EFUSE settings
by Lokesh Vutla 04 Dec '13

04 Dec '13

Certain EFUSE settings were recommended for the first four lots of OMAP5 ES1.0 silicon. These are not applicable for OMAP5 ES2.0 and DRA7 silicon. So removing these EFUSE settings. Reported-by: Griffis, Brad <bgriffis(a)ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- arch/arm/cpu/armv7/omap5/hwinit.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 1065891..8a5e6ed 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -168,12 +168,6 @@ void do_io_settings(void) io_settings_lpddr2(); else io_settings_ddr3(); - - /* Efuse settings */ - writel(EFUSE_1, (*ctrl)->control_efuse_1); - writel(EFUSE_2, (*ctrl)->control_efuse_2); - writel(EFUSE_3, (*ctrl)->control_efuse_3); - writel(EFUSE_4, (*ctrl)->control_efuse_4); } static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { -- 1.7.9.5

2 1

[U-Boot] [PATCH V2 0/3] OMAP5/DRA7: EMIF fixes for lowpower usecases
by Sricharan R 04 Dec '13

04 Dec '13

1) Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases 2) When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Sricharan R (3): ARM: DRA7: Add is_dra7xx cpu check definition ARM: DRA: EMIF: Change DDR3 settings to use hw leveling ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039 arch/arm/cpu/armv7/omap-common/emif-common.c | 142 +++++++++++++---- arch/arm/cpu/armv7/omap5/hw_data.c | 9 +- arch/arm/cpu/armv7/omap5/hwinit.c | 12 +- arch/arm/cpu/armv7/omap5/sdram.c | 214 ++++++++++++++++++-------- arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/emif.h | 14 +- arch/arm/include/asm/omap_common.h | 8 + 7 files changed, 301 insertions(+), 99 deletions(-) -- 1.7.9.5

2 6