December 2013 - U-Boot

[U-Boot] [PATCH 2/2] arm: exynos: remove the unused define.
by Jaehoon Chung 05 Dec '13

05 Dec '13

These defines didn't use anywhere. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index d1c5d4f..09d739d 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -6,10 +6,6 @@ */ #define DWMCI_CLKSEL 0x09C -#define DWMCI_SHIFT_0 0x0 -#define DWMCI_SHIFT_1 0x1 -#define DWMCI_SHIFT_2 0x2 -#define DWMCI_SHIFT_3 0x3 #define DWMCI_SET_SAMPLE_CLK(x) (x) #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) -- 1.7.9.5

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[U-Boot] [PATCH 1/1] powerpc/mpc8349: Use generic mpc85xx DDR driver
by York Sun 05 Dec '13

05 Dec '13

MPC8349 has been using mpc85xx DDR driver through a symbolic link to mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set under driver/ddr/fsl/, the link is replaced by referring driver directly. We now can simply enable the macro and use the driver. Other mpc83xx SoCs still use their own driver. Signed-off-by: York Sun <yorksun(a)freescale.com> --- This patch also fixes the issue addressed by this http://patchwork.ozlabs.org/patch/296086/ arch/powerpc/cpu/mpc83xx/Makefile | 4 +--- include/configs/MPC8349EMDS.h | 1 + 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index c345dd6..cf91162 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -38,9 +38,7 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o # Stub implementations of cache management functions for USB obj-y += cache.o -ifdef CONFIG_SYS_FSL_DDR2 -obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o -else +ifndef CONFIG_SYS_FSL_DDRC_GEN2 obj-y += spd_sdram.o endif obj-$(CONFIG_SYS_FSL_DDR2) += law.o diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index a80a696..0374841 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -67,6 +67,7 @@ */ #define CONFIG_SYS_FSL_DDR2 #ifdef CONFIG_SYS_FSL_DDR2 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x51 -- 1.7.9.5

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[U-Boot] [PATCH] powerpc/t2080qds: undef CONFIG_FSL_DDR_INTERACTIVE
by Shengzhou Liu 05 Dec '13

05 Dec '13

Usually CONFIG_FSL_DDR_INTERACTIVE feature is used for debug. we would not enable this by default to save the limited space of u-boot. This avoid following compiling error: section .bootpg loaded at [00000000effff000,00000000effff577] overlap ssection .data loaded at [00000000efff31b8,00000000f00010c7] u-boot: section .bootpg lma 0xeffff000 adjusted to 0xf00010c8 Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- include/configs/T2080QDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h index ad09816..bff001f 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T2080QDS.h @@ -155,7 +155,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR3 -#define CONFIG_FSL_DDR_INTERACTIVE +#undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 -- 1.8.0

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[U-Boot] [PATCH] T4240: Address T4240/T4160 Rev2.0 DDR clock change
by Roy Zang 05 Dec '13

05 Dec '13

MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0. It's 12 in Rev1.0, for Rev2.0 it uses 6. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> Reviewed-by: Yusong Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/speed.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 1a58a19..46ae80c 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -86,6 +86,14 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of + * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 + * it uses 6. + */ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) + if (SVR_MAJ(get_svr()) >= 2) + mem_pll_rat *= 2; +#endif if (mem_pll_rat > 2) sys_info->freq_ddrbus *= mem_pll_rat; else -- 1.7.9.5

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[U-Boot] [PATCH][v3] powerpc: spiflash:Add corenet devices support in eSPI SPL
by Priyanka Jain 05 Dec '13

05 Dec '13

Existing eSPI SPL framework assumes booting from spi-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040 as corenet deivces use PBI-RCW based intialization. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Changes for v3: Send as independent patch (not as part of patch set) Changes for v2: Updated description based on Sun York's inputs drivers/mtd/spi/fsl_espi_spl.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index 6263d8c..e5ac79b 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -31,6 +31,10 @@ void spi_boot(void) hang(); } +#ifdef CONFIG_FSL_CORENET + offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE; +#else /* * Load U-Boot image from SPI flash into RAM */ @@ -50,6 +54,7 @@ void spi_boot(void) code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); /* Skip spl code */ code_len = code_len - CONFIG_SPL_MAX_SIZE; +#endif /* copy code to DDR */ spi_flash_read(flash, offset, code_len, (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST); -- 1.7.4.1

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[U-Boot] [PATCH] powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROM
by Po Liu 05 Dec '13

05 Dec '13

Currently, there is only one EEPROM on c29xpcie board which isAT24C1024. We program the SPD data at beginning of the AT24C1024.But the AT24C1024 has a 16-bit sub-address mode. This patch is tomake it work when getting SPD in a 16-bit sub-address EEPROM. Signed-off-by: Po Liu <Po.Liu(a)freescale.com> --- board/freescale/c29xpcie/ddr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index 3337d6c..28f1bd2 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -84,3 +84,15 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; } } + +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} -- 1.8.0

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[U-Boot] [PATCH] powerpc/p1010rdb:modify the mtest start_address
by Zhao Qiang 05 Dec '13

05 Dec '13

In new board P1010RDB-PB, the interrupt vector table is at the start of memory. So if the start_address needs to be set a proper value. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- include/configs/P1010RDB.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c1cfbd4..e0fb4c1 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -173,7 +173,7 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ -- 1.8.4

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[U-Boot] [PATCH] powerpc/corenet: CPC1 speculation disable
by shh.xie＠gmail.com 05 Dec '13

05 Dec '13

From: Dave Liu <daveliu(a)freescale.com> In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable CPC1 speculation and keep it till relocation. Otherwise, speculation transactions will go to DDR controller, it will cause problem. Signed-off-by: Dave Liu <daveliu(a)freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/start.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6a81fa7..db84d10 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -886,7 +886,11 @@ delete_ccsr_l2_tlb: erratum_set_dcsr 0xb0008 0x00900000 erratum_set_dcsr 0xb0e40 0xe00a0000 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY +#ifdef CONFIG_RAMBOOT_PBL + erratum_set_ccsr 0x10f00 0x495e5000 +#else erratum_set_ccsr 0x10f00 0x415e5000 +#endif erratum_set_ccsr 0x11f00 0x415e5000 /* Make temp mapping uncacheable again, if it was initially */ -- 1.8.0

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[U-Boot] [PATCH REPOST] spi: tegra: clear RDY bit prior to every transfer
by Stephen Warren 05 Dec '13

05 Dec '13

From: Yen Lin <yelin(a)nvidia.com> The RDY bit indicates that a transfer is complete. This needs to be cleared by SW before every single HW transaction, rather than only at the start of each SW transaction (those being made up of n HW transactions). It seems that earlier HW may have cleared this bit autonomously when starting a new transfer, and hence this code was not needed in practice. However, this is generally a good idea in all cases. In Tegra124, the HW behaviour appears to have changed, and SW must explicitly clear this bit. Otherwise, SW will believe that transfers have completed when they have not, and may e.g. read stale data from the RX FIFO. Signed-off-by: Yen Lin <yelin(a)nvidia.com> [swarren, rewrote commit description, unified duplicate RDY clearing code and moved it right before the start of the HW transaction, unconditionally exit loop after reading RX data, rather than checking if TX FIFO is empty, since it is guaranteed to be] Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- drivers/spi/tegra114_spi.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 4d2af483d77f..810fa4718ce1 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -289,9 +289,6 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, reg = readl(&regs->fifo_status); writel(reg, &regs->fifo_status); - /* clear ready bit */ - setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY); - clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | (slave->cs << SPI_CMD1_CS_SEL_SHIFT)); @@ -305,7 +302,6 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, /* handle data in 32-bit chunks */ while (num_bytes > 0) { int bytes; - int is_read = 0; int tm, i; tmpdout = 0; @@ -319,6 +315,9 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, num_bytes -= bytes; + /* clear ready bit */ + setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY); + clrsetbits_le32(&regs->command1, SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); @@ -329,20 +328,14 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, * Wait for SPI transmit FIFO to empty, or to time out. * The RX FIFO status will be read and cleared last */ - for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { + for (tm = 0; tm < SPI_TIMEOUT; ++tm) { u32 fifo_status, xfer_status; - fifo_status = readl(&regs->fifo_status); - - /* We can exit when we've had both RX and TX activity */ - if (is_read && - (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)) - break; - xfer_status = readl(&regs->xfer_status); if (!(xfer_status & SPI_XFER_STS_RDY)) continue; + fifo_status = readl(&regs->fifo_status); if (fifo_status & SPI_FIFO_STS_ERR) { debug("%s: got a fifo error: ", __func__); if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) @@ -367,7 +360,6 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { tmpdin = readl(&regs->rx_fifo); - is_read = 1; /* swap bytes read in */ if (din != NULL) { @@ -377,6 +369,9 @@ int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, } din += bytes; } + + /* We can exit when we've had both RX and TX */ + break; } } -- 1.8.1.5

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[U-Boot] [PATCH 0/3] OMAP USB host fixes for Beagle & Panda
by Roger Quadros 04 Dec '13

04 Dec '13

Hi, This series - Fixes OMAP4 Panda USB device detection issues - Gets rid of ULPI reset errors on Beagle & Panda --- cheers, -roger Roger Quadros (3): usb: ehci-omap: Reset the USB Host OMAP module omap3_beagle: Don't use ulpi_reset omap4_panda: Don't use ulpi_reset drivers/usb/host/ehci-omap.c | 57 +++++++++++++++++++++++++++++++----------- include/configs/omap3_beagle.h | 3 --- include/configs/omap4_panda.h | 3 --- 3 files changed, 42 insertions(+), 21 deletions(-) -- 1.8.3.2

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