December 2013 - U-Boot

[U-Boot] [PATCH v2] net: Add fixed phy driver
by Christian Gmeiner 10 Dec '13

10 Dec '13

This patch is needed if the MAC is directly connected to a ethernet switch. In my case the FEC MAC is connected to a Micrel KSZ8895. All I need to to is configure my fixed phy/link like: #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE MII100 #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0x5 #define CONFIG_PHYLIB #define CONFIG_PHY_FIXED #define CONFIG_PHY_FIXED_SPEED SPEED_100 #define CONFIG_PHY_FIXED_DUPLEX DUPLEX_FULL Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- drivers/net/phy/Makefile | 1 + drivers/net/phy/fixed.c | 34 ++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 +++ 3 files changed, 38 insertions(+) create mode 100644 drivers/net/phy/fixed.c diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index fe762e9..17e486f 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -19,6 +19,7 @@ COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o +COBJS-$(CONFIG_PHY_FIXED) += fixed.o COBJS-$(CONFIG_PHY_ICPLUS) += icplus.o COBJS-$(CONFIG_PHY_LXT) += lxt.o COBJS-$(CONFIG_PHY_MARVELL) += marvell.o diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c new file mode 100644 index 0000000..70ff7bb --- /dev/null +++ b/drivers/net/phy/fixed.c @@ -0,0 +1,34 @@ +/* + * Fixed PHY driver + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2013 Bachmann electronic GmbH + * author Gmeiner Christian + */ +#include <config.h> +#include <common.h> +#include <phy.h> + +int fixed_config(struct phy_device *phydev) +{ + phydev->link = 1; + phydev->duplex = CONFIG_PHY_FIXED_SPEED; + phydev->speed = CONFIG_PHY_FIXED_DUPLEX; + + return 0; +} + +static struct phy_driver fixed_driver = { + .uid = 0xffffffff, + .mask = 0x00000000, + .name = "Fixed PHY", + .features = 0, + .config = &fixed_config, +}; + +int phy_fixed_init(void) +{ + phy_register(&fixed_driver); + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 62925bb..f2bccaf 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -479,6 +479,9 @@ int phy_init(void) #ifdef CONFIG_PHY_VITESSE phy_vitesse_init(); #endif +#ifdef CONFIG_PHY_FIXED + phy_fixed_init(); +#endif return 0; } -- 1.7.10.4

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Re: [U-Boot] FW: [PATCH 06/10] video: exynos: fimd: always use 16bpp display mode.
by Donghwa Lee 10 Dec '13

10 Dec '13

Hi, On 3 Dec 2013 18:03, Przemyslaw wrote: > This change updates exynos board files too. > 16 bpp mode is required by LCD console mode. > > Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> > --- > board/samsung/trats/trats.c | 2 +- > board/samsung/trats2/trats2.c | 2 +- > board/samsung/universal_c210/universal.c | 2 +- > drivers/video/exynos_fimd.c | 10 ++-------- > include/configs/s5pc210_universal.h | 2 +- > include/configs/trats.h | 2 +- > include/configs/trats2.h | 2 +- > 7 files changed, 8 insertions(+), 14 deletions(-) > > diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c > index ce4b41f..db527c7 100644 > --- a/board/samsung/trats/trats.c > +++ b/board/samsung/trats/trats.c > @@ -739,7 +739,7 @@ vidinfo_t panel_info = { > .vl_hsp = CONFIG_SYS_LOW, > .vl_vsp = CONFIG_SYS_LOW, > .vl_dp = CONFIG_SYS_LOW, > - .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ > + .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */ > > /* s6e8ax0 Panel infomation */ > .vl_hspw = 5, > diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c > index 73b8cc1..6fa02c9 100644 > --- a/board/samsung/trats2/trats2.c > +++ b/board/samsung/trats2/trats2.c > @@ -542,7 +542,7 @@ vidinfo_t panel_info = { > .vl_hsp = CONFIG_SYS_LOW, > .vl_vsp = CONFIG_SYS_LOW, > .vl_dp = CONFIG_SYS_LOW, > - .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ > + .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */ > > /* s6e8ax0 Panel infomation */ > .vl_hspw = 5, > diff --git a/board/samsung/universal_c210/universal.c > b/board/samsung/universal_c210/universal.c > index 166d5ee..1ebea0f 100644 > --- a/board/samsung/universal_c210/universal.c > +++ b/board/samsung/universal_c210/universal.c > @@ -446,7 +446,7 @@ vidinfo_t panel_info = { > .vl_vsp = CONFIG_SYS_HIGH, > .vl_dp = CONFIG_SYS_HIGH, > > - .vl_bpix = 5, /* Bits per pixel */ > + .vl_bpix = 4, /* Bits per pixel */ > > /* LD9040 LCD Panel */ > .vl_hspw = 2, > diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c > index f962c4f..847fbe8 100644 > --- a/drivers/video/exynos_fimd.c > +++ b/drivers/video/exynos_fimd.c > @@ -73,18 +73,12 @@ static void exynos_fimd_set_par(unsigned int win_id) > /* DATAPATH is DMA */ > cfg |= EXYNOS_WINCON_DATAPATH_DMA; > > - if (pvid->logo_on) /* To get proprietary LOGO */ > - cfg |= EXYNOS_WINCON_WSWP_ENABLE; > - else /* To get output console on LCD */ > - cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; > + cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; > > /* dma burst is 16 */ > cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; > > - if (pvid->logo_on) /* To get proprietary LOGO */ > - cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; > - else /* To get output console on LCD */ > - cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; > + cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; > Why does exynos fimd always use 16bpp display mode? It could be used as other bpp modes in exynos. How do you use above vl_bpix variable in panel_info structure to check bpp mode? BR, Donghwa Lee.

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Re: [U-Boot] [PATCH 05/10] lib: tizen: add Tizen 16bpp logo support.
by Przemyslaw Marczak 10 Dec '13

10 Dec '13

Hello Hyungwon, On 12/10/2013 07:09 AM, 황형원 wrote: > Dear Marczak, > > Please replace the old tizen logo by the new one. > If you don't have the new one, I can send you. > > Thank you. > > > -----Original Message----- > From: u-boot-bounces(a)lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On > Behalf Of Przemyslaw Marczak > Sent: Wednesday, December 04, 2013 3:03 AM > To: u-boot(a)lists.denx.de > Cc: Przemyslaw Marczak > Subject: [U-Boot] [PATCH 05/10] lib: tizen: add Tizen 16bpp logo support. > > Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> > --- > This is big size patch. Please follow link: > http://www.denx.de/wiki/pub/U-Boot/TooBigPatches/0005-lib-tizen-add-Tizen- > 16bpp-logo-support.patch > > > Best regards, > Hyungwon Hwang > > Do you mean silver logo from tizen.org? Actually I can make some but if you send me one then it will be faster. Thank you -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marczak(a)samsung.com

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[U-Boot] OMAP4: NAND support (confusion)
by Vikram Singh Shekhawat 10 Dec '13

10 Dec '13

hi all, I am looking into nand for omap4, i have added patches for nand support in omap4 but have some doubts. 1) In thease patches we are not using CONFIG's register for chip select, we define that in arch/arm/include/asm/arch-omap4/mem.h(as copied from omap3's mem.h) but thease are not uses in arch/arm/cpu/armv7/omap-common/mem.c or any other place in u-boot for omap4. Is it possible without adding thease CONFIG's register, NAND will works properly. 2) I am not understanding what is the meaning of GPMC_SIZE_256M , GPMC_SIZE_128M , GPMC_SIZE_64M , GPMC_SIZE_32M, GPMC_SIZE_16M.Defined in arch/arm/include/asm/arch-omap4/mem.h. I have a MT29F4G08ABBD(NAND with 4 GB space) which gpmc size configuration i need for this nand chip. Thanks & regards Vikram singh shekhawat

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[U-Boot] [PATCH REPOST] ARM: rpi_b: power on SDHCI and USB HW modules
by Stephen Warren 09 Dec '13

09 Dec '13

Send RPC commands to the VideoCore to turn on the SDHCI and USB modules. For SDHCI this isn't needed in practice, since the firmware already turned on the power in order to load U-Boot. However, it's best to be explicit. For USB, this is necessary, since the module isn't powered otherwise. This will allow the kernel USB driver to work. Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- arch/arm/include/asm/arch-bcm2835/mbox.h | 48 ++++++++++++++++++++++++++++++ board/raspberrypi/rpi_b/rpi_b.c | 34 ++++++++++++++++++++- 2 files changed, 81 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 6b806ec..38cb42a 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -133,6 +133,54 @@ struct bcm2835_mbox_tag_get_arm_mem { } body; }; +#define BCM2835_MBOX_POWER_DEVID_SDHCI 0 +#define BCM2835_MBOX_POWER_DEVID_UART0 1 +#define BCM2835_MBOX_POWER_DEVID_UART1 2 +#define BCM2835_MBOX_POWER_DEVID_USB_HCD 3 +#define BCM2835_MBOX_POWER_DEVID_I2C0 4 +#define BCM2835_MBOX_POWER_DEVID_I2C1 5 +#define BCM2835_MBOX_POWER_DEVID_I2C2 6 +#define BCM2835_MBOX_POWER_DEVID_SPI 7 +#define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 + +#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 1) +/* Device doesn't exist */ +#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) + +#define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 + +struct bcm2835_mbox_tag_get_power_state { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 device_id; + } req; + struct { + u32 device_id; + u32 state; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 + +#define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) +#define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) + +struct bcm2835_mbox_tag_set_power_state { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 device_id; + u32 state; + } req; + struct { + u32 device_id; + u32 state; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 #define BCM2835_MBOX_CLOCK_ID_EMMC 1 diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c index 16d442a..f33fae9 100644 --- a/board/raspberrypi/rpi_b/rpi_b.c +++ b/board/raspberrypi/rpi_b/rpi_b.c @@ -29,6 +29,12 @@ struct msg_get_arm_mem { u32 end_tag; }; +struct msg_set_power_state { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_set_power_state set_power_state; + u32 end_tag; +}; + struct msg_get_clock_rate { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_get_clock_rate get_clock_rate; @@ -54,11 +60,35 @@ int dram_init(void) return 0; } +static int power_on_module(u32 module) +{ + ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16); + int ret; + + BCM2835_MBOX_INIT_HDR(msg_pwr); + BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state, + SET_POWER_STATE); + msg_pwr->set_power_state.body.req.device_id = module; + msg_pwr->set_power_state.body.req.state = + BCM2835_MBOX_SET_POWER_STATE_REQ_ON | + BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, + &msg_pwr->hdr); + if (ret) { + printf("bcm2835: Could not set module %u power state\n", + module); + return -1; + } + + return 0; +} + int board_init(void) { gd->bd->bi_boot_params = 0x100; - return 0; + return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD); } int board_mmc_init(void) @@ -66,6 +96,8 @@ int board_mmc_init(void) ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16); int ret; + power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI); + BCM2835_MBOX_INIT_HDR(msg_clk); BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE); msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC; -- 1.7.10.4

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[U-Boot] [PATCH] ARM: tegra: Use the IRAM for the early stack
by Alban Bedel 09 Dec '13

09 Dec '13

Unlike many other platforms the tegra platform has the luxury of already having the SDRAM running during the early init, and it is used for the early stack. However the memory test of the POST subsystem is expecting the SDRAM to be unused, and on tegra platforms the test fail to run as it destroy the stack. To fix the problem simply use the IRAM for the initial stack. Signed-off-by: Alban Bedel <alban.bedel(a)avionic-design.de> --- include/configs/tegra-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 522cd41..340f5aa 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -124,7 +124,7 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE +#define CONFIG_SYS_INIT_RAM_ADDR EARLY_CPU_STACK #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ -- 1.8.5

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[U-Boot] [PULL] u-boot-atmel/master -> u-boot-arm/master
by Andreas Bießmann 09 Dec '13

09 Dec '13

Dear Albert Aribaud, please pull the following changes from u-boot-atmel/master into u-boot-arm/master. The following changes since commit 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7: arm: keep all sections in ELF file (2013-12-07 06:53:58 +0100) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to 1dcdd86205708d3ab9f0dc3a2d6b5fa12b16fde4: arm: at91: support for the Calao USB-A9263 board (based on AT91SAM9263) (2013-12-09 13:21:54 +0100) ---------------------------------------------------------------- Andreas Bießmann (4): at91: add new gpio pin definitions at91: redefine legacy GPIO PIN_BASE at91: nand: switch atmel_nand to generic GPIO API at91: switch coloured LED to gpio API Heiko Schocher (2): arm, at91: add Siemens board taurus and axm arm, at91: add siemens corvus board Mateusz Kulikowski (1): arm: at91: support for the Calao USB-A9263 board (based on AT91SAM9263) arch/arm/cpu/arm926ejs/at91/led.c | 16 ++- arch/arm/include/asm/arch-at91/gpio.h | 26 ++++- board/BuS/vl_ma2sc/vl_ma2sc.c | 5 +- board/calao/usb_a9263/Makefile | 14 +++ board/calao/usb_a9263/usb_a9263.c | 148 +++++++++++++++++++++++++ board/egnite/ethernut5/ethernut5.c | 3 +- board/esd/meesc/meesc.c | 5 +- board/esd/otc570/otc570.c | 5 +- board/eukrea/cpu9260/cpu9260.c | 5 +- board/ronetix/pm9261/led.c | 14 +-- board/ronetix/pm9261/pm9261.c | 5 +- board/ronetix/pm9263/led.c | 10 +- board/ronetix/pm9263/pm9263.c | 5 +- board/ronetix/pm9g45/pm9g45.c | 5 +- board/siemens/corvus/Makefile | 18 +++ board/siemens/corvus/board.c | 195 +++++++++++++++++++++++++++++++++ board/siemens/taurus/Makefile | 18 +++ board/siemens/taurus/taurus.c | 160 +++++++++++++++++++++++++++ boards.cfg | 4 + drivers/gpio/at91_gpio.c | 4 +- drivers/mtd/nand/atmel_nand.c | 8 +- include/configs/at91sam9n12ek.h | 4 +- include/configs/corvus.h | 165 ++++++++++++++++++++++++++++ include/configs/cpu9260.h | 4 +- include/configs/ethernut5.h | 2 +- include/configs/meesc.h | 4 +- include/configs/otc570.h | 4 +- include/configs/pm9261.h | 10 +- include/configs/pm9263.h | 8 +- include/configs/pm9g45.h | 8 +- include/configs/taurus.h | 160 +++++++++++++++++++++++++++ include/configs/usb_a9263.h | 169 ++++++++++++++++++++++++++++ include/configs/vl_ma2sc.h | 4 +- 33 files changed, 1145 insertions(+), 70 deletions(-) create mode 100644 board/calao/usb_a9263/Makefile create mode 100644 board/calao/usb_a9263/usb_a9263.c create mode 100644 board/siemens/corvus/Makefile create mode 100644 board/siemens/corvus/board.c create mode 100644 board/siemens/taurus/Makefile create mode 100644 board/siemens/taurus/taurus.c create mode 100644 include/configs/corvus.h create mode 100644 include/configs/taurus.h create mode 100644 include/configs/usb_a9263.h

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[U-Boot] [PATCH v2] t2080qds/ddr: update ddr parameters
by Shengzhou Liu 09 Dec '13

09 Dec '13

- optimize ddr parameters for whole frequency range from 1500MT/s to 2140MT/s. - remove unused patameters: 'cpo', 'wrdata delay', '2T', which is unrelated to DDR3/3L on t2080qds. - remove unused rdimm code(only udimm is supported on t2080qds board). Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- Against master branch of git://git.denx.de/u-boot-mpc85xx.git v2: throw an error in case of rDIMM. board/freescale/t2080qds/ddr.c | 18 ++---------- board/freescale/t2080qds/ddr.h | 64 +++++++++--------------------------------- 2 files changed, 17 insertions(+), 65 deletions(-) diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c index 5db5d21..d877731 100644 --- a/board/freescale/t2080qds/ddr.c +++ b/board/freescale/t2080qds/ddr.c @@ -24,24 +24,19 @@ void fsl_ddr_board_options(memctl_options_t *popts, const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; - if (ctrl_num > 2) { + if (ctrl_num > 1) { printf("Not supported controller number %d\n", ctrl_num); return; } if (!pdimm->n_ranks) return; - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ if (popts->registered_dimm_en) - pbsp = rdimms[0]; + puts("ERROR: rDIMM is not supported on t2080qds board\n"); else pbsp = udimms[0]; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; @@ -49,14 +44,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -69,13 +60,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, printf("for data rate %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h index 964eaad..f8c5d2b 100644 --- a/board/freescale/t2080qds/ddr.h +++ b/board/freescale/t2080qds/ddr.h @@ -14,9 +14,6 @@ struct board_specific_parameters { u32 wrlvl_start; u32 wrlvl_ctl_2; u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; }; /* @@ -28,58 +25,25 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0}, - {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, - {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, - {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, - {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, + {2, 1500, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {2, 1700, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 2140, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {1, 1500, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, + {1, 1700, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 2140, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, + {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b}, {} }; -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {} -}; - -/* - * The three slots have slightly different timing. The center values are good - * for all slots. We use identical speed tables for them. In future use, if - * DIMMs require separated tables, make more entries as needed. - */ static const struct board_specific_parameters *udimms[] = { udimm0, }; - -/* - * The three slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, -}; - - #endif -- 1.8.0

2 1

[U-Boot] [PATCH] powerpc/mpc85xx: Add support for single source clocking
by Priyanka Jain 09 Dec '13

09 Dec '13

Single-source clocking is new feature introduced in T1040. In this mode, a differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-sourec clocking whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/speed.c | 20 ++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/immap_85xx.h | 3 +++ 3 files changed, 24 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 1a58a19..cd49695 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -77,7 +77,27 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_systembus = sysclk; #ifdef CONFIG_DDR_CLK_FREQ +#ifdef CONFIG_SINGLE_SOURCE_CLK + /* + * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS + * are driven by separate DDR Refclock or single source + * differential clock. + */ + uint single_src; + single_src = (in_be32(&gur->rcwsr[5]) >> + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; + /* + * For single source clocking, both ddrclock and syclock + * are driven by differential sysclock. + */ + if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) + sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; + else + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#else sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#endif #else sys_info->freq_ddrbus = sysclk; #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 99e16bd..370bd21 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -711,6 +711,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CONFIG_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 672e8c6..68c3c82 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1774,6 +1774,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011 +#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 -- 1.7.4.1

3 4

[U-Boot] [PATCH v5] at91: add support for CDU9G25 board
by Jiri Prchal 09 Dec '13

09 Dec '13

This patch adds support for our companies board CDU9G25 with Atmel AT91SAM9G25, 128MB DDR2, 256MB NAND. Signed-off-by: Jiri Prchal <jiri.prchal(a)aksignal.cz> --- v.2 Fixed static IP and MAC addr cofiguration by random MAC and DHCP. Added entry to MAINTAINERS. Fixed line lenght, trailing spaces and other cosmetics. v.3 Removed static eth_gadget addresses. MAC address set from serial number of F-RAM. v.4 Changed debug to printf if used random MAC addr, print that addr. Keep MAC addr set in enviroment. v.5 Changes to Bo Shen comments. Signed-off-by: Jiri Prchal <jiri.prchal(a)aksignal.cz> --- arch/arm/include/asm/mach-types.h | 1 + board/AKsignal/cdu9g25/Makefile | 34 ++++++ board/AKsignal/cdu9g25/cdu9g25.c | 202 +++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/cdu9g25.h | 210 +++++++++++++++++++++++++++++++++++++ 5 files changed, 448 insertions(+) create mode 100644 board/AKsignal/cdu9g25/Makefile create mode 100644 board/AKsignal/cdu9g25/cdu9g25.c create mode 100644 include/configs/cdu9g25.h diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 440b041..9b274ba 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -986,6 +986,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_VIT_IBOX 3371 #define MACH_TYPE_DM6441_ESP 3372 #define MACH_TYPE_AT91SAM9X5EK 3373 +#define MACH_TYPE_CDU9G25 3373 #define MACH_TYPE_LIBRA 3374 #define MACH_TYPE_EASYCRRH 3375 #define MACH_TYPE_TRIPEL 3376 diff --git a/board/AKsignal/cdu9g25/Makefile b/board/AKsignal/cdu9g25/Makefile new file mode 100644 index 0000000..b644a83 --- /dev/null +++ b/board/AKsignal/cdu9g25/Makefile @@ -0,0 +1,34 @@ +# +# U-boot - Makefile +# +# (C) Copyright 2013 +# Jiri Prchal <jiri.prchal(a)aksignal.cz> +# AK signal <www.aksignal.cz> +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += cdu9g25.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/AKsignal/cdu9g25/cdu9g25.c b/board/AKsignal/cdu9g25/cdu9g25.c new file mode 100644 index 0000000..7321a02 --- /dev/null +++ b/board/AKsignal/cdu9g25/cdu9g25.c @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2013 + * Jiri Prchal <jiri.prchal(a)aksignal.cz> + * AK signal <www.aksignal.cz> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/at91sam9x5_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_spi.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <atmel_hlcdc.h> +#include <atmel_mci.h> +#include <spi.h> +#include <net.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void cdu9g25_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + unsigned long csa; + + /* Enable CS3 */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(1), + &smc->cs[3].mode); + + writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + debug("spi_cs_is_valid: bus=%u cs=%u\n", bus, cs); + if (bus < 2 && cs < 4) + return 1; + + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + debug("spi_cs_activate: bus=%u cs=%u\n", slave->bus, slave->cs); + at91_set_pio_output(AT91_PIO_PORTA, 23, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + debug("spi_cs_deactivate: bus=%u cs=%u\n", slave->bus, slave->cs); + at91_set_pio_output(AT91_PIO_PORTA, 23, 1); +} + +void cdu9g25_spi0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + at91_set_pio_output(AT91_PIO_PORTA, 23, 1); +} + +void cdu9g25_init_enetaddr(void) +{ + struct spi_slave *slave; + uchar sernum[9]; + int ret; + + if (eth_getenv_enetaddr("ethaddr", sernum)) + return; + + slave = spi_setup_slave(0, 3, 1000000, SPI_MODE_0); + if (!slave) { + debug("Failed to set up FRAM slave\n"); + goto err_spi_setup_slave; + } + + ret = spi_claim_bus(slave); + if (ret) { + debug("Failed to claim SPI bus: %d\n", ret); + goto err_spi_claim_bus; + } + + *sernum = 0xc3; /* opcode to read serial number */ + ret = spi_xfer(slave, sizeof(sernum) * 8, sernum, sernum, + SPI_XFER_BEGIN | SPI_XFER_END); + if (ret) { + debug("Failed to read serial#: %d\n", ret); + goto err_spi_xfer; + } + + memmove(sernum + 1, sernum + 3, 6); + *sernum = 0x02; + +err_spi_xfer: + spi_release_bus(slave); +err_spi_claim_bus: + spi_free_slave(slave); +err_spi_setup_slave: + if (!is_valid_ether_addr(sernum)) { + eth_random_enetaddr(sernum); + printf("Using random MAC address %pM\n", sernum); + } + eth_setenv_enetaddr("ethaddr", sernum); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + cdu9g25_init_enetaddr(); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); + + return rc; +} + +static void cdu9g25_led_init(void) +{ + at91_set_gpio_output(CONFIG_LED_B, 1); + at91_set_gpio_value(CONFIG_LED_B, 0); +} + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_CDU9G25; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + cdu9g25_led_init(); + + cdu9g25_nand_hw_init(); + + cdu9g25_spi0_hw_init(); + + at91_macb_hw_init(); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +} +#endif + diff --git a/boards.cfg b/boards.cfg index dbd8479..7a7d39e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -77,6 +77,7 @@ Active arm arm926ejs - armltd integrator Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla(a)marvell.com> Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav <ajay.bhargav(a)einfochips.com> Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin(a)ossfans.org> +Active arm arm926ejs at91 AKsignal cdu9g25 cdu9g25 - Jiri Prchal <jiri.prchal(a)aksignal.cz> Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian(a)popies.net> Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian(a)popies.net> Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian(a)popies.net> diff --git a/include/configs/cdu9g25.h b/include/configs/cdu9g25.h new file mode 100644 index 0000000..a4189cc --- /dev/null +++ b/include/configs/cdu9g25.h @@ -0,0 +1,210 @@ +/* + * (C) Copyright 2013 + * Jiri Prchal <jiri.prchal(a)aksignal.cz> + * AK signal <www.aksignal.cz> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#define CONFIG_AT91SAM9X5 +#include <asm/hardware.h> + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ +#define CONFIG_SYS_HZ 1000 + +/* Define actual evaluation board type from used processor type */ +#define CONFIG_CDU9G25 +#define CONFIG_AT91FAMILY +#define CONFIG_IDENT_STRING "_cdu9g25" + +/* Misc CPU related */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* LEDs */ +#define CONFIG_LED_R AT91_PIN_PB18 +#define CONFIG_LED_G AT91_PIN_PB16 +#define CONFIG_LED_Y AT91_PIN_PB14 +#define CONFIG_LED_B AT91_PIN_PB12 + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_BOOT_RETRY_TIME 600 + +#define CONFIG_HW_WATCHDOG +#define CONFIG_AT91SAM9_WATCHDOG + +/* SPI */ +#define CONFIG_ATMEL_SPI +#define CONFIG_CMD_SPI + +/* RAMTRON FRAM */ +#define CONFIG_CMD_SF +#define CONFIG_ATMEL_SPI0 /* SPI used for FRAM is SPI0 */ +#define CONFIG_SPI_FLASH /* RAMTRON FRAM on SPI bus */ +#define CONFIG_SPI_FRAM_RAMTRON + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT + +/* + * SDRAM: 1 bank, 128 MB + * Initialized before u-boot gets started. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */ +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CONFIG_SYS_TEXT_BASE 0x27f00000 + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024\ + - GENERATED_GBL_DATA_SIZE) + +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 + +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 + +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_NAND_TRIMFFS +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:256k(bootstrap),"\ + "768k(uboot),256k(ubootenv),"\ + "4864k(kernel),"\ + "-(root)" + +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +/* FAT */ +#ifdef CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY +#define CONFIG_RANDOM_MACADDR + +/* USB */ +#ifdef CONFIG_CMD_USB +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#else +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#endif +#define CONFIG_USB_ATMEL +#define CONFIG_USB_STORAGE +#endif + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_TEXT_BASE + +/* CONFIG_SYS_USE_NANDFLASH */ +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128kB */ +#define CONFIG_ENV_RANGE 0x40000 /* 2 sectors for bad sector handling */ +#define CONFIG_BOOTCOMMAND "nand read 21000000 kernel; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 ubi.mtd=root "\ + "root=ubi0:root rootfstype=ubifs rw" +#define CONFIG_SERVERIP 10.0.1.1 +#define CONFIG_BOOTFILE "kernel_cdu9g25" +#define CONFIG_PREBOOT "mtdparts default" /* for partitions */ + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)\ + + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + CONFIG_ENV_SIZE) + +#endif -- 1.7.9.5

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