December 2013 - U-Boot

[U-Boot] [PATCH v6] spi: Add support SH Quad SPI driver
by Nobuhiro Iwamatsu 16 Dec '13

16 Dec '13

This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp(a)renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- Changes for v6: - Update Makefile to new style. Changes for v5: - Add print abort when call ctrlc(). - Move source code in spi_xfer() which should be processed by spi_cs_activate(). - Move source code in spi_xfer() which should be processed by spi_cs_deactivate(). - Remove sh_qspi_xfer, move to spi_xfer(). Changes for v4: - Added tabs - Added comments - Added sh_qspi_init() Changes for v3: - Change Queued to Quad. - Remove path of file from file header. - Use read* and write* directly instead of sh_qspi_write* sh_qspi_read*. - Change driver format. Changes for v2: - "SH QSPI" to "SH QSPI (Queued SPI)". - Remove magic number. drivers/spi/Makefile | 1 + drivers/spi/sh_qspi.c | 244 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 245 insertions(+) create mode 100644 drivers/spi/sh_qspi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 27902fe..914e71f 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o obj-$(CONFIG_SH_SPI) += sh_spi.o +obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_FDT_SPI) += fdt_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c new file mode 100644 index 0000000..8f53552 --- /dev/null +++ b/drivers/spi/sh_qspi.c @@ -0,0 +1,244 @@ +/* + * SH QSPI (Quad SPI) driver + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> + +/* SH QSPI register bit masks <REG>_<BIT> */ +#define SPCR_MSTR 0x08 +#define SPCR_SPE 0x40 +#define SPSR_SPRFF 0x80 +#define SPSR_SPTEF 0x20 +#define SPPCR_IO3FV 0x04 +#define SPPCR_IO2FV 0x02 +#define SPPCR_IO1FV 0x01 +#define SPBDCR_RXBC0 (1 << 0) +#define SPCMD_SCKDEN (1 << 15) +#define SPCMD_SLNDEN (1 << 14) +#define SPCMD_SPNDEN (1 << 13) +#define SPCMD_SSLKP (1 << 7) +#define SPCMD_BRDV0 (1 << 2) +#define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \ + SPCMD_SPNDEN | SPCMD_SSLKP | \ + SPCMD_BRDV0 +#define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \ + SPCMD_BRDV0 +#define SPBFCR_TXRST (1 << 7) +#define SPBFCR_RXRST (1 << 6) + +/* SH QSPI register set */ +struct sh_qspi_regs { + unsigned char spcr; + unsigned char sslp; + unsigned char sppcr; + unsigned char spsr; + unsigned long spdr; + unsigned char spscr; + unsigned char spssr; + unsigned char spbr; + unsigned char spdcr; + unsigned char spckd; + unsigned char sslnd; + unsigned char spnd; + unsigned char dummy0; + unsigned short spcmd0; + unsigned short spcmd1; + unsigned short spcmd2; + unsigned short spcmd3; + unsigned char spbfcr; + unsigned char dummy1; + unsigned short spbdcr; + unsigned long spbmul0; + unsigned long spbmul1; + unsigned long spbmul2; + unsigned long spbmul3; +}; + +struct sh_qspi_slave { + struct spi_slave slave; + struct sh_qspi_regs *regs; +}; + +static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave) +{ + return container_of(slave, struct sh_qspi_slave, slave); +} + +static void sh_qspi_init(struct sh_qspi_slave *ss) +{ + /* QSPI initialize */ + writeb(SPCR_MSTR, &ss->regs->spcr); + writeb(0x00, &ss->regs->sslp); + writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr); + + /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */ + writeb(0x01, &ss->regs->spbr); + + writeb(0x00, &ss->regs->spdcr); + writeb(0x00, &ss->regs->spckd); + writeb(0x00, &ss->regs->sslnd); + writeb(0x00, &ss->regs->spnd); + writew(SPCMD_INIT1, &ss->regs->spcmd0); + writew(SPCMD_INIT2, &ss->regs->spcmd0); + writeb(SPBFCR_TXRST|SPBFCR_RXRST, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spscr); + writeb(SPCR_SPE|SPCR_MSTR, &ss->regs->spcr); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + + writeb(SPCR_MSTR, &ss->regs->spcr); + writew(SPCMD_INIT1, &ss->regs->spcmd0); + writeb(SPBFCR_TXRST|SPBFCR_RXRST, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spscr); + writeb(SPCR_SPE|SPCR_MSTR, &ss->regs->spcr); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + + writeb(SPCR_MSTR, &ss->regs->spcr); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct sh_qspi_slave *ss; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs); + if (!ss) { + printf("SPI_error: Fail to allocate sh_qspi_slave\n"); + return NULL; + } + + ss->regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE; + + /* Init SH QSPI */ + sh_qspi_init(ss); + + return &ss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct sh_qspi_slave *spi = to_sh_qspi(slave); + + free(spi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + unsigned long nbyte; + int ret = 0; + unsigned char dtdata = 0, drdata; + unsigned char *tdata = &dtdata, *rdata = &drdata; + unsigned long *spbmul0 = &ss->regs->spbmul0; + + if (dout == NULL && din == NULL) { + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + return 0; + } + + if (bitlen % 8) { + printf("%s: bitlen is not 8bit alined %d", __func__, bitlen); + return 1; + } + + nbyte = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) { + spi_cs_activate(slave); + + /* Set 1048576 byte */ + writel(0x100000, spbmul0); + } + + if (flags & SPI_XFER_END) + writel(nbyte, spbmul0); + + if (dout != NULL) + tdata = (unsigned char *)dout; + + if (din != NULL) + rdata = din; + + while (nbyte > 0) { + while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) { + if (ctrlc()) { + puts("abort\n"); + return 1; + } + udelay(10); + } + + writeb(*tdata, (unsigned char *)(&ss->regs->spdr)); + + while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) { + if (ctrlc()) { + puts("abort\n"); + return 1; + } + udelay(1); + } + + while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) { + if (ctrlc()) { + puts("abort\n"); + return 1; + } + udelay(10); + } + + *rdata = readb((unsigned char *)(&ss->regs->spdr)); + + if (dout != NULL) + tdata++; + if (din != NULL) + rdata++; + + nbyte--; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} -- 1.8.4.2

2 3

[U-Boot] [PATCH] ARM: bcm2835: fix mailbox timeout
by Stephen Warren 16 Dec '13

16 Dec '13

My original intention was to have a 100ms timeout. However, the timer operations used return values in ms not us, so we ended up with a 100s timeout instead. Fixing this exposes that some operations need longer to operate than 100ms, so bump the timeout up to a whole second. Reported-by: Andre Heider <a.heider(a)gmail.com> Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- Albert, I believe this implies that my "ARM: rpi_b: power on SDHCI and USB HW modules" can be applied now. arch/arm/cpu/arm1176/bcm2835/mbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/cpu/arm1176/bcm2835/mbox.c index 4daf1e4..3b17a31 100644 --- a/arch/arm/cpu/arm1176/bcm2835/mbox.c +++ b/arch/arm/cpu/arm1176/bcm2835/mbox.c @@ -8,7 +8,7 @@ #include <asm/io.h> #include <asm/arch/mbox.h> -#define TIMEOUT (100 * 1000) /* 100mS in uS */ +#define TIMEOUT 1000 /* ms */ int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv) { -- 1.7.10.4

2 1

[U-Boot] [PATCH v2 1/4] spi:rewrite the Freescale DSPI driver.
by Chao Fu 16 Dec '13

16 Dec '13

From: Chao Fu <B44548(a)freescale.com> Freescale DSPI module is used on both the ColdFire platform and the ARM platform. The original DSPI driver is written for ColdFire platform only, this patch rewrite the driver to make it be used across the platforms. Some files, functions, variables and macros were changed accordingly for some ColdFire boards and Arm boards. The rewrite including the following changes: Rename the file name : cf_spi.c -> fsl_dspi.c Move the file: arch/m68k/include/asm/coldfire/dspi.h -> include/fsl_dspi.h Rename the functions and variables: cfxxx -> dspixxx Renamed macros: CONFIG_CF_DSPI -> CONFIG_FSL_DSPI Keep the following functions for ColdFire: cfspi_port_conf() cfspi_claim_bus() cfspi_release_bus() Add function for ColdFire: get_dspi_clk() Tested on board M54455EVB and VF610-twr. Signed-off-by: Chao Fu <B44548(a)freescale.com> --- arch/m68k/cpu/mcf5227x/cpu_init.c | 3 +- arch/m68k/cpu/mcf5227x/speed.c | 7 + arch/m68k/cpu/mcf52x2/speed.c | 7 + arch/m68k/cpu/mcf5445x/cpu_init.c | 3 +- arch/m68k/cpu/mcf5445x/speed.c | 7 + arch/m68k/include/asm/immap_5227x.h | 1 - arch/m68k/include/asm/immap_5301x.h | 1 - arch/m68k/include/asm/immap_5441x.h | 1 - arch/m68k/include/asm/immap_5445x.h | 1 - arch/m68k/include/asm/immap_547x_8x.h | 1 - drivers/spi/Makefile | 2 +- drivers/spi/{cf_spi.c => fsl_dspi.c} | 240 +++++++++++---------- include/configs/M52277EVB.h | 3 +- include/configs/M54418TWR.h | 3 +- include/configs/M54451EVB.h | 3 +- include/configs/M54455EVB.h | 3 +- .../asm/coldfire/dspi.h => include/fsl_dspi.h | 8 +- 17 files changed, 156 insertions(+), 138 deletions(-) rename drivers/spi/{cf_spi.c => fsl_dspi.c} (56%) rename arch/m68k/include/asm/coldfire/dspi.h => include/fsl_dspi.h (96%) diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c index 91b5fad..bd0b4ab 100644 --- a/arch/m68k/cpu/mcf5227x/cpu_init.c +++ b/arch/m68k/cpu/mcf5227x/cpu_init.c @@ -16,6 +16,7 @@ #include <asm/io.h> #include <asm/rtc.h> #include <linux/compiler.h> +#include <fsl_dspi.h> /* * Breath some life into the CPU... @@ -139,7 +140,7 @@ void uart_port_conf(int port) } } -#ifdef CONFIG_CF_DSPI +#ifdef CONFIG_FSL_DSPI void cfspi_port_conf(void) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; diff --git a/arch/m68k/cpu/mcf5227x/speed.c b/arch/m68k/cpu/mcf5227x/speed.c index 44de4a6..2bfff13 100644 --- a/arch/m68k/cpu/mcf5227x/speed.c +++ b/arch/m68k/cpu/mcf5227x/speed.c @@ -124,3 +124,10 @@ int get_clocks(void) return (0); } + +#ifdef CONFIG_FSL_DSPI +int get_dspi_clk(void) +{ + return gd->bus_clk; +} +#endif diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c index c5961d4..69b49c7 100644 --- a/arch/m68k/cpu/mcf52x2/speed.c +++ b/arch/m68k/cpu/mcf52x2/speed.c @@ -83,3 +83,10 @@ int get_clocks (void) return (0); } + +#ifdef CONFIG_FSL_DSPI +int get_dspi_clk(void) +{ + return gd->bus_clk; +} +#endif diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 9c324dc..bb7a4cd 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -16,6 +16,7 @@ #include <asm/rtc.h> #include <asm/io.h> #include <linux/compiler.h> +#include <fsl_dspi.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -423,7 +424,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear) } #endif -#ifdef CONFIG_CF_DSPI +#ifdef CONFIG_FSL_DSPI void cfspi_port_conf(void) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 07a9b35..29c858e 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -279,3 +279,10 @@ int get_clocks(void) return (0); } + +#ifdef CONFIG_FSL_DSPI +int get_dspi_clk(void) +{ + return gd->bus_clk; +} +#endif diff --git a/arch/m68k/include/asm/immap_5227x.h b/arch/m68k/include/asm/immap_5227x.h index 2cc4102..18a592e 100644 --- a/arch/m68k/include/asm/immap_5227x.h +++ b/arch/m68k/include/asm/immap_5227x.h @@ -51,7 +51,6 @@ #define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) #include <asm/coldfire/crossbar.h> -#include <asm/coldfire/dspi.h> #include <asm/coldfire/edma.h> #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h index 337fe73..6b19023 100644 --- a/arch/m68k/include/asm/immap_5301x.h +++ b/arch/m68k/include/asm/immap_5301x.h @@ -52,7 +52,6 @@ #define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000) #include <asm/coldfire/crossbar.h> -#include <asm/coldfire/dspi.h> #include <asm/coldfire/edma.h> #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h index 4db6145..62cb681 100644 --- a/arch/m68k/include/asm/immap_5441x.h +++ b/arch/m68k/include/asm/immap_5441x.h @@ -78,7 +78,6 @@ #define MMAP_GPIO 0xEC094000 #include <asm/coldfire/crossbar.h> -#include <asm/coldfire/dspi.h> #include <asm/coldfire/edma.h> #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_5445x.h b/arch/m68k/include/asm/immap_5445x.h index 2b12972..1525f9d 100644 --- a/arch/m68k/include/asm/immap_5445x.h +++ b/arch/m68k/include/asm/immap_5445x.h @@ -55,7 +55,6 @@ #include <asm/coldfire/ata.h> #include <asm/coldfire/crossbar.h> -#include <asm/coldfire/dspi.h> #include <asm/coldfire/edma.h> #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> diff --git a/arch/m68k/include/asm/immap_547x_8x.h b/arch/m68k/include/asm/immap_547x_8x.h index e1ce220..baa7779 100644 --- a/arch/m68k/include/asm/immap_547x_8x.h +++ b/arch/m68k/include/asm/immap_547x_8x.h @@ -41,7 +41,6 @@ #define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00) #define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000) -#include <asm/coldfire/dspi.h> #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> #include <asm/coldfire/flexcan.h> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 27902fe..a047f02 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o -obj-$(CONFIG_CF_SPI) += cf_spi.o +obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_CF_QSPI) += cf_qspi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o diff --git a/drivers/spi/cf_spi.c b/drivers/spi/fsl_dspi.c similarity index 56% rename from drivers/spi/cf_spi.c rename to drivers/spi/fsl_dspi.c index 879a809..47ac1f8 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/fsl_dspi.c @@ -1,10 +1,10 @@ /* - * * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * - * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2009, 2013 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * Chao Fu (B44548(a)freescale.com) * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,26 +12,28 @@ #include <common.h> #include <spi.h> #include <malloc.h> +#include <asm/io.h> +#include <fsl_dspi.h> + +#ifdef CONFIG_VF610 +#include <asm/arch/clock.h> +#endif + +#ifndef CONFIG_VF610 #include <asm/immap.h> +#endif -struct cf_spi_slave { +struct dspi_slave { struct spi_slave slave; + struct dspi *regs; uint baudrate; int charbit; }; -int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, - void *din, ulong flags); -struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode); -void cfspi_init(void); -void cfspi_tx(u32 ctrl, u16 data); -u16 cfspi_rx(void); - -extern void cfspi_port_conf(void); -extern int cfspi_claim_bus(uint bus, uint cs); -extern void cfspi_release_bus(uint bus, uint cs); - -DECLARE_GLOBAL_DATA_PTR; +static inline struct dspi_slave *to_dspi_spi(struct spi_slave *slave) +{ + return container_of(slave, struct dspi_slave, slave); +} #ifndef CONFIG_SPI_IDLE_VAL #if defined(CONFIG_SPI_MMC) @@ -41,77 +43,37 @@ DECLARE_GLOBAL_DATA_PTR; #endif #endif -#if defined(CONFIG_CF_DSPI) +#if defined(CONFIG_FSL_DSPI) /* DSPI specific mode */ #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000 -void cfspi_init(void) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - cfspi_port_conf(); /* port configuration */ - - dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 | - DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 | - DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 | - DSPI_MCR_CRXF | DSPI_MCR_CTXF; - - /* Default setting in platform configuration */ -#ifdef CONFIG_SYS_DSPI_CTAR0 - dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR1 - dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR2 - dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR3 - dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR4 - dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR5 - dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR6 - dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR7 - dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7; -#endif -} - -void cfspi_tx(u32 ctrl, u16 data) +static void dspi_tx(struct dspi_slave *dspislave, u32 ctrl, u16 data) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - while ((dspi->sr & 0x0000F000) >= 4) ; + while ((readl(&dspislave->regs->sr) & 0x0000F000) >= 4) + ; - dspi->tfr = (ctrl | data); + writel((ctrl | data), &dspislave->regs->tfr); } -u16 cfspi_rx(void) +static u16 dspi_rx(struct dspi_slave *dspislave) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + while ((readl(&dspislave->regs->sr) & 0x000000F0) == 0) + ; - while ((dspi->sr & 0x000000F0) == 0) ; - - return (dspi->rfr & 0xFFFF); + return (u16)(readl(&dspislave->regs->rfr) & 0xFFFF); } -int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, +int dspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, void *din, ulong flags) { - struct cf_spi_slave *cfslave = (struct cf_spi_slave *)slave; + struct dspi_slave *dspislave = to_dspi_spi(slave); u16 *spi_rd16 = NULL, *spi_wr16 = NULL; u8 *spi_rd = NULL, *spi_wr = NULL; static u32 ctrl = 0; uint len = bitlen >> 3; - if (cfslave->charbit == 16) { + if (dspislave->charbit == 16) { bitlen >>= 1; spi_wr16 = (u16 *) dout; spi_rd16 = (u16 *) din; @@ -129,19 +91,19 @@ int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, int tmp_len = len - 1; while (tmp_len--) { if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16++); + if (dspislave->charbit == 16) + dspi_tx(dspislave, ctrl, *spi_wr16++); else - cfspi_tx(ctrl, *spi_wr++); - cfspi_rx(); + dspi_tx(dspislave, ctrl, *spi_wr++); + dspi_rx(dspislave); } if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16++ = cfspi_rx(); + dspi_tx(dspislave, ctrl, CONFIG_SPI_IDLE_VAL); + if (dspislave->charbit == 16) + *spi_rd16++ = dspi_rx(dspislave); else - *spi_rd++ = cfspi_rx(); + *spi_rd++ = dspi_rx(dspislave); } } @@ -153,30 +115,30 @@ int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, if (len) { if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16); + if (dspislave->charbit == 16) + dspi_tx(dspislave, ctrl, *spi_wr16); else - cfspi_tx(ctrl, *spi_wr); - cfspi_rx(); + dspi_tx(dspislave, ctrl, *spi_wr); + dspi_rx(dspislave); } if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16 = cfspi_rx(); + dspi_tx(dspislave, ctrl, CONFIG_SPI_IDLE_VAL); + if (dspislave->charbit == 16) + *spi_rd16 = dspi_rx(dspislave); else - *spi_rd = cfspi_rx(); + *spi_rd = dspi_rx(dspislave); } } else { /* dummy read */ - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - cfspi_rx(); + dspi_tx(dspislave, ctrl, CONFIG_SPI_IDLE_VAL); + dspi_rx(dspislave); } return 0; } -struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode) +struct spi_slave *dspi_setup_slave(struct dspi_slave *dspislave, uint mode) { /* * bit definition for mode: @@ -191,7 +153,6 @@ struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode) * 11 - 8: Delay after transfer scaler * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST */ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; int prescaler[] = { 2, 3, 5, 7 }; int scaler[] = { 2, 4, 6, 8, @@ -200,21 +161,63 @@ struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode) 4096, 8192, 16384, 32768 }; int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; - int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed; + int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed, bus_clk; u32 bus_setup = 0; + dspislave->regs = (dspi_t *) MMAP_DSPI; + +#ifndef CONFIG_VF610 + cfspi_port_conf(); /* port configuration */ +#endif + + writel(DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 | + DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 | + DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 | + DSPI_MCR_CRXF | DSPI_MCR_CTXF, + &dspislave->regs->mcr); + /* Default setting in platform configuration */ +#ifdef CONFIG_SYS_DSPI_CTAR0 + writel(CONFIG_SYS_DSPI_CTAR0, &dspislave->regs->ctar[0]); +#endif +#ifdef CONFIG_SYS_DSPI_CTAR1 + writel(CONFIG_SYS_DSPI_CTAR1, &dspislave->regs->ctar[1]); +#endif +#ifdef CONFIG_SYS_DSPI_CTAR2 + writel(CONFIG_SYS_DSPI_CTAR2, &dspislave->regs->ctar[2]); +#endif +#ifdef CONFIG_SYS_DSPI_CTAR3 + writel(CONFIG_SYS_DSPI_CTAR3, &dspislave->regs->ctar[3]); +#endif +#ifdef CONFIG_SYS_DSPI_CTAR4 + writel(CONFIG_SYS_DSPI_CTAR4, &dspislave->regs->ctar[4]); +#endif +#ifdef CONFIG_SYS_DSPI_CTAR5 + writel(CONFIG_SYS_DSPI_CTAR5, &dspislave->regs->ctar[5]); +#endif +#ifdef CONFIG_SYS_DSPI_CTAR6 + writel(CONFIG_SYS_DSPI_CTAR6, &dspislave->regs->ctar[6]); +#endif +#ifdef CONFIG_SYS_DSPI_CTAR7 + writel(CONFIG_SYS_DSPI_CTAR7, &dspislave->regs->ctar[7]); +#endif + tmp = (prescaler[3] * scaler[15]); +#ifdef CONFIG_VF610 + bus_clk = mxc_get_clock(MXC_DSPI_CLK); +#else + bus_clk = get_dspi_clk(); +#endif /* Maximum and minimum baudrate it can handle */ - if ((cfslave->baudrate > (gd->bus_clk >> 1)) || - (cfslave->baudrate < (gd->bus_clk / tmp))) { + if ((dspislave->baudrate > (bus_clk >> 1)) || + (dspislave->baudrate < (bus_clk / tmp))) { printf("Exceed baudrate limitation: Max %d - Min %d\n", - (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp)); + (int)(bus_clk >> 1), (int)(bus_clk / tmp)); return NULL; } /* Activate Double Baud when it exceed 1/4 the bus clk */ if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) || - (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { + (dspislave->baudrate > (bus_clk / (prescaler[0] * scaler[0])))) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; } @@ -231,7 +234,8 @@ struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode) if ((mode & 0xF0000000) == 0) bus_setup |= - dspi->ctar[cfslave->slave.bus] & 0x78000000; + readl(&dspislave->regs->ctar[dspislave->slave.bus]) + & 0x78000000; else bus_setup |= ((mode & 0xF0000000) >> 1); @@ -246,25 +250,26 @@ struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode) bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */ bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */ } else - bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0); + bus_setup |= readl(&dspislave->regs->ctar[dspislave->slave.bus]) + & 0x78FCFFF0; - cfslave->charbit = - ((dspi->ctar[cfslave->slave.bus] & 0x78000000) == - 0x78000000) ? 16 : 8; + dspislave->charbit = + ((readl(&dspislave->regs->ctar[dspislave->slave.bus]) & 0x78000000) + == 0x78000000) ? 16 : 8; pbrcnt = sizeof(prescaler) / sizeof(int); brcnt = sizeof(scaler) / sizeof(int); /* baudrate calculation - to closer value, may not be exact match */ for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) { - baud_speed = gd->bus_clk / prescaler[i]; + baud_speed = bus_clk / prescaler[i]; for (j = 0; j < brcnt; j++) { tmp = (baud_speed / scaler[j]) * (1 + dbr); - if (tmp > cfslave->baudrate) - diff = tmp - cfslave->baudrate; + if (tmp > dspislave->baudrate) + diff = tmp - dspislave->baudrate; else - diff = cfslave->baudrate - tmp; + diff = dspislave->baudrate - tmp; if (diff < bestmatch) { bestmatch = diff; @@ -273,16 +278,12 @@ struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode) } } } - bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); - dspi->ctar[cfslave->slave.bus] = bus_setup; - return &cfslave->slave; + bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); + writel(bus_setup, &dspislave->regs->ctar[dspislave->slave.bus]) ; + return &dspislave->slave; } -#endif /* CONFIG_CF_DSPI */ - -#ifdef CONFIG_CF_QSPI -/* 52xx, 53xx */ -#endif /* CONFIG_CF_QSPI */ +#endif /* CONFIG_FSL_DSPI */ #ifdef CONFIG_CMD_SPI int spi_cs_is_valid(unsigned int bus, unsigned int cs) @@ -303,25 +304,22 @@ void spi_init_r(void) void spi_init(void) { - cfspi_init(); } struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { - struct cf_spi_slave *cfslave; + struct dspi_slave *dspislave; if (!spi_cs_is_valid(bus, cs)) return NULL; - - cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs); - if (!cfslave) + dspislave = spi_alloc_slave(struct dspi_slave, bus, cs); + if (!dspislave) return NULL; - cfslave->baudrate = max_hz; - + dspislave->baudrate = max_hz; /* specific setup */ - return cfspi_setup_slave(cfslave, mode); + return dspi_setup_slave(dspislave, mode); } void spi_free_slave(struct spi_slave *slave) @@ -331,17 +329,23 @@ void spi_free_slave(struct spi_slave *slave) int spi_claim_bus(struct spi_slave *slave) { +#ifdef CONFIG_VF610 + return 0; +#else return cfspi_claim_bus(slave->bus, slave->cs); +#endif } void spi_release_bus(struct spi_slave *slave) { +#ifndef CONFIG_VF610 cfspi_release_bus(slave->bus, slave->cs); +#endif } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - return cfspi_xfer(slave, bitlen, dout, din, flags); + return dspi_xfer(slave, bitlen, dout, din, flags); } #endif /* CONFIG_CMD_SPI */ diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index cde7305..485af4c 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -137,8 +137,7 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ -#define CONFIG_CF_SPI -#define CONFIG_CF_DSPI +#define CONFIG_FSL_DSPI #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 #ifdef CONFIG_CMD_SPI diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index de063b7..d8bb8cd 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -207,8 +207,7 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ -#define CONFIG_CF_SPI -#define CONFIG_CF_DSPI +#define CONFIG_FSL_DSPI #define CONFIG_SERIAL_FLASH #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 0f4b726..7141601 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -148,8 +148,7 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ -#define CONFIG_CF_SPI -#define CONFIG_CF_DSPI +#define CONFIG_FSL_DSPI #define CONFIG_SERIAL_FLASH #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 7a55d3c..15b7c40 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -181,8 +181,7 @@ #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* DSPI and Serial Flash */ -#define CONFIG_CF_SPI -#define CONFIG_CF_DSPI +#define CONFIG_FSL_DSPI #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x13 #ifdef CONFIG_CMD_SPI diff --git a/arch/m68k/include/asm/coldfire/dspi.h b/include/fsl_dspi.h similarity index 96% rename from arch/m68k/include/asm/coldfire/dspi.h rename to include/fsl_dspi.h index fda7138..36a352e 100644 --- a/arch/m68k/include/asm/coldfire/dspi.h +++ b/include/fsl_dspi.h @@ -1,8 +1,9 @@ /* - * MCF5227x Internal Memory Map + * Freescale DSPI Module Defines * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2013 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * Chao Fu (B44548(a)freesacle.com) * * SPDX-License-Identifier: GPL-2.0+ */ @@ -19,8 +20,7 @@ typedef struct dspi { u32 sr; /* 0x2C */ u32 irsr; /* 0x30 */ u32 tfr; /* 0x34 - PUSHR */ - u16 resv1; /* 0x38 */ - u16 rfr; /* 0x3A - POPR */ + u32 rfr; /* 0x38 - POPR */ #ifdef CONFIG_MCF547x_8x u32 tfdr[4]; /* 0x3C */ u8 resv2[0x30]; /* 0x40 */ -- 1.8.4

3 6

[U-Boot] booting issue with Atmel SAMA5D31 Evaluation kit
by Ron Eggler 16 Dec '13

16 Dec '13

Hi, I got a SAMA5D31 evaluation kit here, it came with some default application. I started reading through the getting started guide and immediately tried to load my own image - MISTAKE! I started playing around with u-boot trying to get an image from my tftp server loaded but now i realize, that I can't get it to hook up to my LAN. Bad! Because it won't even let me boot the original application anymore. When I boot it and my variables look like this: ... ... Warning: failed to set MAC address Hit any key to stop autoboot: 0 macb0: PHY present at 0 macb0: Starting autonegotiation... macb0: Autonegotiation timed out (status=0x7849) macb0: link down (status: 0x7849) macb0: PHY present at 0 macb0: Starting autonegotiation... macb0: Autonegotiation timed out (status=0x7849) macb0: link down (status: 0x7849) Wrong Image Format for bootm command ERROR: can't get kernel image! U-Boot> printenv baudrate=115200 bootargs=console=ttyS0,115200 ip=${ipaddr} root=/dev/nfs rw nfsroot=${serverip}:/full/path/to/rfs bootcmd=tftp;tftp 21000000 sama5d3x_ek.dtbbootm 22000000 - 21000000 bootdelay=1 bootfile=uImage-3.6-ts-armv7l ethact=macb0 ipaddr=192.168.1.122 loadaddr=22000000 serverip=192.168.1.121 stderr=serial stdin=serial stdout=serial Environment size: 367/131067 bytes U-Boot> What can I do to at least get it to boot the default program again? Thanks, Ron -- *ron eggler | semios | senior software engineer* 320 - 887 Great Northern Way | Vancouver, BC | V5T 4T5 T | 604 229 2044 ext 105[1] C | 778 230 9442[2] E | reggler(a)semios.com[3] smart farming[4] twitter[5] linkedin[6] -------- [1] tel:604%20229%202044%20ext%20105 [2] tel:778%20230%209442 [3] mailto:reggler@semios.com [4] http://www.semios.com [5] https://twitter.com/semios [6] http://www.linkedin.com/company/semiosbio-technologies-inc?goback=%2Enmp_*1…

4 7

[U-Boot] Improve upstream support for Snowball board
by Roy Spliet 15 Dec '13

15 Dec '13

Patches are loosely based on the tree maintained by Calao. FDT confirmed working, LAN is successfully detected by u-boot (but lacking a proper tftp setup this is untested). Upstream U-Boot still has one bug that prevents booting from eMMC. Easiest workaround is to revert e95504497ecac46907204b0ee3460b708a2981ac mmc: Split device init to decouple OCR-polling delay until I (or someone else) has time to device a proper fix. This doesn't prevent anyone from pushing these two patches though.

2 5

[U-Boot] [PATCH 0/2] Add usb eth support
by Inderpal Singh 14 Dec '13

14 Dec '13

From: Chander Kashyap <chander.kashyap(a)linaro.org> Arndale board has AX88760, which is USB 2.0 Hub & USB 2.0 Ethernet Combo controller, connected to HSIC Phy of USB host controller via USB3503 hub. This patchset add support for this usb ethernet controllor. Chander Kashyap (1): exynos5: arndale: Add network support Inderpal Singh (1): usb: ehci: exynos: set/reset hsic phys arch/arm/include/asm/arch-exynos/ehci.h | 14 +++++++++ board/samsung/arndale/arndale.c | 23 +++++++++++++++ drivers/usb/host/ehci-exynos.c | 48 +++++++++++++++++++++++++++++++ include/configs/arndale.h | 6 ++++ 4 files changed, 91 insertions(+) -- 1.7.9.5

5 11

[U-Boot] [PATCH] i2c: Fix i2c speed command
by Darwin Rambo 14 Dec '13

14 Dec '13

This corrects i2c core to interpret the value returned by i2c_set_bus_speed as a success indicator rather than the actual speed that was set. When i2c_set_bus_speed returns a failure code, the speed is unknown so the adapter speed is set to zero. Signed-off-by: Darwin Rambo <drambo(a)broadcom.com> Reviewed-by: Tim Kryger <tim.kryger(a)linaro.org> Reviewed-by: Steve Rae <srae(a)broadcom.com> --- drivers/i2c/i2c_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index e1767f4..18d6736 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -349,7 +349,7 @@ unsigned int i2c_set_bus_speed(unsigned int speed) return 0; ret = I2C_ADAP->set_bus_speed(I2C_ADAP, speed); if (gd->flags & GD_FLG_RELOC) - I2C_ADAP->speed = ret; + I2C_ADAP->speed = (ret == 0) ? speed : 0; return ret; } -- 1.7.9.5

2 1

Re: [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
by Scott Wood 14 Dec '13

14 Dec '13

On Fri, 2013-12-13 at 21:09 -0600, Liu Po-B43644 wrote: > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Saturday, December 14, 2013 4:26 AM > > To: Liu Po-B43644 > > Cc: u-boot(a)lists.denx.de; Sun York-R58495; Kushwaha Prabhakar-B32579 > > Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot > > support base on TPL/SPL > > > > On Wed, 2013-12-11 at 00:16 -0600, Liu Po-B43644 wrote: > > > > > SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, > > CONFIG_SYS_NAND_BASE_PHYS, > > > > > - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > > > > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > > > > 0, 5, BOOKE_PAGESZ_64K, 1), > > > > > > > > No. > > > Without MAS3_SX, the board can't run in booting from NAND. > > > > Explain why you're executing from this TLB entry. This should be for > > accessing the NAND as I/O after you've relocated away from the boot > > buffer. There should be a different mapping for the boot buffer early on. > > None of the other NAND boot targets have needed this. Perhaps this is > > related to the other TLB entry that you said you could work without. > This is because for SPL, the > #define CONFIG_SPL_TEXT_BASE 0xff800000 > #define CONFIG_SYS_NAND_BASE 0xff800000 > Code space overlap the nand io space. OK, I guess we move the NAND buffer before relocating out of it. And for some reason I missed that existing targets do the same thing. Never mind... -Scott

1 0

[U-Boot] [U-Boot v2] [PATCH] rsa: add a more flexible way to support different hash algorithms (e.g. sha256)
by andreas＠oetken.name 13 Dec '13

13 Dec '13

As proposed by Heiko I made some small changes and verified the patch with the checkpatch-script. >From 169f40e72fceb222bb15dd59c1337f42371e97a5 Mon Sep 17 00:00:00 2001 From: Andreas Oetken <andreas.oetken(a)siemens.com> Date: Wed, 27 Nov 2013 13:09:19 +0100 Subject: [PATCH] Added rsa-sha256 support. Signed-off-by: Andreas Oetken <andreas.oetken(a)siemens.com> --- common/image-sig.c | 33 +++++++++++++ include/image.h | 20 +++++++- include/rsa-checksum.h | 25 ++++++++++ include/rsa.h | 17 +++++++ lib/rsa/Makefile | 2 +- lib/rsa/rsa-checksum.c | 108 +++++++++++++++++++++++++++++++++++++++++++ lib/rsa/rsa-sign.c | 10 ++-- lib/rsa/rsa-verify.c | 80 +++++++++----------------------- test/vboot/sign-configs.its | 2 +- test/vboot/sign-images.its | 2 +- 10 files changed, 233 insertions(+), 66 deletions(-) create mode 100644 include/rsa-checksum.h create mode 100644 lib/rsa/rsa-checksum.c diff --git a/common/image-sig.c b/common/image-sig.c index 973b06d..5ce6b80 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -14,15 +14,48 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* !USE_HOSTCC*/ #include <image.h> #include <rsa.h> +#include <rsa-checksum.h> #define IMAGE_MAX_HASHED_NODES 100 + +struct image_hash_algo image_hash_algos[] = { + { + "sha1", + SHA1_SUM_LEN, +#if IMAGE_ENABLE_SIGN + EVP_sha1, +#else + sha1_calculate, + padding_sha1_rsa2048, +#endif + }, + { + "sha256", + SHA256_SUM_LEN, +#if IMAGE_ENABLE_SIGN + EVP_sha256, +#else + sha256_calculate, + padding_sha256_rsa2048, +#endif + } +}; + struct image_sig_algo image_sig_algos[] = { { "sha1,rsa2048", rsa_sign, rsa_add_verify_data, rsa_verify, + &image_hash_algos[0], + }, + { + "sha256,rsa2048", + rsa_sign, + rsa_add_verify_data, + rsa_verify, + &image_hash_algos[1], } }; diff --git a/include/image.h b/include/image.h index ee6eb8d..1f7ca61 100644 --- a/include/image.h +++ b/include/image.h @@ -822,7 +822,8 @@ int calculate_hash(const void *data, int data_len, const char *algo, # ifdef USE_HOSTCC # define IMAGE_ENABLE_SIGN 1 # define IMAGE_ENABLE_VERIFY 0 -#else +# include <openssl/evp.h> +# else # define IMAGE_ENABLE_SIGN 0 # define IMAGE_ENABLE_VERIFY 1 # endif @@ -861,6 +862,20 @@ struct image_region { int size; }; +struct image_hash_algo { + const char *name; + const int checksum_len; +#if IMAGE_ENABLE_SIGN + EVP_MD *(*calculate)(void); +#else +#if IMAGE_ENABLE_VERIFY + void (*calculate)(const struct image_region region[], + int region_count, uint8_t *checksum); + const uint8_t *rsa_padding; +#endif +#endif +}; + struct image_sig_algo { const char *name; /* Name of algorithm */ @@ -911,6 +926,9 @@ struct image_sig_algo { int (*verify)(struct image_sign_info *info, const struct image_region region[], int region_count, uint8_t *sig, uint sig_len); + + /* pointer to hash algorithm */ + struct image_hash_algo *hash_algo; }; /** diff --git a/include/rsa-checksum.h b/include/rsa-checksum.h new file mode 100644 index 0000000..d2c6474 --- /dev/null +++ b/include/rsa-checksum.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2013, Andreas Oetken. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _RSA_CHECKSUM_H +#define _RSA_CHECKSUM_H + +#include <errno.h> +#include <image.h> +#include <sha1.h> +#include <sha256.h> + +#if IMAGE_ENABLE_VERIFY +extern const uint8_t padding_sha256_rsa2048[]; +extern const uint8_t padding_sha1_rsa2048[]; + +void sha256_calculate(const struct image_region region[], + int region_count, uint8_t *checksum); +void sha1_calculate(const struct image_region region[], + int region_count, uint8_t *checksum); +#endif + +#endif diff --git a/include/rsa.h b/include/rsa.h index add4c78..12ae443 100644 --- a/include/rsa.h +++ b/include/rsa.h @@ -15,6 +15,23 @@ #include <errno.h> #include <image.h> +#define RSA2048_BYTES (2048 / 8) + +/** + * struct rsa_public_key - holder for a public key + * + * An RSA public key consists of a modulus (typically called N), the inverse + * and R^2, where R is 2^(# key bits). + */ + +struct rsa_public_key { + uint len; /* Length of modulus[] in number of uint32_t */ + uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */ + uint32_t *modulus; /* modulus as little endian array */ + uint32_t *rr; /* R^2 as little endian array */ +}; + + #if IMAGE_ENABLE_SIGN /** * sign() - calculate and return signature for given input data diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile index 164ab39..a5a96cb6 100644 --- a/lib/rsa/Makefile +++ b/lib/rsa/Makefile @@ -7,4 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o +obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o diff --git a/lib/rsa/rsa-checksum.c b/lib/rsa/rsa-checksum.c new file mode 100644 index 0000000..e75abb8 --- /dev/null +++ b/lib/rsa/rsa-checksum.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013, Andreas Oetken. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <rsa.h> +#include <sha1.h> +#include <sha256.h> +#include <asm/byteorder.h> +#include <asm/errno.h> +#include <asm/unaligned.h> + + +/* PKCS 1.5 paddings as described in the RSA PKCS#1 v2.1 standard. */ + + +const uint8_t padding_sha256_rsa2048[RSA2048_BYTES - SHA256_SUM_LEN] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x31, 0x30, + 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, + 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 +}; + +const uint8_t padding_sha1_rsa2048[RSA2048_BYTES - SHA1_SUM_LEN] = { + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x21, 0x30, + 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, 0x02, 0x1a, + 0x05, 0x00, 0x04, 0x14 +}; + + +void sha1_calculate(const struct image_region region[], + int region_count, uint8_t *checksum) +{ + sha1_context ctx; + uint32_t i; + + sha1_starts(&ctx); + for (i = 0; i < region_count; i++) + sha1_update(&ctx, region[i].data, region[i].size); + sha1_finish(&ctx, checksum); +} + +void sha256_calculate(const struct image_region region[], + int region_count, uint8_t *checksum) +{ + sha256_context ctx; + uint32_t i; + + sha256_starts(&ctx); + for (i = 0; i < region_count; i++) + sha256_update(&ctx, region[i].data, region[i].size); + sha256_finish(&ctx, checksum); +} + diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 549130e..e3b8790 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -159,8 +159,9 @@ static void rsa_remove(void) EVP_cleanup(); } -static int rsa_sign_with_key(RSA *rsa, const struct image_region region[], - int region_count, uint8_t **sigp, uint *sig_size) +static int rsa_sign_with_key(RSA *rsa, struct image_hash_algo *hash_algo, + const struct image_region region[], + int region_count, uint8_t **sigp, uint *sig_size) { EVP_PKEY *key; EVP_MD_CTX *context; @@ -192,7 +193,7 @@ static int rsa_sign_with_key(RSA *rsa, const struct image_region region[], goto err_create; } EVP_MD_CTX_init(context); - if (!EVP_SignInit(context, EVP_sha1())) { + if (!EVP_SignInit(context, hash_algo->calculate())) { ret = rsa_err("Signer setup failed"); goto err_sign; } @@ -242,7 +243,8 @@ int rsa_sign(struct image_sign_info *info, ret = rsa_get_priv_key(info->keydir, info->keyname, &rsa); if (ret) goto err_priv; - ret = rsa_sign_with_key(rsa, region, region_count, sigp, sig_len); + ret = rsa_sign_with_key(rsa, info->algo->hash_algo, + region, region_count, sigp, sig_len); if (ret) goto err_sign; diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 02cc4e3..9a42641 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -7,28 +7,14 @@ #include <common.h> #include <fdtdec.h> #include <rsa.h> -#include <sha1.h> #include <asm/byteorder.h> #include <asm/errno.h> #include <asm/unaligned.h> -/** - * struct rsa_public_key - holder for a public key - * - * An RSA public key consists of a modulus (typically called N), the inverse - * and R^2, where R is 2^(# key bits). - */ -struct rsa_public_key { - uint len; /* Length of modulus[] in number of uint32_t */ - uint32_t n0inv; /* -1 / modulus[0] mod 2^32 */ - uint32_t *modulus; /* modulus as little endian array */ - uint32_t *rr; /* R^2 as little endian array */ -}; +#define MAXIMUM_CHECKSUM_LEN 512 #define UINT64_MULT32(v, multby) (((uint64_t)(v)) * ((uint32_t)(multby))) -#define RSA2048_BYTES (2048 / 8) - /* This is the minimum/maximum key size we support, in bits */ #define RSA_MIN_KEY_BITS 2048 #define RSA_MAX_KEY_BITS 2048 @@ -36,38 +22,6 @@ struct rsa_public_key { /* This is the maximum signature length that we support, in bits */ #define RSA_MAX_SIG_BITS 2048 -static const uint8_t padding_sha1_rsa2048[RSA2048_BYTES - SHA1_SUM_LEN] = { - 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0x21, 0x30, - 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03, 0x02, 0x1a, - 0x05, 0x00, 0x04, 0x14 -}; /** * subtract_modulus() - subtract modulus from the given value @@ -209,7 +163,8 @@ static int pow_mod(const struct rsa_public_key *key, uint32_t *inout) } static int rsa_verify_key(const struct rsa_public_key *key, const uint8_t *sig, - const uint32_t sig_len, const uint8_t *hash) + const uint32_t sig_len, const uint8_t *hash, + struct image_hash_algo *hash_algo) { const uint8_t *padding; int pad_len; @@ -223,6 +178,8 @@ static int rsa_verify_key(const struct rsa_public_key *key, const uint8_t *sig, return -EINVAL; } + debug("Hash-algorithm: %s", hash_algo->name); + /* Sanity check for stack size */ if (sig_len > RSA_MAX_SIG_BITS / 8) { debug("Signature length %u exceeds maximum %d\n", sig_len, @@ -239,8 +196,8 @@ static int rsa_verify_key(const struct rsa_public_key *key, const uint8_t *sig, return ret; /* Determine padding to use depending on the signature type. */ - padding = padding_sha1_rsa2048; - pad_len = RSA2048_BYTES - SHA1_SUM_LEN; + padding = hash_algo->rsa_padding; + pad_len = RSA2048_BYTES - hash_algo->checksum_len; /* Check pkcs1.5 padding bytes. */ if (memcmp(buf, padding, pad_len)) { @@ -309,7 +266,7 @@ static int rsa_verify_with_keynode(struct image_sign_info *info, } debug("key length %d\n", key.len); - ret = rsa_verify_key(&key, sig, sig_len, hash); + ret = rsa_verify_key(&key, sig, sig_len, hash, info->algo->hash_algo); if (ret) { printf("%s: RSA failed to verify: %d\n", __func__, ret); return ret; @@ -323,12 +280,21 @@ int rsa_verify(struct image_sign_info *info, uint8_t *sig, uint sig_len) { const void *blob = info->fdt_blob; - uint8_t hash[SHA1_SUM_LEN]; + /* Reserve memory for a maximum checksum-length of 512 bytes */ + uint8_t hash[MAXIMUM_CHECKSUM_LEN]; int ndepth, noffset; int sig_node, node; char name[100]; - sha1_context ctx; - int ret, i; + int ret; + + /* Verify that checksum-length is lower than MAXIMUM_CHECKSUM_LEN */ + if (info->algo->hash_algo->checksum_len > MAXIMUM_CHECKSUM_LEN) { + debug("%s: invlaid checksum-length %s, a maximum \ + of %d is currently set.\n", + __func__, info->algo->hash_algo->name, + MAXIMUM_CHECKSUM_LEN); + return -EINVAL; + } sig_node = fdt_subnode_offset(blob, 0, FIT_SIG_NODENAME); if (sig_node < 0) { @@ -336,10 +302,8 @@ int rsa_verify(struct image_sign_info *info, return -ENOENT; } - sha1_starts(&ctx); - for (i = 0; i < region_count; i++) - sha1_update(&ctx, region[i].data, region[i].size); - sha1_finish(&ctx, hash); + /* Calculate checksum with checksum-algorithm */ + info->algo->hash_algo->calculate(region, region_count, hash); /* See if we must use a particular key */ if (info->required_keynode != -1) { diff --git a/test/vboot/sign-configs.its b/test/vboot/sign-configs.its index db2ed79..5b315f3 100644 --- a/test/vboot/sign-configs.its +++ b/test/vboot/sign-configs.its @@ -36,7 +36,7 @@ kernel = "kernel@1"; fdt = "fdt@1"; signature@1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; sign-images = "fdt", "kernel"; }; diff --git a/test/vboot/sign-images.its b/test/vboot/sign-images.its index f69326a..e2b0446 100644 --- a/test/vboot/sign-images.its +++ b/test/vboot/sign-images.its @@ -27,7 +27,7 @@ compression = "none"; fdt-version = <1>; signature@1 { - algo = "sha1,rsa2048"; + algo = "sha256,rsa2048"; key-name-hint = "dev"; }; }; -- 1.7.10.4

3 2

Re: [U-Boot] [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot support base on TPL/SPL
by Po.Liu＠freescale.com 13 Dec '13

13 Dec '13

Sorry for late reply since the email system crash. > -----Original Message----- > From: Scott Wood [mailto:scottwood@freescale.com] > Sent: Saturday, December 07, 2013 9:22 AM > To: Liu Po-B43644 > Cc: u-boot(a)lists.denx.de; Sun York-R58495; Kushwaha Prabhakar-B32579 > Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot > support base on TPL/SPL > > On Thu, 2013-12-05 at 14:19 +0800, Po Liu wrote: > > diff --git a/board/freescale/c29xpcie/spl.c > > b/board/freescale/c29xpcie/spl.c new file mode 100644 index > > 0000000..7bc8ce1 > > --- /dev/null > > +++ b/board/freescale/c29xpcie/spl.c > > @@ -0,0 +1,73 @@ > > +/* Copyright 2013 Freescale Semiconductor, Inc. > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + */ > > + > > +#include <common.h> > > +#include <ns16550.h> > > +#include <malloc.h> > > +#include <mmc.h> > > +#include <nand.h> > > +#include <i2c.h> > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +ulong get_effective_memsize(void) > > +{ > > + return CONFIG_SYS_L2_SIZE; > > +} > > + > > +void board_init_f(ulong bootflag) > > +{ > > + u32 plat_ratio; > > + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; > > + > > + console_init_f(); > > + > > + /* initialize selected port with appropriate baud rate */ > > + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; > > + plat_ratio >>= 1; > > + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; > > + > > + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, > > + gd->bus_clk / 16 / CONFIG_BAUDRATE); > > + > > + /* copy code to RAM and jump to it - this should not return */ > > + /* NOTE - code has to be copied out of NAND buffer before > > + * other blocks can be read. > > + */ > > + relocate_code(CONFIG_SPL_RELOC_STACK, 0, > > +CONFIG_SPL_RELOC_TEXT_BASE); } > > + > > +void board_init_r(gd_t *gd, ulong dest_addr) { > > + /* Pointer is writable since we allocated a register for it */ > > + gd = (gd_t *)CONFIG_SPL_GD_ADDR; > > + bd_t *bd; > > + > > + memset(gd, 0, sizeof(gd_t)); > > + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); > > + memset(bd, 0, sizeof(bd_t)); > > + gd->bd = bd; > > + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; > > + bd->bi_memsize = CONFIG_SYS_L2_SIZE; > > + > > + probecpu(); > > + get_clocks(); > > + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, > > + CONFIG_SPL_RELOC_MALLOC_SIZE); > > + > > + /* relocate environment function pointers etc. */ > > + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, > > + (uchar *)CONFIG_ENV_ADDR); > > + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); > > + gd->env_valid = 1; > > + > > + i2c_init_all(); > > + > > + gd->ram_size = initdram(0); > > + > > + puts("\nTertiary program loader running in sram..."); > > Why do you assume tertiary? Couldn't this be SPL for SD/SPI? Or was it > a copy/paste error that you added things to the board config file for > SD/SPI (after all, the subject line says it's a NAND patch)? > Yes, I assume this patch only for NAND boot for C29XPCIE. > > +void board_init_r(gd_t *gd, ulong dest_addr) { > > + puts("\nSecond program loader running in sram..."); > > I see that this isn't new to this patch, but we ought to be consistent > and either change this to "secondary", or change "tertiary" to "third". > > It's also probably too verbose... Simply saying "SPL\n" or "TPL\n" > would suffice to indicate progress and verify that console output is > working (if nothing is printed, then that path doesn't get tested in the > absence of a load error). > > > diff --git a/board/freescale/c29xpcie/tlb.c > > b/board/freescale/c29xpcie/tlb.c index 84844ee..11f8a37 100644 > > --- a/board/freescale/c29xpcie/tlb.c > > +++ b/board/freescale/c29xpcie/tlb.c > > @@ -26,10 +26,20 @@ struct fsl_e_tlb_entry tlb_table[] = { > > 0, 0, BOOKE_PAGESZ_4K, 0), > > > > /* TLB 1 */ > > +#ifdef CONFIG_SPL_NAND_MINIMAL > > + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, > > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > + 0, 10, BOOKE_PAGESZ_4K, 1), > > + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, > > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > + 0, 11, BOOKE_PAGESZ_4K, 1), > > +#endif > > CONFIG_SPL_NAND_MINIMAL should not exist. It was introduced by accident > after a different approach was chosen in patch review (and even then, > this wasn't what it meant). > > Prabhakar, why did you extend that to other uses? Why are both entries > ifdeffed here, but only the 0xffffe000 entry on existing boards? > > If this needs to be ifdeffed (and it probably does, if only to avoid > possible speculative instruction fetches), use (and document) > CONFIG_SPL_NAND_BOOT. I'll replace the CONFIG_SPL_NAND_MINIMAL with CONFIG_SPL_NAND_BOOT > > > SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, > > - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > 0, 5, BOOKE_PAGESZ_64K, 1), > > No. > > > SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, @@ -61,7 +72,8 @@ > > struct fsl_e_tlb_entry tlb_table[] = { > > MAS3_SX|MAS3_SW|MAS3_SR, 0, > > 0, 7, BOOKE_PAGESZ_256K, 1), > > > > -#ifdef CONFIG_SYS_RAMBOOT > > +#if defined(CONFIG_SYS_RAMBOOT) || (defined(CONFIG_SPL) \ > > + && !defined(CONFIG_SPL_COMMON_INIT_DDR)) > > SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, > > CONFIG_SYS_DDR_SDRAM_BASE, > > MAS3_SX|MAS3_SW|MAS3_SR, 0, > > This will have the result of mapping DDR in the SPL where it's not used, > but not in the TPL where it is. Just define: #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) ? I think code load image to SRAM from NAND for SPL and DDR do not need to be allocate. > > -Scott > >

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