December 2013 - U-Boot

[U-Boot] [PATCH] net/designware: make driver compatible with data cache
by Alexey Brodkin 24 Dec '13

24 Dec '13

Up until now this driver only worked with data cache disabled. To make it work with enabled data cache following changes were required: * Implement all accesses to shared structures between CPU and GMAC via uncached reads/writes ("readl"/"writel"). * Flush cache for data passed from CPU to GMAC * Invalidate cache for data passed from GMAC to CPU I tried to implement items above keeping as much code unchanged as possible. So logic of operation is kept as it is. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Vipin Kumar <vipin.kumar(a)st.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Mischa Jonker <mjonker(a)synopsys.com> --- drivers/net/designware.c | 91 ++++++++++++++++++++++++++++++------------------ 1 file changed, 58 insertions(+), 33 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 22155b4..04ae02c 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -30,26 +30,30 @@ static void tx_descs_init(struct eth_device *dev) for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; - desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; - desc_p->dmamac_next = &desc_table_p[idx + 1]; + writel(&txbuffs[idx * CONFIG_ETH_BUFSIZE], + &desc_p->dmamac_addr); + writel(&desc_table_p[idx + 1], &desc_p->dmamac_next); #if defined(CONFIG_DW_ALTDESCRIPTOR) - desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | - DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ - DESC_TXSTS_TXCHECKINSCTRL | \ - DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); - - desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; - desc_p->dmamac_cntl = 0; - desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); + writel(readl(&desc_p->txrx_status) & ~(DESC_TXSTS_TXINT | + DESC_TXSTS_TXLAST | DESC_TXSTS_TXFIRST | + DESC_TXSTS_TXCRCDIS | DESC_TXSTS_TXCHECKINSCTRL | + DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS), + &desc_p->txrx_status); + + writel(readl(&desc_p->txrx_status) | DESC_TXSTS_TXCHAIN, + &desc_p->txrx_status); + writel(0, &desc_p->dmamac_cntl); + writel(readl(&desc_p->txrx_status) & ~(DESC_TXSTS_MSK | + DESC_TXSTS_OWNBYDMA), &desc_p->txrx_status); #else - desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; - desc_p->txrx_status = 0; + writel(DESC_TXCTRL_TXCHAIN, &desc_p->dmamac_cntl); + writel(0, &desc_p->txrx_status); #endif } /* Correcting the last pointer of the chain */ - desc_p->dmamac_next = &desc_table_p[0]; + writel(&desc_table_p[0], &desc_p->dmamac_next); writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); } @@ -63,20 +67,30 @@ static void rx_descs_init(struct eth_device *dev) struct dmamacdescr *desc_p; u32 idx; + /* Before passing buffers to GMAC we need to make sure zeros + * written there right after "priv" structure allocation were + * flushed into RAM. + * Otherwise there's a chance to get some of them flushed in RAM when + * GMAC is already pushing data to RAM via DMA. This way incoming from + * GMAC data will be corrupted. */ + flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + + RX_TOTAL_BUFSIZE); + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; - desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; - desc_p->dmamac_next = &desc_table_p[idx + 1]; - desc_p->dmamac_cntl = - (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ - DESC_RXCTRL_RXCHAIN; + writel(&rxbuffs[idx * CONFIG_ETH_BUFSIZE], + &desc_p->dmamac_addr); + writel(&desc_table_p[idx + 1], &desc_p->dmamac_next); + + writel((MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | + DESC_RXCTRL_RXCHAIN, &desc_p->dmamac_cntl); - desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; + writel(DESC_RXSTS_OWNBYDMA, &desc_p->txrx_status); } /* Correcting the last pointer of the chain */ - desc_p->dmamac_next = &desc_table_p[0]; + writel(&desc_table_p[0], &desc_p->dmamac_next); writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); } @@ -198,26 +212,32 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; /* Check if the descriptor is owned by CPU */ - if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { + if (readl(&desc_p->txrx_status) & DESC_TXSTS_OWNBYDMA) { printf("CPU not owner of tx frame\n"); return -1; } memcpy((void *)desc_p->dmamac_addr, packet, length); -#if defined(CONFIG_DW_ALTDESCRIPTOR) - desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; - desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ - DESC_TXCTRL_SIZE1MASK; + flush_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + length); - desc_p->txrx_status &= ~(DESC_TXSTS_MSK); - desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; +#if defined(CONFIG_DW_ALTDESCRIPTOR) + writel(readl(&desc_p->txrx_status) | DESC_TXSTS_TXFIRST | + DESC_TXSTS_TXLAST, &desc_p->txrx_status); + writel(readl(&desc_p->dmamac_cntl) | (length << DESC_TXCTRL_SIZE1SHFT) & + DESC_TXCTRL_SIZE1MASK, &desc_p->dmamac_cntl); + + writel(readl(&desc_p->txrx_status) & ~DESC_TXSTS_MSK, + &desc_p->txrx_status); + writel(readl(&desc_p->txrx_status) | DESC_TXSTS_OWNBYDMA, + &desc_p->txrx_status); #else - desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ - DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ - DESC_TXCTRL_TXFIRST; + writel(readl(&desc_p->dmamac_cntl) | + ((length << DESC_TXCTRL_SIZE1SHFT) & DESC_TXCTRL_SIZE1MASK) | + DESC_TXCTRL_TXLAST | DESC_TXCTRL_TXFIRST, &desc_p->dmamac_cntl); - desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; + writel(DESC_TXSTS_OWNBYDMA, &desc_p->txrx_status); #endif /* Test the wrap-around condition. */ @@ -238,7 +258,7 @@ static int dw_eth_recv(struct eth_device *dev) u32 desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; - u32 status = desc_p->txrx_status; + u32 status = readl(&desc_p->txrx_status); int length = 0; /* Check if the owner is the CPU */ @@ -247,13 +267,18 @@ static int dw_eth_recv(struct eth_device *dev) length = (status & DESC_RXSTS_FRMLENMSK) >> \ DESC_RXSTS_FRMLENSHFT; + invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + + length); + NetReceive(desc_p->dmamac_addr, length); /* * Make the current descriptor valid again and go to * the next one */ - desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + writel(readl(&desc_p->txrx_status) | DESC_RXSTS_OWNBYDMA, + &desc_p->txrx_status); /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) -- 1.8.4.2

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[U-Boot] [PATCH 0/2] usb: gadget: fotg210: workaround & new hardware support
by Kuo-Jung Su 24 Dec '13

24 Dec '13

From: Kuo-Jung Su <dantesu(a)faraday-tech.com> 1. It's known that EP0 fifo empty indication is not reliable, an extra delay is necessary to avoid data corruption while handling packets with size greater than 64 bytes. 2. Since hardware revision 1.11.0, some fields of interrupt status registers are now write-1-clear. Kuo-Jung Su (2): usb: gadget: fotg210: add w1c interrupt status support usb: gadget: fotg210: EP0 fifo empty indication is non-reliable drivers/usb/gadget/fotg210.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH 2/2] vexpress: Add vexpress qemu variant
by Ian Campbell 23 Dec '13

23 Dec '13

The main purpose of this is to disable the use of the virtualisation extensions which Qemu does not emulate. Also enable a few additional commands and the u-boot API. This works for me with: $ dd if=/dev/zero of=pflash0.img bs=1M count=64 $ dd if=/dev/zero of=pflash1.img bs=1M count=64 $ qemu-system-arm -M vexpress-a15 -cpu cortex-a15 -kernel u-boot -m 1024m -sd mmc.img -nographic -pflash pflash0.img -pflash pflash1.img (for some reason both pflash images are needed for saveenv to work) Signed-off-by: Ian Campbell <ijc(a)hellion.org.uk> Cc: albert.u.boot(a)aribaud.net --- boards.cfg | 1 + include/configs/vexpress_ca15_tc2.h | 2 ++ include/configs/vexpress_common.h | 4 ++++ 3 files changed, 7 insertions(+) diff --git a/boards.cfg b/boards.cfg index caba64e..6e2fccc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -245,6 +245,7 @@ Active arm arm926ejs versatile armltd versatile Active arm arm946es - armltd integrator integratorap_cm946es integratorap:CM946ES Linus Walleij <linus.walleij(a)linaro.org> Active arm arm946es - armltd integrator integratorcp_cm946es integratorcp:CM946ES Linus Walleij <linus.walleij(a)linaro.org> Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - - +Active arm armv7 - armltd vexpress vexpress_ca15_tc2_qemu vexpress_ca15_tc2:ARCH_VEXPRESS_QEMU - Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel(a)linaro.org> Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel(a)linaro.org> Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo(a)iseebcn.com> diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index 982f4a7..ccdb3c5 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -18,6 +18,8 @@ #define CONFIG_SYSFLAGS_ADDR 0x1c010030 #define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR +#ifndef CONFIG_ARCH_VEXPRESS_QEMU #define CONFIG_ARMV7_VIRT +#endif #endif diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 7e78f8a..fbb9993 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -157,6 +157,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PXE #define CONFIG_MENU +#define CONFIG_CMD_ECHO #define CONFIG_CMD_ELF #define CONFIG_CMD_ENV #define CONFIG_CMD_FLASH @@ -164,6 +165,7 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET #define CONFIG_CMD_PING +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_RUN #define CONFIG_CMD_BOOTZ @@ -176,6 +178,7 @@ #define CONFIG_GENERIC_MMC #define CONFIG_ARM_PL180_MMCI #define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI +#define CONFIG_SYS_MMC_MAX_DEVICE 2 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 #define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 @@ -253,6 +256,7 @@ #define CONFIG_SYS_FLASH_BASE0 V2M_NOR0 #define CONFIG_SYS_FLASH_BASE1 V2M_NOR1 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 +#define CONFIG_API /* Timeout values in ticks */ #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ -- 1.8.4.rc3

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[U-Boot] [PATCH v3 1/4] mkexynosspl: fix uninitialized buffer
by Albert ARIBAUD 23 Dec '13

23 Dec '13

mkexynos reads its input file which might be smaller than its read buffer, but always writes the whole buffer out. This does not affect the functionalyty of the output file, but it makes its content unpredictable as the end of the buffer is never initialized. Fix this by zeroing the buffer before reading the input file. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- Changes in v3: - fixed mkexynosspl uninitialized buffer Changes in v2: None tools/mkexynosspl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/mkexynosspl.c b/tools/mkexynosspl.c index ef685b7..8d605fa 100644 --- a/tools/mkexynosspl.c +++ b/tools/mkexynosspl.c @@ -72,6 +72,8 @@ int main(int argc, char **argv) count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET; + memset(buffer, 0, BUFSIZE); + if (read(ifd, buffer, count) != count) { fprintf(stderr, "%s: Can't read %s: %s\n", argv[0], argv[1], strerror(errno)); -- 1.8.3.2

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[U-Boot] [PATCH 00/11 V12] EXYNOS5420: Add SMDK5420 board support
by Rajeshwari S Shinde 23 Dec '13

23 Dec '13

This patch adds basic board support for SMDK5420 board. These patches are tested for booting fine on EVT1 SMDK5420. Changes in V2: - Corrected a compilation issue for SMDK5420. Changes in V3: - Add patch to support variable size SPL support - Add patch to disable SMU for eMMC. Changes in V4: - Added check for MAX77686 pmic compilation. - Added correct calculation of gpio based addresses. - Rebased on the latest u-boot code. - Removed patches for UART and TZPC changes as they were not needed. - Added flag to disable SMU for eMMC. Changes in V5: - Moved functions board_mmc_init and board_eth_init to common/board.c in case of device tree support. Changes in V6: - Rebased on the latest mainline branch. - Moved the definitions for SMU to arch/arm dwmmc.h Changes in V7: - Removed below patch as it is already merged "DWMMC: SMDK5420: Disable SMU for eMMC" - Corrected the multi line comments and removal of blank spaces and lines. - Corrected the license. Changes in V8: - corrected the if loops with if conditions of pro_id and cpu_id. Changes in V9: - Added macros to get the base address - Rebased on latest code. Changes in V10: - Added new structures for Power and DMC registers for 5420. - Changed the input parameters for common dmc functions. - Removed unnecesarry blank lines and added where ever required. Changes in V11: -Rebased on latest u-boot-samsung branch. Changes in V12: - Changed const void * pointers to uint32_t *. Rajeshwari S Shinde (11): EXYNOS5: Create a common board file Exynos5420: Add base addresses for 5420 EXYNOS5420: Add power register structure. EXYNOS5420: Add dmc and phy_control register structure Exynos5420: Add clock initialization for 5420 Exynos5420: Add DDR3 initialization for 5420 Exynos5420: Add support for 5420 in pinmux and gpio Exynos5420: Add base patch for SMDK5420 DTS: Add dts support for SMDK5420 Config: Add initial config for SMDK5420 SPL: EXYNOS: Prepare for variable size SPL support arch/arm/cpu/armv7/exynos/clock.c | 279 ++++++++- arch/arm/cpu/armv7/exynos/clock_init.h | 17 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 ++++++++++- arch/arm/cpu/armv7/exynos/dmc_common.c | 60 +- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 439 ++++++++++++- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 764 ++++++++++++++++------ arch/arm/cpu/armv7/exynos/pinmux.c | 260 +++++++- arch/arm/dts/exynos5.dtsi | 198 ++++++ arch/arm/dts/exynos5250.dtsi | 194 +----- arch/arm/dts/exynos5420.dtsi | 70 +++ arch/arm/include/asm/arch-exynos/board.h | 17 + arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 494 +++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 52 +- arch/arm/include/asm/arch-exynos/dmc.h | 177 ++++++ arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++- arch/arm/include/asm/arch-exynos/periph.h | 3 + arch/arm/include/asm/arch-exynos/power.h | 837 +++++++++++++++++++++++++ board/samsung/common/Makefile | 4 + board/samsung/common/board.c | 410 ++++++++++++ board/samsung/dts/exynos5420-smdk5420.dts | 169 +++++ board/samsung/smdk5250/exynos5-dt.c | 352 +---------- board/samsung/smdk5250/smdk5250.c | 182 +----- board/samsung/smdk5420/Makefile | 11 + board/samsung/smdk5420/smdk5420.c | 159 +++++ board/samsung/smdk5420/smdk5420_spl.c | 52 ++ boards.cfg | 1 + include/configs/arndale.h | 1 + include/configs/exynos5-dt.h | 289 +++++++++ include/configs/exynos5250-dt.h | 283 +-------- include/configs/smdk5420.h | 56 ++ spl/Makefile | 7 +- tools/Makefile | 3 +- tools/mkexynosspl.c | 167 +++-- 34 files changed, 5188 insertions(+), 1315 deletions(-) create mode 100644 arch/arm/dts/exynos5.dtsi create mode 100644 arch/arm/dts/exynos5420.dtsi create mode 100644 arch/arm/include/asm/arch-exynos/board.h create mode 100644 board/samsung/common/board.c create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts create mode 100644 board/samsung/smdk5420/Makefile create mode 100644 board/samsung/smdk5420/smdk5420.c create mode 100644 board/samsung/smdk5420/smdk5420_spl.c create mode 100644 include/configs/exynos5-dt.h create mode 100644 include/configs/smdk5420.h -- 1.7.12.4

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[U-Boot] [PATCH v2 1/2] doc: README.fuse: Add an example on how to use the fuse API on mx6q
by Fabio Estevam 21 Dec '13

21 Dec '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> When using the fuse API in U-boot user must calculate the 'bank' and 'word' values. Provide a real example on how to calculate such values for the mx6q. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - Move the example into doc/README.imx6 doc/README.imx6 | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/doc/README.imx6 b/doc/README.imx6 index 513a06e..728b32c 100644 --- a/doc/README.imx6 +++ b/doc/README.imx6 @@ -8,3 +8,60 @@ SoC. 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the 16 msbs in word 3. + +Example: + +For reading the MAC address fuses on a MX6Q: + +- The MAC address are stored in two fuse addresses (the fuse addresses are +described in the Fusemap Descriptions table from the mx6q Reference Manual): + +0x620[31:0] - MAC_ADDR[31:0] +0x630[15:0] - MAC_ADDR[47:32] + +In order to use the fuse API, we need to pass the bank and word values, which +are calculated as below: + +Fuse address for the lower MAC address: 0x620 +Base address for the fuses: 0x400 + +(0x620 - 0x400)/0x10 = 0x22 = 34 decimal + +As the fuses are arranged in banks of 8 words: + +34 / 8 = 4 and the remainder is 2, so in this case: + +bank = 4 +word = 2 + +And the U-boot command would be: + +=> fuse read 4 2 +Reading bank 4: + +Word 0x00000002: 9f027772 + +Doing the same for the upper MAC address: + +Fuse address for the upper MAC address: 0x630 +Base address for the fuses: 0x400 + +(0x630 - 0x400)/0x10 = 0x23 = 35 decimal + +As the fuses are arranged in banks of 8 words: + +35 / 8 = 4 and the remainder is 3, so in this case: + +bank = 4 +word = 3 + +And the U-boot command would be: + +=> fuse read 4 3 +Reading bank 4: + +Word 0x00000003: 00000004 + +,which matches the ethaddr value: +=> echo ${ethaddr} +00:04:9f:02:77:72 -- 1.8.1.2

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[U-Boot] [U-Boot, PATCHv3, 2/5] am437x_epos_evm: add SPL API, QSPI, and serial flash support
by Jagannadha Sutradharudu Teki 21 Dec '13

21 Dec '13

From: "Poddar, Sourav" <sourav.poddar(a)ti.com> Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Sourav Poddar <sourav.poddar(a)ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- V3: Fixed warnings, Added review tag V2: none board/ti/am43xx/mux.c | 11 +++++++++++ include/configs/am43xx_evm.h | 20 ++++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 810b194..4db3d78 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -38,6 +38,16 @@ static struct module_pin_mux gpio0_22_pin_mux[] = { {-1}, }; +static struct module_pin_mux qspi_pin_mux[] = { + {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */ + {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */ + {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */ + {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */ + {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */ + {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -50,6 +60,7 @@ void enable_board_pin_mux(void) if (board_is_gpevm()) configure_module_pin_mux(gpio0_22_pin_mux); + configure_module_pin_mux(qspi_pin_mux); } void enable_i2c0_pin_mux(void) diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4de495a..a81c586 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -79,6 +79,26 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_AM437X_USB2PHY2_HOST +/* SPI */ +#undef CONFIG_OMAP3_SPI +#define CONFIG_TI_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_TI_SPI_MMAP +#define CONFIG_QSPI_SEL_GPIO 48 +#define CONFIG_SF_DEFAULT_SPEED 48000000 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 + +/* SPI SPL */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \

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[U-Boot] [U-Boot, PATCHv2, 2/5] am437x_epos_evm: add SPL API, QSPI, and serial flash support
by Jagannadha Sutradharudu Teki 21 Dec '13

21 Dec '13

From: "Poddar, Sourav" <sourav.poddar(a)ti.com> Enables support for SPI SPL, QSPI and Spansion serial flash device on the EVM. Configures pin muxes for QSPI mode. Signed-off-by: Sourav Poddar <sourav.poddar(a)ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- board/ti/am43xx/mux.c | 11 +++++++++++ include/configs/am43xx_evm.h | 20 ++++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index 810b194..4db3d78 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -38,6 +38,16 @@ static struct module_pin_mux gpio0_22_pin_mux[] = { {-1}, }; +static struct module_pin_mux qspi_pin_mux[] = { + {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */ + {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */ + {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */ + {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */ + {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */ + {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -50,6 +60,7 @@ void enable_board_pin_mux(void) if (board_is_gpevm()) configure_module_pin_mux(gpio0_22_pin_mux); + configure_module_pin_mux(qspi_pin_mux); } void enable_i2c0_pin_mux(void) diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4de495a..a81c586 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -79,6 +79,26 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_AM437X_USB2PHY2_HOST +/* SPI */ +#undef CONFIG_OMAP3_SPI +#define CONFIG_TI_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_TI_SPI_MMAP +#define CONFIG_QSPI_SEL_GPIO 48 +#define CONFIG_SF_DEFAULT_SPEED 48000000 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 + +/* SPI SPL */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \

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[U-Boot] [U-Boot,PATCHv3,1/5] am43xx: Add qspi support
by Jagannadha Sutradharudu Teki 21 Dec '13

21 Dec '13

From: "Poddar, Sourav" <sourav.poddar(a)ti.com> Add QSPI definitions and clock configuration support. Signed-off-by: Sourav Poddar <sourav.poddar(a)ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 1 + arch/arm/include/asm/arch-am33xx/cpu.h | 4 +++- arch/arm/include/asm/arch-am33xx/omap.h | 1 + 3 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 97c00b4..fb654bb 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -98,6 +98,7 @@ void enable_basic_clocks(void) &cmper->emiffwclkctrl, &cmper->emifclkctrl, &cmper->otfaemifclkctrl, + &cmper->qspiclkctrl, 0 }; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 9febfa2..0736258 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -332,7 +332,9 @@ struct cm_perpll { unsigned int mcasp1clkctrl; /* offset 0x240 */ unsigned int resv11; unsigned int mmc2clkctrl; /* offset 0x248 */ - unsigned int resv12[5]; + unsigned int resv12[3]; + unsigned int qspiclkctrl; /* offset 0x258 */ + unsigned int resv121; unsigned int usb0clkctrl; /* offset 0x260 */ unsigned int resv13[103]; unsigned int l4lsclkstctrl; /* offset 0x400 */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 7a7d91b..0855d16 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -29,5 +29,6 @@ #define SRAM_SCRATCH_SPACE_ADDR 0x40337C00 #define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR #define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC +#define QSPI_BASE 0x47900000 #endif #endif

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[U-Boot] [PATCH v8] spi: Add Faraday SPI controller support
by Jagannadha Sutradharudu Teki 21 Dec '13

21 Dec '13

From: Kuo-Jung Su <dantesu(a)faraday-tech.com> The Faraday FTSSP010 is a multi-function controller which supports I2S/SPI/SSP/AC97/SPDIF. However This patch implements only the SPI mode. NOTE: The DMA and CS/Clock control logic has been altered since hardware revision 1.19.0. So this patch would first detects the revision id of the underlying chip, and then switch to the corresponding software control routines. Signed-off-by: Kuo-Jung Su <dantesu(a)faraday-tech.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> CC: Tom Rini <trini(a)ti.com> --- Changes for V8: - Added spi flash test log Changes for v7: - Fixed some checkpatch warnings - Removed unneeded "inline" in few lenghty defination funcs. Changes for v6: - Drop SPI_LSB_FIRST support, because this driver supports only 8-bit mode access. - Bug fix: Move chip enable from ftssp010_cs_set() to spi_cs_activate(), because ftssp010_cs_set() is supposed to update only the cs signal. Changes for v5: - Use SPDX-License-Identifier - Add SPI mode checking & setup - Coding Style cleanup Changes for v4: - Coding Style cleanup. - Make it a separate patch, rather then a part of Faraday A36x patch series - Use macro constants for timeout control Changes for v3: - Coding Style cleanup. - Drop macros for wirtel()/readl(), call them directly. - Always insert a blank line between declarations and code. - Replace all the infinite wait loop with a timeout. - Add '__iomem' to all the declaration of HW register pointers. Changes for v2: - Coding Style cleanup. - Use readl(), writel(), clrsetbits_le32() to replace REG() macros. - Use structure based hardware registers to replace the macro constants. - Replace BIT() with BIT_MASK(). doc/SPI/README.ftssp010_spi_test | 41 ++++ drivers/spi/Makefile | 1 + drivers/spi/ftssp010_spi.c | 508 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 550 insertions(+) create mode 100644 doc/SPI/README.ftssp010_spi_test create mode 100644 drivers/spi/ftssp010_spi.c diff --git a/doc/SPI/README.ftssp010_spi_test b/doc/SPI/README.ftssp010_spi_test new file mode 100644 index 0000000..1d86f36 --- /dev/null +++ b/doc/SPI/README.ftssp010_spi_test @@ -0,0 +1,41 @@ +SPI Flash test on Faraday A369 EVB: +================================== + +U-Boot 2014.01-rc2-g3444b6f (Dec 20 2013 - 10:58:40) + +CPU: FA626TE 528 MHz +AHB: 132 MHz +APB: 66 MHz +I2C: ready +DRAM: 256 MiB +MMU: on +NAND: 512 MiB +MMC: ftsdc010: 0 +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: FTGMAC100#0 +Hit any key to stop autoboot: 0 +=> sf probe 0:0 +SF: Detected MX25L1605D with page size 256 Bytes, erase size 64 KiB, total 2 MiB +=> sf read 0x10800000 0 0x400 +SF: 1024 bytes @ 0x0 Read: OK +=> md 0x10800000 +10800000: ea000013 e59ff014 e59ff014 e59ff014 ................ +10800010: e59ff014 e59ff014 e59ff014 e59ff014 ................ +10800020: 1ff7b0c0 1ff7b120 1ff7b180 1ff7b1e0 .... ........... +10800030: 1ff7b240 1ff7b2a0 1ff7b300 deadbeef @............... +10800040: 10800000 0002c1f0 0007409c 00032048 .........@..H .. +10800050: 1fd6af40 e10f0000 e3c0001f e38000d3 @............... +10800060: e129f000 eb000001 eb000223 e12fff1e ..).....#...../. +10800070: e3a00000 ee070f1e ee080f17 ee070f15 ................ +10800080: ee070f9a ee110f10 e3c00c03 e3c00087 ................ +10800090: e3c00a02 e3800002 e3800a01 ee010f10 ................ +108000a0: e1a0c00e eb007a68 e1a0e00c e1a0f00e ....hz.......... +108000b0: e1a00000 e1a00000 e1a00000 e1a00000 ................ +108000c0: e51fd078 e58de000 e14fe000 e58de004 x.........O..... +108000d0: e3a0d013 e169f00d e1a0e00f e1b0f00e ......i......... +108000e0: e24dd048 e88d1fff e51f20a0 e892000c H.M...... ...... +108000f0: e28d0048 e28d5034 e1a0100e e885000f H...4P.......... diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d5a7143..81b6af6 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_CF_QSPI) += cf_qspi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o +obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c new file mode 100644 index 0000000..aa3b5a0 --- /dev/null +++ b/drivers/spi/ftssp010_spi.c @@ -0,0 +1,508 @@ +/* + * (C) Copyright 2013 + * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/> + * Kuo-Jung Su <dantesu(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/compat.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> + +#ifndef CONFIG_FTSSP010_BASE_LIST +#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE } +#endif + +#ifndef CONFIG_FTSSP010_GPIO_BASE +#define CONFIG_FTSSP010_GPIO_BASE 0 +#endif + +#ifndef CONFIG_FTSSP010_GPIO_LIST +#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE } +#endif + +#ifndef CONFIG_FTSSP010_CLOCK +#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP"); +#endif + +#ifndef CONFIG_FTSSP010_TIMEOUT +#define CONFIG_FTSSP010_TIMEOUT 100 +#endif + +/* FTSSP010 chip registers */ +struct ftssp010_regs { + uint32_t cr[3];/* control register */ + uint32_t sr; /* status register */ + uint32_t icr; /* interrupt control register */ + uint32_t isr; /* interrupt status register */ + uint32_t dr; /* data register */ + uint32_t rsvd[17]; + uint32_t revr; /* revision register */ + uint32_t fear; /* feature register */ +}; + +/* Control Register 0 */ +#define CR0_FFMT_MASK (7 << 12) +#define CR0_FFMT_SSP (0 << 12) +#define CR0_FFMT_SPI (1 << 12) +#define CR0_FFMT_MICROWIRE (2 << 12) +#define CR0_FFMT_I2S (3 << 12) +#define CR0_FFMT_AC97 (4 << 12) +#define CR0_FLASH (1 << 11) +#define CR0_FSDIST(x) (((x) & 0x03) << 8) +#define CR0_LOOP (1 << 7) /* loopback mode */ +#define CR0_LSB (1 << 6) /* LSB */ +#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */ +#define CR0_FSJUSTIFY (1 << 4) +#define CR0_OPM_SLAVE (0 << 2) +#define CR0_OPM_MASTER (3 << 2) +#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */ +#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */ +#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */ +#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */ +#define CR0_SCLKPO (1 << 1) /* clock polarity */ +#define CR0_SCLKPH (1 << 0) /* clock phase */ + +/* Control Register 1 */ +#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */ +#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */ +#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */ + +/* Control Register 2 */ +#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */ +#define CR2_FS (1 << 9) /* CS/FS signal level */ +#define CR2_TXEN (1 << 8) /* tx enable */ +#define CR2_RXEN (1 << 7) /* rx enable */ +#define CR2_RESET (1 << 6) /* chip reset */ +#define CR2_TXFC (1 << 3) /* tx fifo Clear */ +#define CR2_RXFC (1 << 2) /* rx fifo Clear */ +#define CR2_TXDOE (1 << 1) /* tx data output enable */ +#define CR2_EN (1 << 0) /* chip enable */ + +/* Status Register */ +#define SR_RFF (1 << 0) /* rx fifo full */ +#define SR_TFNF (1 << 1) /* tx fifo not full */ +#define SR_BUSY (1 << 2) /* chip busy */ +#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */ +#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */ + +/* Feature Register */ +#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */ +#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */ +#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */ +#define FEAR_AC97 (1 << 24) +#define FEAR_I2S (1 << 25) +#define FEAR_SPI_MWR (1 << 26) +#define FEAR_SSP (1 << 27) +#define FEAR_SPDIF (1 << 28) + +/* FTGPIO010 chip registers */ +struct ftgpio010_regs { + uint32_t out; /* 0x00: Data Output */ + uint32_t in; /* 0x04: Data Input */ + uint32_t dir; /* 0x08: Direction */ + uint32_t bypass; /* 0x0c: Bypass */ + uint32_t set; /* 0x10: Data Set */ + uint32_t clr; /* 0x14: Data Clear */ + uint32_t pull_up; /* 0x18: Pull-Up Enabled */ + uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */ +}; + +struct ftssp010_gpio { + struct ftgpio010_regs *regs; + uint32_t pin; +}; + +struct ftssp010_spi { + struct spi_slave slave; + struct ftssp010_gpio gpio; + struct ftssp010_regs *regs; + uint32_t fifo; + uint32_t mode; + uint32_t div; + uint32_t clk; + uint32_t speed; + uint32_t revision; +}; + +static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ftssp010_spi, slave); +} + +static int get_spi_chip(int bus, struct ftssp010_spi *chip) +{ + uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST; + + if (bus >= ARRAY_SIZE(base) || !base[bus]) + return -1; + + chip->regs = (struct ftssp010_regs *)base[bus]; + + chip->revision = readl(&chip->regs->revr); + + fear = readl(&chip->regs->fear); + chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear)); + + return 0; +} + +static int get_spi_gpio(int bus, struct ftssp010_gpio *chip) +{ + uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST; + + if (bus >= ARRAY_SIZE(base) || !base[bus]) + return -1; + + chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000); + chip->pin = base[bus] & 0x1f; + + /* make it an output pin */ + setbits_le32(&chip->regs->dir, 1 << chip->pin); + + return 0; +} + +static int ftssp010_wait(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + int ret = -1; + ulong t; + + /* wait until device idle */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (readl(&regs->sr) & SR_BUSY) + continue; + ret = 0; + break; + } + + if (ret) + puts("ftspi010: busy timeout\n"); + + return ret; +} + +static int ftssp010_wait_tx(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + int ret = -1; + ulong t; + + /* wait until tx fifo not full */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (!(readl(&regs->sr) & SR_TFNF)) + continue; + ret = 0; + break; + } + + if (ret) + puts("ftssp010: tx timeout\n"); + + return ret; +} + +static int ftssp010_wait_rx(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + int ret = -1; + ulong t; + + /* wait until rx fifo not empty */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (!SR_RFVE(readl(&regs->sr))) + continue; + ret = 0; + break; + } + + if (ret) + puts("ftssp010: rx timeout\n"); + + return ret; +} + +static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip, + const void *tx_buf, void *rx_buf, int len, uint flags) +{ + struct ftssp010_regs *regs = chip->regs; + const uint8_t *txb = tx_buf; + uint8_t *rxb = rx_buf; + + while (len > 0) { + int i, depth = min(chip->fifo >> 2, len); + uint32_t xmsk = 0; + + if (tx_buf) { + for (i = 0; i < depth; ++i) { + ftssp010_wait_tx(chip); + writel(*txb++, &regs->dr); + } + xmsk |= CR2_TXEN | CR2_TXDOE; + if ((readl(&regs->cr[2]) & xmsk) != xmsk) + setbits_le32(&regs->cr[2], xmsk); + } + if (rx_buf) { + xmsk |= CR2_RXEN; + if ((readl(&regs->cr[2]) & xmsk) != xmsk) + setbits_le32(&regs->cr[2], xmsk); + for (i = 0; i < depth; ++i) { + ftssp010_wait_rx(chip); + *rxb++ = (uint8_t)readl(&regs->dr); + } + } + + len -= depth; + } + + return 0; +} + +static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip, + const void *tx_buf, void *rx_buf, int len, uint flags) +{ + struct ftssp010_regs *regs = chip->regs; + const uint8_t *txb = tx_buf; + uint8_t *rxb = rx_buf; + + while (len > 0) { + int i, depth = min(chip->fifo >> 2, len); + uint32_t tmp; + + for (i = 0; i < depth; ++i) { + ftssp010_wait_tx(chip); + writel(txb ? (*txb++) : 0, &regs->dr); + } + for (i = 0; i < depth; ++i) { + ftssp010_wait_rx(chip); + tmp = readl(&regs->dr); + if (rxb) + *rxb++ = (uint8_t)tmp; + } + + len -= depth; + } + + return 0; +} + +static void ftssp010_cs_set(struct ftssp010_spi *chip, int high) +{ + struct ftssp010_regs *regs = chip->regs; + struct ftssp010_gpio *gpio = &chip->gpio; + uint32_t mask; + + /* cs pull high/low */ + if (chip->revision >= 0x11900) { + mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0); + writel(mask, &regs->cr[2]); + } else if (gpio->regs) { + mask = 1 << gpio->pin; + if (high) + writel(mask, &gpio->regs->set); + else + writel(mask, &gpio->regs->clr); + } + + /* extra delay for signal propagation */ + udelay_masked(1); +} + +/* + * Determine if a SPI chipselect is valid. + * This function is provided by the board if the low-level SPI driver + * needs it to determine if a given chipselect is actually valid. + * + * Returns: 1 if bus:cs identifies a valid chip on this board, 0 + * otherwise. + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + struct ftssp010_spi chip; + + if (get_spi_chip(bus, &chip)) + return 0; + + if (!cs) + return 1; + else if ((cs < 4) && (chip.revision >= 0x11900)) + return 1; + + return 0; +} + +/* + * Activate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should activate the chip select + * to the device identified by "slave". + */ +void spi_cs_activate(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + /* cs pull */ + if (chip->mode & SPI_CS_HIGH) + ftssp010_cs_set(chip, 1); + else + ftssp010_cs_set(chip, 0); + + /* chip enable + fifo clear */ + setbits_le32(&regs->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC); +} + +/* + * Deactivate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should deactivate the chip + * select to the device identified by "slave". + */ +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + + /* wait until chip idle */ + ftssp010_wait(chip); + + /* cs pull */ + if (chip->mode & SPI_CS_HIGH) + ftssp010_cs_set(chip, 0); + else + ftssp010_cs_set(chip, 1); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +{ + struct ftssp010_spi *chip; + + if (mode & SPI_3WIRE) { + puts("ftssp010: can't do 3-wire\n"); + return NULL; + } + + if (mode & SPI_SLAVE) { + puts("ftssp010: can't do slave mode\n"); + return NULL; + } + + if (mode & SPI_PREAMBLE) { + puts("ftssp010: can't skip preamble bytes\n"); + return NULL; + } + + if (!spi_cs_is_valid(bus, cs)) { + puts("ftssp010: invalid (bus, cs)\n"); + return NULL; + } + + chip = spi_alloc_slave(struct ftssp010_spi, bus, cs); + if (!chip) + return NULL; + + if (get_spi_chip(bus, chip)) + goto free_out; + + if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) { + puts("ftssp010: Before revision 1.19.0, its clock & cs are\n" + "controlled by tx engine which is not synced with rx engine,\n" + "so the clock & cs might be shutdown before rx engine\n" + "finishs its jobs.\n" + "If possible, please add a dedicated gpio for it.\n"); + } + + chip->mode = mode; + chip->clk = CONFIG_FTSSP010_CLOCK; + chip->div = 2; + if (max_hz) { + while (chip->div < 0xffff) { + if ((chip->clk / (2 * chip->div)) <= max_hz) + break; + chip->div += 1; + } + } + chip->speed = chip->clk / (2 * chip->div); + + return &chip->slave; + +free_out: + free(chip); + return NULL; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + writel(CR1_SDL(8) | CR1_DIV(chip->div), &regs->cr[1]); + + if (chip->revision >= 0x11900) { + writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH, + &regs->cr[0]); + writel(CR2_TXFC | CR2_RXFC, + &regs->cr[2]); + } else { + writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO, + &regs->cr[0]); + writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE, + &regs->cr[2]); + } + + if (chip->mode & SPI_LOOP) + setbits_le32(&regs->cr[0], CR0_LOOP); + + if (chip->mode & SPI_CPOL) + setbits_le32(&regs->cr[0], CR0_SCLKPO); + + if (chip->mode & SPI_CPHA) + setbits_le32(&regs->cr[0], CR0_SCLKPH); + + spi_cs_deactivate(slave); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + writel(0, &regs->cr[2]); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + uint32_t len = bitlen >> 3; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + if (chip->revision >= 0x11900) + ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags); + else + ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags); + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} -- 1.8.3

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