December 2013 - U-Boot

[U-Boot] [PATCH] Add code for spi half duplex operation for enc28j60
by Asok Subramanian 08 Jan '14

08 Jan '14

Add code for spi half duplex operation for enc28j60 The current code assumes full duplex spi operation. But there are processors like imx23 which only permit half duplex operation. This fix does half duplex operation based on the definition of CONFIG_SPI_HALF_DUPLEX Signed-off-by: Asok Subramanian <asok at vyassoft.com> --- drivers/net/enc28j60.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index ec33764..753fe26 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -157,9 +157,17 @@ static u8 enc_r8(enc_dev_t *enc, const u16 reg) enc_set_bank(enc, reg); dout[0] = CMD_RCR(reg); +#ifndef CONFIG_SPI_HALF_DUPLEX spi_xfer(enc->slave, nbytes * 8, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); return din[nbytes-1]; +#else + spi_xfer(enc->slave, (nbytes -1) * 8, dout, NULL, + SPI_XFER_BEGIN ); + spi_xfer(enc->slave, 8, NULL, din, + SPI_XFER_END ); + return din[0]; +#endif } /* @@ -175,6 +183,7 @@ static u16 enc_r16(enc_dev_t *enc, const u16 reg) enc_set_bank(enc, reg); dout[0] = CMD_RCR(reg); +#ifndef CONFIG_SPI_HALF_DUPLEX spi_xfer(enc->slave, nbytes * 8, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); result = din[nbytes-1]; @@ -183,6 +192,20 @@ static u16 enc_r16(enc_dev_t *enc, const u16 reg) SPI_XFER_BEGIN | SPI_XFER_END); result |= din[nbytes-1] << 8; return result; +#else + spi_xfer(enc->slave, (nbytes -1) * 8, dout, NULL, + SPI_XFER_BEGIN ); + spi_xfer(enc->slave, 8, NULL, din, + SPI_XFER_END ); + result = din[0]; + dout[0]++; /* next register */ + spi_xfer(enc->slave, (nbytes -1) * 8, dout, NULL, + SPI_XFER_BEGIN ); + spi_xfer(enc->slave, 8, NULL, din, + SPI_XFER_END ); + result |= din[0] << 8; + return result; +#endif } /* -- 1.7.9.5

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[U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
by Armando Visconti 08 Jan '14

08 Jan '14

This patch adds the support for the ARM PL022 SPI controller for the standard variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO. Signed-off-by: Armando Visconti <armando.visconti(a)st.com> Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> Acked-by: Stefan Roese <sr(a)denx.de> --- v5->v6 1. Make use of spi_alloc_slave() macro. 2. Changed the identation on 'if statement' as requested by Jagan. drivers/spi/Makefile | 1 + drivers/spi/pl022_spi.c | 308 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 309 insertions(+) create mode 100644 drivers/spi/pl022_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d08609e..b6443b1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o +COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c new file mode 100644 index 0000000..5b47413 --- /dev/null +++ b/drivers/spi/pl022_spi.c @@ -0,0 +1,308 @@ +/* + * (C) Copyright 2012 + * Armando Visconti, ST Microelectronics, armando.visconti(a)st.com. + * + * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c + * by Atmel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* SSP registers mapping */ +struct pl022 { + u32 ssp_cr0; /* 0x000 */ + u32 ssp_cr1; /* 0x004 */ + u32 ssp_dr; /* 0x008 */ + u32 ssp_sr; /* 0x00c */ + u32 ssp_cpsr; /* 0x010 */ + u32 ssp_imsc; /* 0x014 */ + u32 ssp_ris; /* 0x018 */ + u32 ssp_mis; /* 0x01c */ + u32 ssp_icr; /* 0x020 */ + u32 ssp_dmacr; /* 0x024 */ + u8 reserved_1[0x080 - 0x028]; + u32 ssp_itcr; /* 0x080 */ + u32 ssp_itip; /* 0x084 */ + u32 ssp_itop; /* 0x088 */ + u32 ssp_tdr; /* 0x08c */ + u8 reserved_2[0xFE0 - 0x090]; + u32 ssp_pid0; /* 0xfe0 */ + u32 ssp_pid1; /* 0xfe4 */ + u32 ssp_pid2; /* 0xfe8 */ + u32 ssp_pid3; /* 0xfec */ + u32 ssp_cid0; /* 0xff0 */ + u32 ssp_cid1; /* 0xff4 */ + u32 ssp_cid2; /* 0xff8 */ + u32 ssp_cid3; /* 0xffc */ +}; + +/* SSP Control Register 0 - SSP_CR0 */ +#define SSP_CR0_SPO (0x1 << 6) +#define SSP_CR0_SPH (0x1 << 7) +#define SSP_CR0_8BIT_MODE (0x07) +#define SSP_SCR_MAX (0xFF) +#define SSP_SCR_SHFT 8 + +/* SSP Control Register 0 - SSP_CR1 */ +#define SSP_CR1_MASK_SSE (0x1 << 1) + +#define SSP_CPSR_MAX (0xFE) + +/* SSP Status Register - SSP_SR */ +#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */ +#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */ +#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */ +#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */ +#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ + +struct pl022_spi_slave { + struct spi_slave slave; + void *regs; + unsigned int freq; +}; + +static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave) +{ + return container_of(slave, struct pl022_spi_slave, slave); +} + +/* + * Following three functions should be provided by the + * board support package. + */ +int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void __weak spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void __weak spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_init(void) +{ + /* do nothing */ +} + +/* + * ARM PL022 exists in different 'flavors'. + * This drivers currently support the standard variant (0x00041022), that has a + * 16bit wide and 8 locations deep TX/RX FIFO. + */ +static int pl022_is_supported(struct pl022_spi_slave *ps) +{ + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* PL022 version is 0x00041022 */ + if ((readl(&pl022->ssp_pid0) == 0x22) && + (readl(&pl022->ssp_pid1) == 0x10) && + ((readl(&pl022->ssp_pid2) & 0xf) == 0x04) && + (readl(&pl022->ssp_pid3) == 0x00)) + return 1; + + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct pl022_spi_slave *ps; + struct pl022 *pl022; + u16 scr = 1, prescaler, cr0 = 0, cpsr = 0; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ps = spi_alloc_slave(struct pl022_spi_slave, bus, cs); + if (!ps) + return NULL; + + ps->freq = max_hz; + + switch (bus) { + case 0: + ps->regs = (void *)CONFIG_SYS_SPI_BASE; + break; +#ifdef CONFIG_SYS_SPI_BASE1 + case 1: + ps->regs = (void *)CONFIG_SYS_SPI_BASE1; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE2 + case 2: + ps->regs = (void *)CONFIG_SYS_SPI_BASE2; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE3 + case 3: + ps->regs = (void *)CONFIG_SYS_SPI_BASE3; + break; +#endif + default: + free(ps); + return NULL; + } + + pl022 = (struct pl022 *)ps->regs; + + /* Check the PL022 version */ + if (!pl022_is_supported(ps)) { + free(ps); + return NULL; + } + + /* Set requested polarity and 8bit mode */ + cr0 = SSP_CR0_8BIT_MODE; + cr0 |= (mode & SPI_CPHA) ? SSP_CR0_SPH : 0; + cr0 |= (mode & SPI_CPOL) ? SSP_CR0_SPO : 0; + + writel(cr0, &pl022->ssp_cr0); + + /* Program the SSPClk frequency */ + prescaler = CONFIG_SYS_SPI_CLK / ps->freq; + + if (prescaler <= 0xFF) { + cpsr = prescaler; + } else { + for (scr = 1; scr <= SSP_SCR_MAX; scr++) { + if (!(prescaler % scr)) { + cpsr = prescaler / scr; + if (cpsr <= SSP_CPSR_MAX) + break; + } + } + + if (scr > SSP_SCR_MAX) { + scr = SSP_SCR_MAX; + cpsr = prescaler / scr; + cpsr &= SSP_CPSR_MAX; + } + } + + if (cpsr & 0x1) + cpsr++; + + writel(cpsr, &pl022->ssp_cpsr); + cr0 = readl(&pl022->ssp_cr0); + writel(cr0 | (scr - 1) << SSP_SCR_SHFT, &pl022->ssp_cr0); + + return &ps->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + + free(ps); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Enable the SPI hardware */ + setbits_le32(&pl022->ssp_cr1, SSP_CR1_MASK_SSE); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Disable the SPI hardware */ + writel(0x0, &pl022->ssp_cr1); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + u32 len_tx = 0, len_rx = 0, len; + u32 ret = 0; + const u8 *txp = dout; + u8 *rxp = din, value; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * TODO: The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + ret = -1; + + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (len_tx < len) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_TNF) { + value = (txp != NULL) ? *txp++ : 0; + writel(value, &pl022->ssp_dr); + len_tx++; + } + + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + + while (len_rx < len_tx) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} -- 1.7.11.7

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[U-Boot] [PATCH 0/8] Secure boot improvements and test on Beaglebone Black
by Simon Glass 08 Jan '14

08 Jan '14

This series adds a few improvements to the image signing feature to make it easier to use on the Beaglebone Black. - Add a DEV_TREE_BIN option to make it easier to include the correct FDT (with embedded public keys) into the U-Boot image - Enable cache for more TI boards (to speed things up) - Increase malloc size - Enable CONFIG_OF_CONTROL, FIT and secure boot on am33xx/omap (RFC only, not sure we want this, although we could create a separate config for it) I also have a change to adjust mkimage to automatically make space in the FDT when adding hashes and signatures. Included here is the ENOSPC patch, but the fit_image.c patch will wait until the dumpimage tool is merged, since I am changing the same code. With this, secure boot was tested successfully on Beaglebone Black. Simon Glass (8): am33xx/omap: Allow cache enable for all Sitara/OMAP hash: Export functions to find and show hash fdt: Add DEV_TREE_BIN option to specify a device tree binary file fdt: Update functions which write to an FDT to return -ENOSPC arm: ti: Increase malloc size to 16MB for armv7 boards RFC: am33xx/omap: Enable CONFIG_OF_CONTROL RFC: am33xx/omap: Enable FIT support RFC: am33xx/omap: Enable secure boot with CONFIG_FIT_SIGNATURE Makefile | 8 +- arch/arm/cpu/armv7/omap-common/Makefile | 4 + arch/arm/cpu/armv7/omap-common/hwinit-common.c | 41 -- arch/arm/cpu/armv7/omap-common/omap-cache.c | 56 +++ arch/arm/cpu/armv7/omap3/board.c | 8 - arch/arm/dts/am33xx.dtsi | 649 +++++++++++++++++++++++++ arch/arm/dts/dt-bindings/gpio/gpio.h | 15 + arch/arm/dts/dt-bindings/pinctrl/am33xx.h | 41 ++ arch/arm/dts/dt-bindings/pinctrl/omap.h | 54 ++ board/siemens/common/board.c | 9 - board/ti/dts/am335x-bone-common.dtsi | 262 ++++++++++ board/ti/dts/am335x-boneblack.dts | 17 + board/ti/dts/tps65217.dtsi | 56 +++ common/hash.c | 13 +- common/image-fit.c | 4 +- doc/README.fdt-control | 16 +- include/configs/am335x_evm.h | 9 + include/configs/ti_armv7_common.h | 2 +- include/hash.h | 22 + include/rsa.h | 3 +- lib/rsa/rsa-sign.c | 28 +- 21 files changed, 1236 insertions(+), 81 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/omap-cache.c create mode 100644 arch/arm/dts/am33xx.dtsi create mode 100644 arch/arm/dts/dt-bindings/gpio/gpio.h create mode 100644 arch/arm/dts/dt-bindings/pinctrl/am33xx.h create mode 100644 arch/arm/dts/dt-bindings/pinctrl/omap.h create mode 100644 board/ti/dts/am335x-bone-common.dtsi create mode 100644 board/ti/dts/am335x-boneblack.dts create mode 100644 board/ti/dts/tps65217.dtsi -- 1.8.4

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[U-Boot] [PATCH v3 00/29] zynq: More boards support
by Jagannadha Sutradharudu Teki 08 Jan '14

08 Jan '14

These changes are from u-boot-xlnx.git repo from git.xilinx.com This repo is well tested on xilinx zynq platform, hence pushing the same on upstream. Excluded qspi and nand changes from previous series. -- Thanks, Jagan. Jagannadha Sutradharudu Teki (29): zynq: Enable CONFIG_FIT_VERBOSE zynq: Enable Boot FreeBSD/vxWorks zynq: Cleanup on miscellaneous configs zynq: Cleanup on memory configs zynq: Minor config cleanup zynq: Enable cache options zynq: Add UART0, UART1 configs support zynq: Add GEM0, GEM1 configs support zynq-common: Rename zynq with zynq-common doc: zynq: Add information on zynq u-boot zynq: Add zynq zc70x board support zynq: Add zynq zed board support zynq: Move CONFIG_SYS_SDRAM_SIZE to pre-board configs zynq-common: Define exact TEXT_BASE zynq: zc70x: Add Catalyst 24WC08 EEPROM config support zynq: Add zynq microzed board support zynq: Add zynq_zc770 xm010 board support zynq: Add zynq_zc770 xm013 board support zynq: Add zynq_zc770 xm012 board support zynq: Add support to find bootmode zynq-common: Define default environment zynq-common: Change Env. Sector size to 128Kb zynq-common: Define flash env. partition zynq-common: Define CONFIG_ENV_OVERWRITE dts: zynq: Add basic fdt support gpio: zynq: Add dummy gpio routines zynq-common: Enable verified boot(RSA) dts: zynq: Add more zynq dts files doc: Update the zynq u-boot status arch/arm/cpu/armv7/zynq/slcr.c | 6 + arch/arm/dts/zynq-7000.dtsi | 13 ++ arch/arm/include/asm/arch-zynq/gpio.h | 25 +++ arch/arm/include/asm/arch-zynq/sys_proto.h | 1 + board/xilinx/dts/zynq-microzed.dts | 14 ++ board/xilinx/dts/zynq-zc702.dts | 14 ++ board/xilinx/dts/zynq-zc706.dts | 14 ++ board/xilinx/dts/zynq-zc770-xm010.dts | 14 ++ board/xilinx/dts/zynq-zc770-xm012.dts | 14 ++ board/xilinx/dts/zynq-zc770-xm013.dts | 14 ++ board/xilinx/dts/zynq-zed.dts | 14 ++ board/xilinx/zynq/board.c | 25 +++ boards.cfg | 8 +- doc/README.zynq | 91 +++++++++++ include/configs/zynq-common.h | 241 +++++++++++++++++++++++++++++ include/configs/zynq.h | 139 ----------------- include/configs/zynq_microzed.h | 25 +++ include/configs/zynq_zc70x.h | 28 ++++ include/configs/zynq_zc770.h | 39 +++++ include/configs/zynq_zed.h | 26 ++++ 20 files changed, 624 insertions(+), 141 deletions(-) create mode 100644 arch/arm/dts/zynq-7000.dtsi create mode 100644 arch/arm/include/asm/arch-zynq/gpio.h create mode 100644 board/xilinx/dts/zynq-microzed.dts create mode 100644 board/xilinx/dts/zynq-zc702.dts create mode 100644 board/xilinx/dts/zynq-zc706.dts create mode 100644 board/xilinx/dts/zynq-zc770-xm010.dts create mode 100644 board/xilinx/dts/zynq-zc770-xm012.dts create mode 100644 board/xilinx/dts/zynq-zc770-xm013.dts create mode 100644 board/xilinx/dts/zynq-zed.dts create mode 100644 doc/README.zynq create mode 100644 include/configs/zynq-common.h delete mode 100644 include/configs/zynq.h create mode 100644 include/configs/zynq_microzed.h create mode 100644 include/configs/zynq_zc70x.h create mode 100644 include/configs/zynq_zc770.h create mode 100644 include/configs/zynq_zed.h -- 1.8.3

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[U-Boot] [PULL] u-boot-onenand/master
by Lukasz Majewski 07 Jan '14

07 Jan '14

Hi Tom, Please find a tiny fix for onenand tree. I hope, that this fix will find its way to v2014.01. The following changes since commit fef24f4f38eb685a6da29097930e6e49b378f8fb: ARM: Samsung: Change GONI and Universal_C210 maintainers. (2013-12-20 10:48:06 -0500) are available in the git repository at: git://git.denx.de/u-boot-onenand.git master for you to fetch changes up to 9b56942f7d2f67e620662cfeb4269a9a938d55da: mtd: onenand: Fix unaligned access (2013-12-31 09:59:16 +0100) ---------------------------------------------------------------- Marek Vasut (1): mtd: onenand: Fix unaligned access drivers/mtd/onenand/onenand_base.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group

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[U-Boot] [PATCH v2] exynos5250: remove redundant SPI and PMIC related configs
by Inderpal Singh 07 Jan '14

07 Jan '14

They have been defined once already. Hence remove the redundant definitions. Signed-off-by: Inderpal Singh <inderpal.singh(a)linaro.org> --- v1 was posted as the first patch of [1] Changes in v2: - split from the patchset at [1] - removed redundant configs for PMIC - rebased to latest u-boot-samsung master branch [1] http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/157101 include/configs/exynos5250-dt.h | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 62b83d4..03b07b2 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -246,11 +246,6 @@ #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_I2C_EDID -/* PMIC */ -#define CONFIG_PMIC -#define CONFIG_PMIC_I2C -#define CONFIG_PMIC_MAX77686 - /* SPI */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SPI_FLASH @@ -278,27 +273,6 @@ #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX77686 -/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH - -#ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 50000000 -#define EXYNOS5_SPI_NUM_CONTROLLERS 5 -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X -- 1.7.9.5

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[U-Boot] [PATCH] spi: sh_spi: Use sh_spi_clear_bit() instead of open-coded
by Axel Lin 06 Jan '14

06 Jan '14

We have a sh_spi_clear_bit() function, there's no reason not to use it. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/spi/sh_spi.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c index 744afe3..7ca5e36 100644 --- a/drivers/spi/sh_spi.c +++ b/drivers/spi/sh_spi.c @@ -151,7 +151,6 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, { int i, cur_len, ret = 0; int remain = (int)len; - unsigned long tmp; if (len >= SH_SPI_FIFO_SIZE) sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); @@ -183,9 +182,7 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, } if (flags & SPI_XFER_END) { - tmp = sh_spi_read(&ss->regs->cr1); - tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); - sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); udelay(100); write_fifo_empty_wait(ss); @@ -198,16 +195,13 @@ static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data, unsigned int len, unsigned long flags) { int i; - unsigned long tmp; if (len > SH_SPI_MAX_BYTE) sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3); else sh_spi_write(len, &ss->regs->cr3); - tmp = sh_spi_read(&ss->regs->cr1); - tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); - sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); for (i = 0; i < len; i++) { -- 1.8.1.2

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[U-Boot] linkstation_HGLAN and MPC824x support
by Tom Rini 06 Jan '14

06 Jan '14

Hello, With a recent change to U-Boot (as part of merging http://patchwork.ozlabs.org/patch/293612/), we need cache support for MPC824x, for the linkstation_HGLAN board to continue building, as the network driver is now cache aware. Alternatively, if there is no interest in maintaining the platform upstream anymore, we can remove it. Thanks! -- Tom

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[U-Boot] [PATCH] ARM: HYP/non-sec: Propagate stack pointer to hyp mode
by Ian Campbell 06 Jan '14

06 Jan '14

Some users of the u-boot API (specifically grub) use the initial SP as a hint regarding where to look for the u-boot API signature. Signed-off-by: Ian Campbell <ijc(a)hellion.org.uk> Cc: Marc Zyngier <marc.zyngier(a)arm.com> --- This applies on top of Marc's "ARMv7: add PSCI support to u-boot" and allows me to chainload grub on a cubieboard2. (I don't think that has been applied anywhere yet?) --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 6130a37..2c9e097 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -60,6 +60,10 @@ _secure_monitor: #ifdef CONFIG_ARMV7_VIRT orreq r5, r5, #0x100 @ allow HVC instruction moveq r6, #HYP_MODE @ Enter the kernel as HYP + + mrseq r4, sp_svc @ Propagate SP to HYP mode + msreq sp_hyp, r4 @ it serves as a "hint" to + @ find the u-boot API root. #endif mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set) -- 1.8.4.rc3

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[U-Boot] [PATCH 1/7 V4] mmc: Add some usefull macro definition
by Haijun Zhang 06 Jan '14

06 Jan '14

From: Haijun Zhang <Haijun.Zhang(a)freescale.com> Add command class define. Add mmc erase and secure erase define. Add secure erase and trim support bit define. Signed-off-by: Haijun Zhang <haijun.zhang(a)freescale.com> --- changes for V4: - no changes changes for V3: - No changes include/mmc.h | 50 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/include/mmc.h b/include/mmc.h index cb558da..08f0f3e 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -53,6 +53,7 @@ #define COMM_ERR -18 /* Communications Error */ #define TIMEOUT -19 #define IN_PROGRESS -20 /* operation is in progress */ +#define NOT_SUPPORT -21 /* Operation is not support */ #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 @@ -105,6 +106,39 @@ #define OCR_VOLTAGE_MASK 0x007FFF80 #define OCR_ACCESS_MODE 0x60000000 +/* + * Card Command Classes (CCC) + * + * (0) Basic protocol functions (CMD0,1,2,3,4,7,9,10,12,13,15) + * (and for SPI, CMD58,59) + * (1) Stream read commands (CMD11) + * (2) Block read commands (CMD16,17,18) + * (3) Stream write commands (CMD20) + * (4) Block write commands (CMD16,24,25,26,27) + * (5) Ability to erase blocks (CMD32,33,34,35,36,37,38,39) + * (6) Able to write protect blocks (CMD28,29,30) + * (7) Able to lock down card (CMD16,CMD42) + * (8) Application specific (CMD55,56,57,ACMD*) + * (9) I/O mode (CMD5,39,40,52,53) + * (10) High speed switch (CMD6,34,35,36,37,50) + */ +#define CCC_BASIC (1<<0) +#define CCC_STREAM_READ (1<<1) +#define CCC_BLOCK_READ (1<<2) +#define CCC_STREAM_WRITE (1<<3) +#define CCC_BLOCK_WRITE (1<<4) +#define CCC_ERASE (1<<5) +#define CCC_WRITE_PROT (1<<6) +#define CCC_LOCK_CARD (1<<7) +#define CCC_APP_SPEC (1<<8) +#define CCC_IO_MODE (1<<9) +#define CCC_SWITCH (1<<10) + +#define MMC_ERASE_ARG 0x00000000 +#define MMC_SECURE_ERASE_ARG 0x80000000 +#define MMC_TRIM_ARG 0x00000001 +#define MMC_DISCARD_ARG 0x00000003 + #define SECURE_ERASE 0x80000000 #define MMC_STATUS_MASK (~0x0206BF7F) @@ -160,8 +194,12 @@ #define EXT_CSD_CARD_TYPE 196 /* RO */ #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ +#define EXT_CSD_REL_WR_SEC_C 222 /* RO */ +#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ #define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ +#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ /* * EXT_CSD field definitions @@ -178,6 +216,12 @@ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ +/* EXT_CSD[231] */ +#define EXT_CSD_SEC_ER_EN (1<<0) +#define EXT_CSD_SEC_BD_BLK_EN (1<<2) +#define EXT_CSD_SEC_GB_CL_EN (1<<4) +#define EXT_CSD_SEC_SANITIZE (1<<6) /* v4.5 later */ + #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) @@ -187,7 +231,6 @@ #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) - #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -268,10 +311,15 @@ struct mmc { ushort rca; char part_config; char part_num; + ushort cmdclass; uint tran_speed; uint read_bl_len; uint write_bl_len; uint erase_grp_size; + uint erase_timeout_mult; + char sec_feature_support; + uint sec_erase_mult; + uint sec_erase_timeout; u64 capacity; u64 capacity_user; u64 capacity_boot; -- 1.8.4.1

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