December 2013 - U-Boot

[U-Boot] [PATCH v16 00/10] arm64 patch
by fenghua＠phytium.com.cn 10 Jan '14

10 Jan '14

From: David Feng <fenghua(a)phytium.com.cn> Changes for v16: - make the patches work with latest recently u-boot. add rela relocation type to OBJCFLAGS definition at arm/config.mk. Changes for v15: - modify boot process, u-boot will run at the highest exception level until it prepare jump to OS. - Fix a few bugs in cache.S.These bug is reported by York Sun <yorksun(a)freescale.com> and Scott Wood <scottwood(a)freescale.com>. - when booting, slaves will wait on WFI, master wakeup slaves by SGI interrupt. - add generic_timer.c to utilize the newest timer architecture. - add gic.S to support gic initialization and interrupt operations, currently only support GICv2. Changes for v14: - Merge rela relocation patches from Scott Wood <scottwood(a)freescale.com>. - Remove all CONFIG_NEED_MANUAL_RELOC and other fixups due to manual relocation. With rela relocation patches them are not needed. - Fix the bug of MEMORY_ATTRIBUTES definition due to assembler. That need put brackets around (MT_NORMAL*8). Otherwise the result is wrong.This bug is reported by York Sun <yorksun(a)freescale.com>. - -msoft-float is not supported by aarch64-gcc, make a test though $(call cc-option,-msoft-float). - Adjust the virtual address space to 42 bits. - Filter armv8 boards from LIST_arm in MAKEALL. - remove gpio.h in asm/arch-armv8/ and move mmu.h to asm/armv8/ directory. - remove vexpress64.dts from this patch, it could be accessed from linux kernel. Changes for v13: - fix the bug of board_r.c and arm/lib/board.c due to CONFIG_NEED_MANUAL_RELOC. adjust initr_serial() in board_r.c to the first entry of init_sequence_r[] and relocate serial_initialize() in arm/lib/board.c, routines of serial_device should be relocated firstly by serial_initialize(), so that printf access the correct puts function, otherwise uninitialized serial_current will be selected as the output device. - fix the bug of dcache_enable(). after mmu_setup the sctrl register value should be fetched again because it has been modifed by mmu_seup() function. This bug is reported by York Sun <yorksun(a)freescale.com>. - add macro branch_if_slave to macro.h, it choose processor with all zero affinity value as the master and is used in start.S. Changes for v12: - custom the patches to new format boards.cfg. Changes for v11: - Replace CONFIG_ARMV8 with CONFIG_ARM64. Currently, it's hard to distinguish what is armv8 specific and what is aarch64 specific, so we use CONFIG_ARM64 only, no CONFIG_ARMV8 used. - rename README.armv8 with README.arm64 and make some modification. Changes for v10: - add weak definition to include/linux/linkage.h and make setup_el2/setup_el3/lowlevel_init weak routines, so them can be easily overridden by processor specific code. - modify s-o-f of 0002-board-support-of-vexpress_aemv8a which use wrong mail address of Bhupesh Sharma. Changes for v9: - add Signed-off-by information to patch "board support of vexpress_aemv8a" which SMC91111 support is integrated from Sharma Bhupesh's patch. - adjust pt_regs struct and add exception state preservation in exception.S. Changes for v8: - Integrate SMC91111 patch of sharma bhupesh. - remove v8_outer_cache* which is not need currently. - Change license tag. - Mov crt0.S/relocate.S/interrupts.c to arm/lib and rename them with _64 suffix. - Make el3/el2 initializing process of start.S as two separate routines. It could be easier to be replaced with processor specific codes. - Remove exception stack save and restore routine, it is unnecessary now. - simplify __weak function declaration. Changes for v7: - Check the patches with checkpatch.pl and get rid of almost all warnings. There are a few warnings still, but I think it should be that. - change printf format in cmd_pxe.c, use %zd indtead of %ld to format size_t type variable. - add macro PGTABLE_SIZE to identify tlb table size. Changes for v6: - Make modification to inappropriate licensed file and bugs according to ScottWood's advice. Thanks Scott for his checking to these patches. - Enable u-boot's running at EL1. - Get rid of compiling warnings originated from cmd_pxe.c. Changes for v5: - fix the generic board_f.c, remove zero_global_data from init_sequence_f array and move it to board_init_f() function with CONFIG_X86 switch. The previous fixup is inaccurate. - Replace __ARMEB__ with __AARCH64EB__ in byteorder.h and unaligned.h, gcc for aarch64 use __AARCH64EB__ and __AARCH64EL__ to identify endian. - Some modification to README.armv8 Changes for v4: - merge arm64 to arm architecture. David Feng (10): fdt_support: 64bit initrd start address support cmd_pxe: remove compiling warnings add weak entry definition arm64: Add tool to statically apply RELA relocations arm64: Turn u-boot.bin back into an ELF file after relocate-rela arm64: Make checkarmreloc accept arm64 relocations arm64: core support arm64: generic board support arm64: board support of vexpress_aemv8a arm64: MAKEALL, filter armv8 boards from LIST_arm MAKEALL | 12 +- Makefile | 39 +++++- arch/arm/config.mk | 7 +- arch/arm/cpu/armv8/Makefile | 17 +++ arch/arm/cpu/armv8/cache.S | 136 +++++++++++++++++++ arch/arm/cpu/armv8/cache_v8.c | 219 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/config.mk | 15 +++ arch/arm/cpu/armv8/cpu.c | 43 ++++++ arch/arm/cpu/armv8/exceptions.S | 113 ++++++++++++++++ arch/arm/cpu/armv8/generic_timer.c | 31 +++++ arch/arm/cpu/armv8/gic.S | 106 +++++++++++++++ arch/arm/cpu/armv8/start.S | 164 +++++++++++++++++++++++ arch/arm/cpu/armv8/tlb.S | 34 +++++ arch/arm/cpu/armv8/transition.S | 83 ++++++++++++ arch/arm/cpu/armv8/u-boot.lds | 89 +++++++++++++ arch/arm/include/asm/armv8/mmu.h | 111 ++++++++++++++++ arch/arm/include/asm/byteorder.h | 12 ++ arch/arm/include/asm/cache.h | 5 + arch/arm/include/asm/config.h | 6 + arch/arm/include/asm/gic.h | 49 ++++++- arch/arm/include/asm/global_data.h | 6 +- arch/arm/include/asm/io.h | 15 ++- arch/arm/include/asm/macro.h | 53 ++++++++ arch/arm/include/asm/posix_types.h | 10 ++ arch/arm/include/asm/proc-armv/ptrace.h | 21 +++ arch/arm/include/asm/proc-armv/system.h | 59 ++++++++- arch/arm/include/asm/system.h | 84 ++++++++++++ arch/arm/include/asm/types.h | 4 + arch/arm/include/asm/u-boot.h | 4 + arch/arm/include/asm/unaligned.h | 2 +- arch/arm/lib/Makefile | 20 ++- arch/arm/lib/board.c | 7 +- arch/arm/lib/bootm.c | 24 ++++ arch/arm/lib/crt0_64.S | 113 ++++++++++++++++ arch/arm/lib/interrupts_64.c | 120 +++++++++++++++++ arch/arm/lib/relocate_64.S | 58 ++++++++ board/armltd/vexpress64/Makefile | 8 ++ board/armltd/vexpress64/vexpress64.c | 56 ++++++++ boards.cfg | 1 + common/board_f.c | 20 ++- common/cmd_pxe.c | 4 +- common/fdt_support.c | 66 +++++----- common/image.c | 1 + doc/README.arm64 | 46 +++++++ examples/standalone/stubs.c | 15 +++ include/configs/vexpress_aemv8a.h | 189 ++++++++++++++++++++++++++ include/image.h | 1 + include/linux/linkage.h | 4 + tools/Makefile | 6 + tools/relocate-rela.c | 189 ++++++++++++++++++++++++++ 50 files changed, 2429 insertions(+), 68 deletions(-) create mode 100644 arch/arm/cpu/armv8/Makefile create mode 100644 arch/arm/cpu/armv8/cache.S create mode 100644 arch/arm/cpu/armv8/cache_v8.c create mode 100644 arch/arm/cpu/armv8/config.mk create mode 100644 arch/arm/cpu/armv8/cpu.c create mode 100644 arch/arm/cpu/armv8/exceptions.S create mode 100644 arch/arm/cpu/armv8/generic_timer.c create mode 100644 arch/arm/cpu/armv8/gic.S create mode 100644 arch/arm/cpu/armv8/start.S create mode 100644 arch/arm/cpu/armv8/tlb.S create mode 100644 arch/arm/cpu/armv8/transition.S create mode 100644 arch/arm/cpu/armv8/u-boot.lds create mode 100644 arch/arm/include/asm/armv8/mmu.h create mode 100644 arch/arm/lib/crt0_64.S create mode 100644 arch/arm/lib/interrupts_64.c create mode 100644 arch/arm/lib/relocate_64.S create mode 100644 board/armltd/vexpress64/Makefile create mode 100644 board/armltd/vexpress64/vexpress64.c create mode 100644 doc/README.arm64 create mode 100644 include/configs/vexpress_aemv8a.h create mode 100644 tools/relocate-rela.c -- 1.7.9.5

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[U-Boot] [PATCH 1/3 V2] esdhc: Workaround for card can't be detected on T4240QDS
by Haijun Zhang 10 Jan '14

10 Jan '14

Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board. 1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there. 2. Card detecting pin is functional for SDHC card in Rev2.0. This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0. Signed-off-by: Haijun Zhang <Haijun.Zhang(a)freescale.com> --- changes for V2: - Add the judgement condition for this broken card drivers/mmc/fsl_esdhc.c | 9 +++++++++ include/configs/T4240QDS.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 134a02d..b3b5f37 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -548,6 +548,15 @@ static int esdhc_getcd(struct mmc *mmc) struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000; + /* + * Card detecting pin is not functional on T4240QDS with rev 1.0 SoC. + * Presuming card is present. + */ +#if defined(CONFIG_T4240QDS) + if (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || + IS_SVR_REV(get_svr(), 1, 0)) + return 1; +#endif while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000); diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index c96df54..955e6b9 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -165,6 +165,8 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BRDCFG5 0x55 +#define QIXIS_MUX_SDHC 2 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) #define CONFIG_SYS_CSPR3_EXT (0xf) -- 1.8.4.1

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[U-Boot] [PATCH 0/2 v2] socfpga: Adding Scan Manager
by Chin Liang See 09 Jan '14

09 Jan '14

Adding Scan Manager driver and handoff files. Scan Manager driver will be called to configure the IO buffer setting. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- Changes for v2 - Rebase with latest v2014.01-rc1 Chin Liang See (2): socfpga: Adding Scan Manager driver socfpga: Adding Scan Manager IOCSR handoff files arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/scan_manager.c | 231 +++++++ arch/arm/cpu/armv7/socfpga/spl.c | 4 + arch/arm/include/asm/arch-socfpga/scan_manager.h | 97 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 1 + board/altera/socfpga/iocsr_config.c | 653 ++++++++++++++++++++ board/altera/socfpga/iocsr_config.h | 12 + include/configs/socfpga_cyclone5.h | 1 + 8 files changed, 1000 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/scan_manager.c create mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h create mode 100644 board/altera/socfpga/iocsr_config.c create mode 100644 board/altera/socfpga/iocsr_config.h -- 1.7.9.5

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[U-Boot] [PATCH v3] socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA
by Chin Liang See 09 Jan '14

09 Jan '14

To add the DesignWare MMC driver support for Altera SOCFPGA. It required information such as clocks and bus width from platform specific files (SOCFPGA handoff files) Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: Wolfgang Denk <wd(a)denx.de> --- Changes for v3 - Used structure instead macro for the register access - Made drvsel and smpsel configurable - Used better macro names - Added a documentation on macro used to enable the driver Changes for v2 - Adding u-boot-mmc maintainer --- arch/arm/include/asm/arch-socfpga/dwmmc.h | 12 ++++ arch/arm/include/asm/arch-socfpga/system_manager.h | 65 +++++++++++++++++++ doc/README.socfpga | 53 +++++++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/socfpga_dw_mmc.c | 68 ++++++++++++++++++++ 5 files changed, 199 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/dwmmc.h create mode 100644 doc/README.socfpga create mode 100644 drivers/mmc/socfpga_dw_mmc.c diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h b/arch/arm/include/asm/arch-socfpga/dwmmc.h new file mode 100644 index 0000000..945eb64 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/dwmmc.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_DWMMC_H_ +#define _SOCFPGA_DWMMC_H_ + +extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); + +#endif /* _SOCFPGA_SDMMC_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index d965d25..838d210 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -19,4 +19,69 @@ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; #define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400) +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) + +struct socfpga_system_manager { + u32 siliconid1; + u32 siliconid2; + u32 _pad_0x8_0xf[2]; + u32 wddbg; + u32 bootinfo; + u32 hpsinfo; + u32 parityinj; + u32 fpgaintfgrp_gbl; + u32 fpgaintfgrp_indiv; + u32 fpgaintfgrp_module; + u32 _pad_0x2c_0x2f; + u32 scanmgrgrp_ctrl; + u32 _pad_0x34_0x3f[3]; + u32 frzctrl_vioctrl; + u32 _pad_0x44_0x4f[3]; + u32 frzctrl_hioctrl; + u32 frzctrl_src; + u32 frzctrl_hwctrl; + u32 _pad_0x5c_0x5f; + u32 emacgrp_ctrl; + u32 emacgrp_l3master; + u32 _pad_0x68_0x6f[2]; + u32 dmagrp_ctrl; + u32 dmagrp_persecurity; + u32 _pad_0x78_0x7f[2]; + u32 iswgrp_handoff[8]; + u32 _pad_0xa0_0xbf[8]; + u32 romcodegrp_ctrl; + u32 romcodegrp_cpu1startaddr; + u32 romcodegrp_initswstate; + u32 romcodegrp_initswlastld; + u32 romcodegrp_bootromswstate; + u32 __pad_0xd4_0xdf[3]; + u32 romcodegrp_warmramgrp_enable; + u32 romcodegrp_warmramgrp_datastart; + u32 romcodegrp_warmramgrp_length; + u32 romcodegrp_warmramgrp_execution; + u32 romcodegrp_warmramgrp_crc; + u32 __pad_0xf4_0xff[3]; + u32 romhwgrp_ctrl; + u32 _pad_0x104_0x107; + u32 sdmmcgrp_ctrl; + u32 sdmmcgrp_l3master; + u32 nandgrp_bootstrap; + u32 nandgrp_l3master; + u32 usbgrp_l3master; + u32 _pad_0x11c_0x13f[9]; + u32 eccgrp_l2; + u32 eccgrp_ocram; + u32 eccgrp_usb0; + u32 eccgrp_usb1; + u32 eccgrp_emac0; + u32 eccgrp_emac1; + u32 eccgrp_dma; + u32 eccgrp_can0; + u32 eccgrp_can1; + u32 eccgrp_nand; + u32 eccgrp_qspi; + u32 eccgrp_sdmmc; +}; + #endif /* _SYSTEM_MANAGER_H_ */ diff --git a/doc/README.socfpga b/doc/README.socfpga new file mode 100644 index 0000000..cfcbbfe --- /dev/null +++ b/doc/README.socfpga @@ -0,0 +1,53 @@ + +-------------------------------------------- +SOCFPGA Documentation for U-Boot and SPL +-------------------------------------------- + +This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore +based SOCFPGA. To know more about the hardware itself, please refer to +www.altera.com. + + +-------------------------------------------- +socfpga_dw_mmc +-------------------------------------------- +Here are macro and detailed configuration required to enable DesignWare SDMMC +controller support within SOCFPGA + +#define CONFIG_MMC +-> To enable the SD MMC framework support + +#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) +-> The base address of CSR register for DesignWare SDMMC controller + +#define CONFIG_GENERIC_MMC +-> Enable the generic MMC driver + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM + +#define CONFIG_DWMMC +-> Enable the common DesignWare SDMMC controller framework + +#define CONFIG_SOCFPGA_DWMMC +-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +-> The FIFO depth for SOCFPGA DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to +the card to meet hold time requirements. SD clock is running at 50MHz and +drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time +is 135 / 360 * 20ns = 7.5ns. + +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +-> Phase-shifted clock of sdmmc_clk used to sample the command and data from +the card + +#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 +-> Bus width of data line which either 1, 4 or 8 and based on board routing. + +#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 +-> The clock rate to controller. Do note the controller have a wrapper which +divide the clock from PLL by 4. diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 1ed26ca..e793ed9 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o +obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o else diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c new file mode 100644 index 0000000..bc53a5d --- /dev/null +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <dwmmc.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> + +static const struct socfpga_clock_manager *clock_manager_base = + (void *)SOCFPGA_CLKMGR_ADDRESS; +static const struct socfpga_system_manager *system_manager_base = + (void *)SOCFPGA_SYSMGR_ADDRESS; + +static char *SOCFPGA_NAME = "SOCFPGA DWMMC"; + +static void socfpga_dwmci_clksel(struct dwmci_host *host) +{ + unsigned int drvsel; + unsigned int smplsel; + + /* Disable SDMMC clock. */ + clrbits_le32(&clock_manager_base->per_pll_en, + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + + /* Configures drv_sel and smpl_sel */ + drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; + smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; + + debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); + writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), + &system_manager_base->sdmmcgrp_ctrl); + + debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, + readl(&system_manager_base->sdmmcgrp_ctrl)); + + /* Enable SDMMC clock */ + setbits_le32(&clock_manager_base->per_pll_en, + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); +} + +int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) +{ + struct dwmci_host *host = NULL; + host = calloc(sizeof(struct dwmci_host), 1); + if (!host) { + printf("dwmci_host calloc fail!\n"); + return -1; + } + + host->name = SOCFPGA_NAME; + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + host->clksel = socfpga_dwmci_clksel; + host->dev_index = index; + /* fixed clock divide by 4 which due to the SDMMC wrapper */ + host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ; + host->fifoth_val = MSIZE(0x2) | + RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) | + TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2); + + return add_dwmci(host, host->bus_hz, 400000); +} + -- 1.7.9.5

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[U-Boot] [PATCH V2] mmc: add setdsr support
by Markus Niebel 09 Jan '14

09 Jan '14

From: Markus Niebel <Markus.Niebel(a)tqs.de> The eMMC and the SD-Card specifications describe the optional SET_DSR command. During measurements at our lab we found that some cards implementing this feature having really strong driver strengts per default. This can lead to voltage peaks above the specification of the host on signal edges for data sent from a card to the host. Since availability of a given card type may be shorter than the time a certain hardware will be produced it is useful to have support for this command (Alternative would be changing termination resistors and adapting the driver strength of the host to the used card.) Following proposal for an implementation: - new field that reflects CSD field DSR_IMP in struct mmc - new field for design specific DSR value in struct mmc - board code can set DSR value in mmc struct just after registering an controller - mmc_startup sends the the stored DSR value before selecting a card, if DSR_IMP is set Additionally the mmc command is extended to make is possible to play around with different DSR values. The concept was tested on a i.MX53 based platform using a Micron eMMC card where the default DSR is 0x0400 (12mA) but in our design 0x0100 (0x0100) were enough. To use this feature for instance on a mx53loco one have to add a call to mmc_set_dsr() in board_mmc_init() after calling fsl_esdhc_initialize() for the eMMC. Signed-off-by: Markus Niebel <Markus.Niebel(a)tqs.de> --- changes for V2: - extend documentation according to the comments from Pantelis Antoniou common/cmd_mmc.c | 23 +++++++++++++++++++++++ drivers/mmc/mmc.c | 18 ++++++++++++++++++ include/mmc.h | 3 +++ 3 files changed, 44 insertions(+) diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 67a94a7..da5fef9 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -340,6 +340,28 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_SUPPORT_EMMC_BOOT */ } + + else if (argc == 3 && strcmp(argv[1], "setdsr") == 0) { + struct mmc *mmc = find_mmc_device(curr_device); + u32 val = simple_strtoul(argv[2], NULL, 16); + int ret; + + if (!mmc) { + printf("no mmc device at slot %x\n", curr_device); + return 1; + } + ret = mmc_set_dsr(mmc, val); + printf("set dsr %s\n", (!ret) ? "OK, force rescan" : "ERROR"); + if (!ret) { + mmc->has_init = 0; + if (mmc_init(mmc)) + return 1; + else + return 0; + } + return ret; + } + state = MMC_INVALID; if (argc == 5 && strcmp(argv[1], "read") == 0) state = MMC_READ; @@ -423,5 +445,6 @@ U_BOOT_CMD( "mmc bootpart <device num> <boot part size MB> <RPMB part size MB>\n" " - change sizes of boot and RPMB partitions of specified device\n" #endif + "mmc setdsr - set DSR register value\n" ); #endif /* !CONFIG_GENERIC_MMC */ diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index e1461a9..c6a1c23 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -877,6 +877,7 @@ static int mmc_startup(struct mmc *mmc) mmc->tran_speed = freq * mult; + mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); if (IS_SD(mmc)) @@ -907,6 +908,14 @@ static int mmc_startup(struct mmc *mmc) if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) mmc->write_bl_len = MMC_MAX_BLOCK_LEN; + if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { + cmd.cmdidx = MMC_CMD_SET_DSR; + cmd.cmdarg = (mmc->dsr & 0xffff) << 16; + cmd.resp_type = MMC_RSP_NONE; + if (mmc_send_cmd(mmc, &cmd, NULL)) + printf("MMC: SET_DSR failed\n"); + } + /* Select the card, and put it into Transfer Mode */ if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ cmd.cmdidx = MMC_CMD_SELECT_CARD; @@ -1163,6 +1172,9 @@ static int mmc_send_if_cond(struct mmc *mmc) int mmc_register(struct mmc *mmc) { + /* Setup dsr related values */ + mmc->dsr_imp = 0; + mmc->dsr = 0xffffffff; /* Setup the universal parts of the block interface just once */ mmc->block_dev.if_type = IF_TYPE_MMC; mmc->block_dev.dev = cur_dev_num++; @@ -1280,6 +1292,12 @@ int mmc_init(struct mmc *mmc) return err; } +int mmc_set_dsr(struct mmc *mmc, u16 val) +{ + mmc->dsr = val; + return 0; +} + /* * CPU and board-specific MMC initializations. Aliased function * signals caller to move on diff --git a/include/mmc.h b/include/mmc.h index cb558da..facb819 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -262,6 +262,8 @@ struct mmc { uint card_caps; uint host_caps; uint ocr; + uint dsr; + uint dsr_imp; uint scr[2]; uint csd[4]; uint cid[4]; @@ -304,6 +306,7 @@ int board_mmc_getcd(struct mmc *mmc); int mmc_switch_part(int dev_num, unsigned int part_num); int mmc_getcd(struct mmc *mmc); int mmc_getwp(struct mmc *mmc); +int mmc_set_dsr(struct mmc *mmc, u16 val); void spl_mmc_load(void) __noreturn; /* Function to change the size of boot partition and rpmb partitions */ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, -- 1.7.9.5

2 2

[U-Boot] [PATCH] mmc: Minor cleanup of sdhci.c
by Darwin Rambo 09 Jan '14

09 Jan '14

Fixup prints to show where the print is done from, and a few minor formatting/grammar issues. Signed-off-by: Darwin Rambo <drambo(a)broadcom.com> --- drivers/mmc/sdhci.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 46ae9cb..1e86b92 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -24,7 +24,8 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { if (timeout == 0) { - printf("Reset 0x%x never completed.\n", (int)mask); + printf("%s: Reset 0x%x never completed.\n", + __func__, (int)mask); return; } timeout--; @@ -79,7 +80,8 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, do { stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) { - printf("Error detected in status(0x%X)!\n", stat); + printf("%s: Error detected in status(0x%X)!\n", + __func__, stat); return -1; } if (stat & rdy) { @@ -102,7 +104,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, if (timeout-- > 0) udelay(10); else { - printf("Transfer data timeout\n"); + printf("%s: Transfer data timeout\n", __func__); return -1; } } while (!(stat & SDHCI_INT_DATA_END)); @@ -147,7 +149,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { if (time >= cmd_timeout) { - printf("MMC: %d busy ", mmc_dev); + printf("%s: MMC: %d busy ", __func__, mmc_dev); if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) { cmd_timeout += cmd_timeout; printf("timeout increasing to: %u ms.\n", @@ -179,7 +181,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (data) flags |= SDHCI_CMD_DATA; - /*Set Transfer mode regarding to data flag*/ + /* Set Transfer mode regarding to data flag */ if (data != 0) { sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); mode = SDHCI_TRNS_BLK_CNT_EN; @@ -230,7 +232,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) return 0; else { - printf("Timeout for status update!\n"); + printf("%s: Timeout for status update!\n", __func__); return TIMEOUT; } } @@ -307,7 +309,8 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) & SDHCI_CLOCK_INT_STABLE)) { if (timeout == 0) { - printf("Internal clock never stabilised.\n"); + printf("%s: Internal clock never stabilised.\n", + __func__); return -1; } timeout--; @@ -397,7 +400,8 @@ int sdhci_init(struct mmc *mmc) if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { aligned_buffer = memalign(8, 512*1024); if (!aligned_buffer) { - printf("Aligned buffer alloc failed!!!"); + printf("%s: Aligned buffer alloc failed!!!\n", + __func__); return -1; } } @@ -418,8 +422,8 @@ int sdhci_init(struct mmc *mmc) } /* Enable only interrupts served by the SD controller */ - sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK - , SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, + SDHCI_INT_ENABLE); /* Mask all sdhci interrupt sources */ sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); @@ -433,7 +437,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) mmc = malloc(sizeof(struct mmc)); if (!mmc) { - printf("mmc malloc fail!\n"); + printf("%s: mmc malloc fail!\n", __func__); return -1; } @@ -450,7 +454,8 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) caps = sdhci_readl(host, SDHCI_CAPABILITIES); #ifdef CONFIG_MMC_SDMA if (!(caps & SDHCI_CAN_DO_SDMA)) { - printf("Your controller don't support sdma!!\n"); + printf("%s: Your controller doesn't support SDMA!!\n", + __func__); return -1; } #endif @@ -467,7 +472,8 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) mmc->f_max *= 1000000; } if (mmc->f_max == 0) { - printf("Hardware doesn't specify base clock frequency\n"); + printf("%s: Hardware doesn't specify base clock frequency\n", + __func__); return -1; } if (min_clk) -- 1.7.9.5

3 3

[U-Boot] [PATCH v2] mmc/dwmmc: use bounce buffer for data exchange between CPU and MMC controller
by Alexey Brodkin 09 Jan '14

09 Jan '14

Bounce buffer implementation takes care of proper data buffer alignemt and correct flush/invalidation of data cache at once so we no longer depend on input data variety and make sure CPU and MMC controller deal with expected data in case of enabled data cache. Bounce buffer requires to add its definition (CONFIG_BOUNCE_BUFFER) in board configuration, otherwise corresponding library won't be compiled and linker will fail to build resulting executable. Difference since v1 - fixed compile-time warning with type casting to "void *": ==== passing argument 2 of ‘bounce_buffer_start’ discards ‘const’ qualifier from pointer target type ==== Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Mischa Jonker <mjonker(a)synopsys.com> Cc: Alim Akhtar <alim.akhtar(a)samsung.com> Cc: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Amar <amarendra.xt(a)samsung.com> Cc: Kyungmin Park <kyungmin.park(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: Andy Fleming <afleming(a)gmail.com> --- drivers/mmc/dw_mmc.c | 32 ++++++++++++++++++++++---------- include/configs/arndale.h | 1 + include/configs/exynos5250-dt.h | 1 + 3 files changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 19d9b0b..1e34f36 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <bouncebuf.h> #include <common.h> #include <malloc.h> #include <mmc.h> @@ -41,11 +42,13 @@ static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, } static void dwmci_prepare_data(struct dwmci_host *host, - struct mmc_data *data, struct dwmci_idmac *cur_idmac) + struct mmc_data *data, + struct dwmci_idmac *cur_idmac, + void *bounce_buffer) { unsigned long ctrl; unsigned int i = 0, flags, cnt, blk_cnt; - ulong data_start, data_end, start_addr; + ulong data_start, data_end; blk_cnt = data->blocks; @@ -55,11 +58,6 @@ static void dwmci_prepare_data(struct dwmci_host *host, data_start = (ulong)cur_idmac; dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac); - if (data->flags == MMC_DATA_READ) - start_addr = (unsigned int)data->dest; - else - start_addr = (unsigned int)data->src; - do { flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; @@ -70,7 +68,7 @@ static void dwmci_prepare_data(struct dwmci_host *host, cnt = data->blocksize * 8; dwmci_set_idma_desc(cur_idmac, flags, cnt, - start_addr + (i * PAGE_SIZE)); + (u32)bounce_buffer + (i * PAGE_SIZE)); if (blk_cnt <= 8) break; @@ -117,6 +115,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, u32 retry = 10000; u32 mask, ctrl; ulong start = get_timer(0); + struct bounce_buffer bbstate; while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { if (get_timer(start) > timeout) { @@ -127,8 +126,19 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); - if (data) - dwmci_prepare_data(host, data, cur_idmac); + if (data) { + if (data->flags == MMC_DATA_READ) { + bounce_buffer_start(&bbstate, (void*)data->dest, + data->blocksize * + data->blocks, GEN_BB_WRITE); + } else { + bounce_buffer_start(&bbstate, (void*)data->src, + data->blocksize * + data->blocks, GEN_BB_READ); + } + dwmci_prepare_data(host, data, cur_idmac, + bbstate.bounce_buffer); + } dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); @@ -204,6 +214,8 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, ctrl = dwmci_readl(host, DWMCI_CTRL); ctrl &= ~(DWMCI_DMA_EN); dwmci_writel(host, DWMCI_CTRL, ctrl); + + bounce_buffer_stop(&bbstate); } udelay(100); diff --git a/include/configs/arndale.h b/include/configs/arndale.h index a3cb56b..3d29caf 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -85,6 +85,7 @@ #define CONFIG_DWMMC #define CONFIG_EXYNOS_DWMMC #define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_BOUNCE_BUFFER #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 8fb904c..b39bafc 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -102,6 +102,7 @@ #define CONFIG_DWMMC #define CONFIG_EXYNOS_DWMMC #define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_BOUNCE_BUFFER #define CONFIG_BOARD_EARLY_INIT_F -- 1.8.4.2

3 2

[U-Boot] [PATCH 00/11 V13] EXYNOS5420: Add SMDK5420 board support
by Rajeshwari S Shinde 08 Jan '14

08 Jan '14

This patch adds basic board support for SMDK5420 board. These patches are tested for booting fine on EVT1 SMDK5420. Rajeshwari S Shinde (11): EXYNOS5: Create a common board file Exynos5420: Add base addresses for 5420 EXYNOS5420: Add power register structure. EXYNOS5420: Add dmc and phy_control register structure Exynos5420: Add clock initialization for 5420 Exynos5420: Add DDR3 initialization for 5420 Exynos5420: Add support for 5420 in pinmux and gpio Exynos5420: Add base patch for SMDK5420 DTS: Add dts support for SMDK5420 Config: Add initial config for SMDK5420 SPL: EXYNOS: Prepare for variable size SPL support arch/arm/cpu/armv7/exynos/clock.c | 279 ++++++++- arch/arm/cpu/armv7/exynos/clock_init.h | 17 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 352 ++++++++++- arch/arm/cpu/armv7/exynos/dmc_common.c | 60 +- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 439 ++++++++++++- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 764 ++++++++++++++++------ arch/arm/cpu/armv7/exynos/pinmux.c | 260 +++++++- arch/arm/dts/exynos5.dtsi | 198 ++++++ arch/arm/dts/exynos5250.dtsi | 194 +----- arch/arm/dts/exynos5420.dtsi | 70 +++ arch/arm/include/asm/arch-exynos/board.h | 17 + arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 494 +++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 52 +- arch/arm/include/asm/arch-exynos/dmc.h | 177 ++++++ arch/arm/include/asm/arch-exynos/gpio.h | 143 ++++- arch/arm/include/asm/arch-exynos/periph.h | 3 + arch/arm/include/asm/arch-exynos/power.h | 837 +++++++++++++++++++++++++ board/samsung/common/Makefile | 4 + board/samsung/common/board.c | 408 ++++++++++++ board/samsung/dts/exynos5420-smdk5420.dts | 169 +++++ board/samsung/smdk5250/exynos5-dt.c | 350 +---------- board/samsung/smdk5250/smdk5250.c | 182 +----- board/samsung/smdk5420/Makefile | 11 + board/samsung/smdk5420/smdk5420.c | 159 +++++ board/samsung/smdk5420/smdk5420_spl.c | 52 ++ boards.cfg | 1 + include/configs/arndale.h | 1 + include/configs/exynos5-dt.h | 290 +++++++++ include/configs/exynos5250-dt.h | 284 +-------- include/configs/smdk5420.h | 56 ++ spl/Makefile | 7 +- tools/Makefile | 3 +- tools/mkexynosspl.c | 167 +++-- 34 files changed, 5187 insertions(+), 1314 deletions(-) create mode 100644 arch/arm/dts/exynos5.dtsi create mode 100644 arch/arm/dts/exynos5420.dtsi create mode 100644 arch/arm/include/asm/arch-exynos/board.h create mode 100644 board/samsung/common/board.c create mode 100644 board/samsung/dts/exynos5420-smdk5420.dts create mode 100644 board/samsung/smdk5420/Makefile create mode 100644 board/samsung/smdk5420/smdk5420.c create mode 100644 board/samsung/smdk5420/smdk5420_spl.c create mode 100644 include/configs/exynos5-dt.h create mode 100644 include/configs/smdk5420.h -- 1.7.12.4

3 13

[U-Boot] [PATCH] ARM: omap5_uevm: Enable 8-bit eMMC access
by Lubomir Popov 08 Jan '14

08 Jan '14

All prerequisites are already available, so why not enable 8-bit access - it is a matter of a define in the board file only. Signed-off-by: Lubomir Popov <l-popov(a)ti.com> --- include/configs/omap5_uevm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 96b5f23..3c479db 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -36,6 +36,7 @@ #define CONFIG_EFI_PARTITION #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART +#define CONFIG_HSMMC2_8BIT /* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X -- 1.7.9.5

2 1

[U-Boot] [PATCH v2] mmc/dwmmc: Using calloc instead malloc
by Chin Liang See 08 Jan '14

08 Jan '14

To enhance the SDMMC DesignWare driver to use calloc instead of malloc. This will avoid the incident that uninitialized members of mmc structure are later used for NULL comparison. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Mischa Jonker <mjonker(a)synopsys.com> Cc: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Andy Fleming <afleming(a)freescale.com> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> --- Changes for v2 - Adding u-boot-mmc maintainer --- drivers/mmc/dw_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) mode change 100644 => 100755 drivers/mmc/dw_mmc.c diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c old mode 100644 new mode 100755 index 19d9b0b..82abe19 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -336,9 +336,9 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) struct mmc *mmc; int err = 0; - mmc = malloc(sizeof(struct mmc)); + mmc = calloc(sizeof(struct mmc), 1); if (!mmc) { - printf("mmc malloc fail!\n"); + printf("mmc calloc fail!\n"); return -1; } -- 1.7.9.5

2 1