November 2013 - U-Boot

[U-Boot] [PATCH 1/4] udoo: Add Ethernet support.
by Giuseppe Pagano 07 Nov '13

07 Nov '13

Add Ethernet and networking support on uDoo board (FEC + phy Micrel) Signed-off-by: Giuseppe Pagano <giuseppe.pagano(a)seco.com> Cc: sbabic(a)denx.de --- diff -uNr a/board/udoo/udoo.c b/board/udoo/udoo.c --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -9,6 +9,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> +#include <malloc.h> #include <asm/arch/mx6-pins.h> #include <asm/errno.h> #include <asm/gpio.h> @@ -18,6 +19,9 @@ #include <asm/arch/crm_regs.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> +#include <micrel.h> +#include <miiphy.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +29,9 @@ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -58,6 +65,99 @@ MX6_PAD_EIM_D19__GPIO_3_19, }; +int mx6_rgmii_rework(struct phy_device *phydev) +{ + /* To advertise only 10 Mbs */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x4, 0x61); + phy_write(phydev, MDIO_DEVAD_NONE, 0x9, 0x0c00); + + /* enable master mode, force phy to 100Mbps */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x9, 0x1c00); + + /* min rx data delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x0b, 0x8105); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0c, 0x0000); + + /* max rx/tx clock delay, min rx/tx control delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x0b, 0x8104); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0c, 0xf0f0); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0b, 0x104); + + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0x03FF); + return 0; +} + +static iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* RGMII reset */ + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* alimentazione ethernet*/ + MX6_PAD_EIM_EB3__GPIO_2_31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + udelay(20); + gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power on of enet */ + + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ + + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + udelay(1000 * 10); + + gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY rst */ + /* Need delay 100ms according to KSZ9031 spec */ + udelay(1000 * 100); + + gpio_free(IMX_GPIO_NR(6, 24)); + gpio_free(IMX_GPIO_NR(6, 25)); + gpio_free(IMX_GPIO_NR(6, 27)); + gpio_free(IMX_GPIO_NR(6, 28)); + gpio_free(IMX_GPIO_NR(6, 29)); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); @@ -77,6 +177,37 @@ return 1; /* Always present */ } +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + int board_mmc_init(bd_t *bis) { imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); @@ -94,6 +225,15 @@ return 0; } +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + int board_init(void) { /* address of boot parameters */ diff -uNr a/include/configs/udoo.h b/include/configs/udoo.h --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -34,6 +34,22 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +/* Network support */ + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1

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[U-Boot] [PATCH 2/4] udoo: Add SATA disk support.
by Giuseppe Pagano 07 Nov '13

07 Nov '13

Add Sata support on uDoo Board. Signed-off-by: Giuseppe Pagano <giuseppe.pagano(a)seco.com> Cc: sbabic(a)denx.de --- diff -uNr a/board/udoo/udoo.c b/board/udoo/udoo.c --- a/board/udoo/udoo.c 2013-11-06 18:45:22.000000000 +0100 +++ b/board/udoo/udoo.c 2013-11-06 18:46:00.000000000 +0100 @@ -208,6 +208,32 @@ return 0; } +#ifdef CONFIG_CMD_SATA +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) + |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED + |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 + |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB + |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V + |IOMUXC_GPR13_SATA_PHY_1_SLOW); + + return 0; +} +#endif + int board_mmc_init(bd_t *bis) { imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); @@ -239,6 +265,9 @@ /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif return 0; } diff -uNr a/include/configs/udoo.h b/include/configs/udoo.h --- a/include/configs/udoo.h 2013-11-06 18:45:22.000000000 +0100 +++ b/include/configs/udoo.h 2013-11-06 18:46:27.000000000 +0100 @@ -34,6 +34,19 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CMD_SATA +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + /* Network support */ #define CONFIG_CMD_PING

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[U-Boot] [PATCH 3/4] udoo: Adjust default boot envirnment
by Giuseppe Pagano 07 Nov '13

07 Nov '13

Change u-boot default environment for uDoo board to: - mount /dev/mmcblk0p1 partition - activate hdmi monitor by default (instead of nothing) Signed-off-by: Giuseppe Pagano <giuseppe.pagano(a)seco.com> Cc: sbabic(a)denx.de --- diff -uNr a/include/configs/udoo.h b/include/configs/udoo.h --- a/include/configs/udoo.h 2013-11-06 18:51:57.000000000 +0100 +++ b/include/configs/udoo.h 2013-11-06 18:52:16.000000000 +0100 @@ -100,7 +100,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "uimage=/boot/uImage\0" \ "console=ttymxc1\0" \ "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ @@ -111,7 +111,7 @@ "ip_dyn=yes\0" \ "mmcdev=0\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \ "update_sd_firmware_filename=u-boot.imx\0" \ "update_sd_firmware=" \ "if test ${ip_dyn} = yes; then " \ @@ -127,13 +127,14 @@ "fi; " \ "fi\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ + "root=${mmcroot} rootwait rw " \ + "fbmem=24M video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24\0" \ "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ @@ -189,7 +190,7 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_PROMPT "uDoo board >" #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256

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[U-Boot] [PATCH 4/4] udoo: fix watchdog setting
by Giuseppe Pagano 07 Nov '13

07 Nov '13

To have watchdog quiet during kernel boot it is necessary to change gpio wdt trigger direction. Signed-off-by: Giuseppe Pagano <giuseppe.pagano(a)seco.com> Cc: sbabic(a)denx.de --- diff -uNr a/board/udoo/udoo.c b/board/udoo/udoo.c --- a/board/udoo/udoo.c 2013-11-06 18:47:26.000000000 +0100 +++ b/board/udoo/udoo.c 2013-11-06 18:54:46.000000000 +0100 @@ -168,6 +168,7 @@ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); gpio_direction_output(WDT_TRG, 0); gpio_direction_output(WDT_EN, 1); + gpio_direction_input(WDT_TRG); } static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };

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[U-Boot] [PATCH 0/4] udoo: Improve stability of DDR3 setting
by Giuseppe Pagano 07 Nov '13

07 Nov '13

Move udoo configuration files to board/udoo/ folder. Align clock configuration and DDR3 calibration to Seco suggested value to increase system stability. Signed-off-by: Giuseppe Pagano <giuseppe.pagano(a)seco.com> Cc: sbabic(a)denx.de ... diff -uNr a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg --- a/board/udoo/1066mhz_4x256mx16.cfg +++ b/board/udoo/1066mhz_4x256mx16.cfg @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB + +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 + +DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 + +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 + +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 + +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 + +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 + +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + diff -uNr a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg --- a/board/udoo/clocks.cfg +++ b/board/udoo/clocks.cfg @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + diff -uNr a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg --- a/board/udoo/ddr-setup.cfg +++ b/board/udoo/ddr-setup.cfg @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + diff -uNr a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg --- a/board/udoo/udoo.cfg +++ b/board/udoo/udoo.cfg @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff -uNr a/boards.cfg b/boards.cfg --- a/boards.cfg +++ b/boards.cfg @@ -283,7 +283,7 @@ Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic(a)denx.de> -Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.este...(a)freescale.com> +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.este...(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam(a)freescale.com> Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam(a)freescale.com>

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[U-Boot] Pull request: u-boot-imx
by Stefano Babic 07 Nov '13

07 Nov '13

Hi Albert, please pull from u-boot-imx, thanks ! The following changes since commit 262f08d6ea18a62f827b8ccb60f355ca2eaf6e2b: zynq: Use arch_cpu_init() instead of lowlevel_init() (2013-10-17 08:34:45 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to c93addb5635630847e8a33f6dba4afef78a6d180: wandboard: README: Include the quad version (2013-11-04 09:56:25 +0100) ---------------------------------------------------------------- Anatolij Gustschin (1): imx_watchdog: do not soft-reset while watchdog init Christoph G. Baumann (1): ARM: mxs: Configure 2 Gbit DDR2 RAM for BG0900 Eric Nelson (1): i.MX6: nitrogen6x: fix erase size in 6x_upgrade.txt Fabio Estevam (5): udoo: Add initial support for mx6q udoo board ARM: mx5: Enable L2 cache mx5: lowlevel_init: Remove unused macro configs: imx: Make CONFIG_SYS_PROMPT uniform across FSL boards wandboard: README: Include the quad version Marek Vasut (4): ARM: mxs: tools: Use mkimage for BootStream generation ARM: mxs: Add PPC-AG BG0900 board ARM: mxs: Setup stack in JTAG mode ARM: mxs: Enable DCDC converter for battery boot Otavio Salvador (1): mx6: Remove PAD_CTL_DSE_120ohm from i.MX6DL's IPU1_DI0_PIN4 pin Pierre Aubert (1): mx6: compute PLL PFD frequencies rather than using defines Stefano Babic (1): Revert "configs: imx: Make CONFIG_SYS_PROMPT uniform across FSL boards" arch/arm/cpu/arm926ejs/mxs/Makefile | 11 +- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 4 +- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg | 4 +- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 + arch/arm/cpu/arm926ejs/mxs/start.S | 9 ++ arch/arm/cpu/armv7/mx5/lowlevel_init.S | 12 +- arch/arm/cpu/armv7/mx6/clock.c | 56 +++++-- arch/arm/include/asm/arch-mx6/crm_regs.h | 11 -- arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 2 +- arch/arm/include/asm/arch-mxs/sys_proto.h | 2 + board/boundary/nitrogen6x/6x_upgrade.txt | 2 +- board/ppcag/bg0900/Makefile | 31 ++++ board/ppcag/bg0900/bg0900.c | 86 +++++++++++ board/ppcag/bg0900/spl_boot.c | 153 +++++++++++++++++++ board/udoo/Makefile | 26 ++++ board/udoo/udoo.c | 110 ++++++++++++++ board/wandboard/README | 4 +- boards.cfg | 2 + doc/README.mxs | 39 ++++- drivers/watchdog/imx_watchdog.c | 3 +- include/configs/bg0900.h | 97 ++++++++++++ include/configs/udoo.h | 206 ++++++++++++++++++++++++++ 22 files changed, 819 insertions(+), 53 deletions(-) create mode 100644 board/ppcag/bg0900/Makefile create mode 100644 board/ppcag/bg0900/bg0900.c create mode 100644 board/ppcag/bg0900/spl_boot.c create mode 100644 board/udoo/Makefile create mode 100644 board/udoo/udoo.c create mode 100644 include/configs/bg0900.h create mode 100644 include/configs/udoo.h -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[U-Boot] test
by Igor Grinberg 07 Nov '13

07 Nov '13

test -- Regards, Igor.

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[U-Boot] ARM: interrupt_init before relocation, write fails
by Joe Kulikauskas 07 Nov '13

07 Nov '13

Hi, v2013.10-rc1 (and after) has a patch ( http://lists.denx.de/pipermail/u-boot/2013-June/156298.html) which sets up the abort stack before relocation. However, what I am seeing: IRQ_STACK_START_IN is in flash at that time, so this write fails. interrupt_init: FF0A0FA8 e59f3010 LDR R3,ff0a0fc0 (ff0a0050=IRQ_STACK_START_IN) Before this patch, abort stack setup was done after relocation, so target location is in RAM and writeable. interrupt_init: 9FFB4020 e59f3010 LDR R3,9ffb4038 (9ffb3054=IRQ_STACK_START_IN) If I revert that patch, I don't see that problem. Joe Kulikauskas

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[U-Boot] [U-boot] CONFIG_LOGBUFFER and _POST_WORD_ADDR
by TigerLiu＠viatech.com.cn 07 Nov '13

07 Nov '13

Hi, experts: I tried to turn on log buffer function by defined CONFIG_LOGBUFFER. When compiled source code, it tips: Should define _POST_WORD_ADDR . But i think: _POST_WORD_ADDR is not related with CONFIG_LOGBUFFER. _POST_WORD_ADDR is justed related with CONFIG_POST So, should revise include/post.h file. Best wishes,

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[U-Boot] [PATCH] freescale: p1_p2_rdb_pc: rename COBJS-y to obj-y
by Masahiro Yamada 07 Nov '13

07 Nov '13

Signed-off-by: Masahiro Yamada <yamada.m(a)jp.panasonic.com> --- board/freescale/p1_p2_rdb_pc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile index 8e20073..a2a1f92 100644 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -18,7 +18,7 @@ obj-y += spl_minimal.o tlb.o law.o else ifdef CONFIG_SPL_BUILD -COBJS-y += spl.o +obj-y += spl.o endif obj-y += p1_p2_rdb_pc.o -- 1.8.3.2

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