September 2012 - U-Boot

[U-Boot] [PATCH] omap4_panda: remove CONFIG_PANDA, not used
by Peter Meerwald 28 Sep '12

28 Sep '12

From: Peter Meerwald <p.meerwald(a)bct-electronic.com> Signed-off-by: Peter Meerwald <pmeerw(a)pmeerw.net> --- include/configs/omap4_panda.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index b4756be..eacb5f5 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -31,7 +31,6 @@ /* * High Level Configuration Options */ -#define CONFIG_PANDA /* working with Panda */ /* USB UHH support options */ #define CONFIG_CMD_USB -- 1.7.9.5

2 1

[U-Boot] [PATCH v4 1/2] ARM: Add Altera SOCFPGA Cyclone5
by dinguyen＠altera.com 28 Sep '12

28 Sep '12

From: Dinh Nguyen <dinguyen(a)altera.com> Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Applied on top of trini/WIP/spl-improvements v6 Signed-off-by: Dinh Nguyen <dinguyen(a)altera.com> Signed-off-by: Chin Liang See <clsee(a)altera.com> Signed-off-by: Pavel Machek <pavel(a)denx.de> --- MAINTAINERS | 5 + arch/arm/cpu/armv7/socfpga/Makefile | 51 +++++ arch/arm/cpu/armv7/socfpga/config.mk | 16 ++ arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 77 +++++++ arch/arm/cpu/armv7/socfpga/misc.c | 55 +++++ arch/arm/cpu/armv7/socfpga/spl.c | 48 ++++ arch/arm/cpu/armv7/socfpga/timer.c | 105 +++++++++ arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 57 +++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 36 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 27 +++ arch/arm/include/asm/arch-socfpga/spl.h | 26 +++ arch/arm/include/asm/arch-socfpga/timer.h | 29 +++ board/altera/socfpga_cyclone5/Makefile | 50 ++++ board/altera/socfpga_cyclone5/socfpga_cyclone5.c | 85 +++++++ boards.cfg | 1 + include/common.h | 2 +- include/configs/socfpga_cyclone5.h | 240 ++++++++++++++++++++ 17 files changed, 909 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/Makefile create mode 100644 arch/arm/cpu/armv7/socfpga/config.mk create mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/socfpga/misc.c create mode 100644 arch/arm/cpu/armv7/socfpga/spl.c create mode 100644 arch/arm/cpu/armv7/socfpga/timer.c create mode 100644 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-socfpga/reset_config.h create mode 100644 arch/arm/include/asm/arch-socfpga/reset_manager.h create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h create mode 100644 arch/arm/include/asm/arch-socfpga/spl.h create mode 100644 arch/arm/include/asm/arch-socfpga/timer.h create mode 100644 board/altera/socfpga_cyclone5/Makefile create mode 100644 board/altera/socfpga_cyclone5/socfpga_cyclone5.c create mode 100644 include/configs/socfpga_cyclone5.h diff --git a/MAINTAINERS b/MAINTAINERS index c5a6f2f..df48dea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -765,6 +765,11 @@ Nagendra T S <nagendra(a)mistralsolutions.com> am3517_crane ARM ARMV7 (AM35x SoC) +Dinh Nguyen <dinguyen(a)altera.com> +Chin Liang See <clsee(a)altera.com> + + socfpga socfpga_cyclone5 + Kyungmin Park <kyungmin.park(a)samsung.com> apollon ARM1136EJS diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile new file mode 100644 index 0000000..376a4bd --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Copyright (C) 2012 Altera Corporation <www.altera.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS-y := misc.o timer.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk new file mode 100644 index 0000000..b72ed1e --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/config.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +ifndef CONFIG_SPL_BUILD +ALL-y += $(obj)u-boot.img +endif diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S new file mode 100644 index 0000000..001b37d --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <config.h> +#include <version.h> + +/* Save the parameter pass in by previous boot loader */ +.global save_boot_params +save_boot_params: + /* save the parameter here */ + + /* + * Setup stack for exception, which is located + * at the end of on-chip RAM. We don't expect exception prior to + * relocation and if that happens, we won't worry -- it will overide + * global data region as the code will goto reset. After relocation, + * this region won't be used by other part of program. + * Hence it is safe. + */ + ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) + ldr r1, =IRQ_STACK_START_IN + str r0, [r1] + + bx lr + + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + + /* Remap */ +#ifdef CONFIG_SPL_BUILD + /* + * SPL : configure the remap (L3 NIC-301 GPV) + * so the on-chip RAM at lower memory instead ROM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x19 + str r1, [r0] +#else + /* + * U-Boot : configure the remap (L3 NIC-301 GPV) + * so the SDRAM at lower memory instead on-chip RAM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x2 + str r1, [r0] + + /* Private components security */ + + /* + * U-Boot : configure private timer, global timer and cpu + * component access as non secure for kernel stage (as required + * by kernel) + */ + mrc p15,4,r0,c15,c0,0 + add r1, r0, #0x54 + ldr r2, [r1] + orr r2, r2, #0xff + orr r2, r2, #0xf00 + str r2, [r1] +#endif /* #ifdef CONFIG_SPL_BUILD */ + mov pc, lr diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c new file mode 100644 index 0000000..ef0c750 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <linux/compiler.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset + */ +__noreturn void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor. + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + return 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c new file mode 100644 index 0000000..944238b --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <version.h> +#include <image.h> +#include <malloc.h> +#include <asm/arch/reset_manager.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_RAM; +} + +/* + * Board initialization after bss clearance + */ +void spl_board_init(void) +{ + /* init timer for enabling delay function */ + timer_init(); + + /* de-assert reset for peripherals and bridges based on handoff */ + reset_deassert_peripherals_handoff(); + + /* enable console uart printing */ + preloader_console_init(); +} diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c new file mode 100644 index 0000000..1ceb6e9 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; + +/* + * Timer initialization + */ +int timer_init(void) +{ + writel(TIMER_LOAD_VAL, &timer_base->load_val); + writel(TIMER_LOAD_VAL, &timer_base->curr_val); + setbits_le32(&timer_base->ctrl, 0x3); + return 0; +} + +static u32 read_timer(void) +{ + return readl(&timer_base->curr_val); +} + +/* + * Delay x useconds + */ +void __udelay(unsigned long usec) +{ + unsigned long now, last; + /* + * get the tmo value based on timer clock speed + * tmo = delay required / period of timer clock + */ + long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000; + + last = read_timer(); + while (tmo > 0) { + now = read_timer(); + if (last >= now) + /* normal mode (non roll) */ + tmo -= last - now; + else + /* we have overflow of the count down timer */ + tmo -= TIMER_LOAD_VAL - last + now; + last = now; + } +} + +/* + * Get the timer value + */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * Timer : get the time difference + * Unit of tick is based on the CONFIG_SYS_HZ + */ +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + if (gd->lastinc >= now) { + /* normal mode (non roll) */ + /* move stamp forward with absolute diff ticks */ + gd->tbl += gd->lastinc - now; + } else { + /* we have overflow of the count down timer */ + gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now; + } + gd->lastinc = now; + return gd->tbl; +} + +/* + * Reset the timer + */ +void reset_timer(void) +{ + /* capture current decrementer value time */ + gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + /* start "advancing" time stamp from 0 */ + gd->tbl = 0; +} + diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds new file mode 100644 index 0000000..0236daa --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sram + + . = ALIGN(8); + __malloc_start = .; + . = . + CONFIG_SPL_MALLOC_SIZE; + __malloc_end = .; + + . = . + CONFIG_SPL_STACK_SIZE; + . = ALIGN(8); + __stack_start = .; +} diff --git a/arch/arm/include/asm/arch-socfpga/reset_config.h b/arch/arm/include/asm/arch-socfpga/reset_config.h new file mode 100644 index 0000000..e69de29 diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h new file mode 100644 index 0000000..dd4a0c6 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _RESET_MANAGER_H_ +#define _RESET_MANAGER_H_ + +void reset_deassert_peripherals_handoff(void); + +struct socfpga_reset_manager { + u32 padding1; + u32 ctrl; + u32 padding2; + u32 padding3; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; +}; + +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 + +#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h new file mode 100644 index 0000000..f353eb2 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_BASE_ADDRS_H_ +#define _SOCFPGA_BASE_ADDRS_H_ + +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 + +#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h new file mode 100644 index 0000000..c2014c5 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/spl.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2012 Pavel Machek <pavel(a)denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_SPL_H_ +#define _SOCFPGA_SPL_H_ + +/* Symbols from linker script */ +extern void __malloc_start, __malloc_end, __stack_start; + +#define BOOT_DEVICE_RAM 1 + +#endif diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h new file mode 100644 index 0000000..830c94a --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/timer.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_TIMER_H_ +#define _SOCFPGA_TIMER_H_ + +struct socfpga_timer { + u32 load_val; + u32 curr_val; + u32 ctrl; + u32 eoi; + u32 int_stat; +}; + +#endif diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile new file mode 100644 index 0000000..43bbc37 --- /dev/null +++ b/board/altera/socfpga_cyclone5/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := socfpga_cyclone5.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c new file mode 100644 index 0000000..858ab3c --- /dev/null +++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> + +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +void show_boot_progress(int progress) +{ + debug("Boot reached stage %d\n", progress); +} + +/* + * Print CPU information + */ +int print_cpuinfo(void) +{ + puts("CPU : Altera SOCFPGA Platform\n"); + return 0; +} + +/* + * Print Board information + */ +int checkboard(void) +{ + puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + return 0; +} + +/* + * Initialization function which happen at early stage of c code + */ +int board_early_init_f(void) +{ + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + icache_enable(); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + return 0; +} +#endif + +/* + * DesignWare Ethernet initialization + */ +/* We know all the init functions have been run now */ +int board_eth_init(bd_t *bis) +{ + return 0; +} diff --git a/boards.cfg b/boards.cfg index fdb84ad..1b5c860 100644 --- a/boards.cfg +++ b/boards.cfg @@ -261,6 +261,7 @@ seaboard arm armv7 seaboard nvidia ventana arm armv7 ventana nvidia tegra2 whistler arm armv7 whistler nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 +socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/include/common.h b/include/common.h index 55025c0..e57301f 100644 --- a/include/common.h +++ b/include/common.h @@ -582,7 +582,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); -void reset_cpu (ulong addr); +void reset_cpu (ulong addr) __attribute__((noreturn)); #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd); #ifdef CONFIG_PCI diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h new file mode 100644 index 0000000..bb96274 --- /dev/null +++ b/include/configs/socfpga_cyclone5.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/socfpga_base_addrs.h> + +/* + * High level configuration + */ + +#define CONFIG_ARMV7 +#define CONFIG_L2_OFF +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_USE_IRQ + +#define CONFIG_MISC_INIT_R +#define CONFIG_SINGLE_BOOTLOADER +#define CONFIG_SOCFPGA + +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#define V_NS16550_CLK 1000000 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_TIMER_CLOCK_KHZ 2400 +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Enable early stage initialization at C environment + */ +#define CONFIG_BOARD_EARLY_INIT_F + +/* flat device tree */ +#define CONFIG_OF_LIBFDT +/* skip updating the FDT blob */ +#define CONFIG_FDT_BLOB_SKIP_UPDATE +/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ +#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) + +/* + * Memory allocation (MALLOC) + */ +/* Room required on the stack for the environment data */ +#define CONFIG_ENV_SIZE 1024 +/* Size of DRAM reserved for malloc() use */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +/* Reserving 0x100 space at back of scratch RAM for debug info */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + + +/* + * Command line configuration. + */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +/* FAT file system support */ +#define CONFIG_CMD_FAT + + +/* + * Misc + */ +#define CONFIG_DOS_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif + +/* + * Environment setup + */ + +/* Delay before automatically booting the default image */ +#define CONFIG_BOOTDELAY 3 +/* Enable auto completion of commands using TAB */ +#define CONFIG_AUTO_COMPLETE +/* use "hush" command parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMD_RUN + +#define CONFIG_BOOTCOMMAND "run ramboot" + +/* + * arguments passed to the bootm command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=uImage\0" \ + "fdt_addr=100\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* using environment setting for stdin, stdout, stderr */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* Enable the call to overwrite_console() */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +/* Enable overwrite of previous console environment settings */ +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + + +/* + * Hardware drivers + */ + +/* + * SDRAM Memory Map + */ +/* We have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +/* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* SDRAM memory size */ +#define PHYS_SDRAM_1_SIZE 0x80000000 + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE + +/* + * NS16550 Configuration + */ +#define UART0_BASE SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 UART0_BASE + +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * FLASH + */ +#define CONFIG_SYS_NO_FLASH + +/* + * L4 OSC1 Timer 0 + */ +/* This timer use eosc1 where the clock frequency is fixed + * throughout any condition */ +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS + +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +#define CONFIG_ENV_IS_NOWHERE + +/* + * SPL "Second Program Loader" aka Initial Software + */ + +/* Enable building of SPL globally */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK + +/* TEXT_BASE for linking the SPL binary */ +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 + +/* Stack size for SPL */ +#define CONFIG_SPL_STACK_SIZE (4 * 1024) +#define CONFIG_SPL_MAX_SIZE (64 * 1024) + +/* MALLOC size for SPL */ +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) + +#define CONFIG_SPL_STACK (&__stack_start) +#define CONFIG_SYS_SPL_MALLOC_START (&__malloc_start) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) + +#define CONFIG_SPL_BSS_START_ADDR 0x08000040 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE + +#define CHUNKSZ_CRC32 (1 * 1024) + +#define CONFIG_CRC32_VERIFY + +/* Linker script for SPL */ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" + +/* Support for common/libcommon.o in SPL binary */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT +/* Support for lib/libgeneric.o in SPL binary */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#endif /* __CONFIG_H */ -- 1.7.9.5

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[U-Boot] Pull request: u-boot-video/master
by Anatolij Gustschin 28 Sep '12

28 Sep '12

Hello Tom, The following changes since commit a6f0c4faa4c65a7b7048b12c9d180d7e1aad1721: Merge branch 'master' of git://git.denx.de/u-boot-avr32 (2012-09-04 09:17:27 +0200) are available in the git repository at: git://git.denx.de/u-boot-video.git master Nikita Kiryanov (5): common lcd: simplify lcd_logo common lcd: simplify lcd_display common lcd: simplify core functions common lcd: simplify lcd_display_bitmap common/lcd: add protection from null bmp pointer Timur Tabi (1): video/powerpc: don't touch DIU registers that we don't need board/mcc200/lcd.c | 20 ++++++ common/lcd.c | 147 +++++++++++++++++++++++--------------------- drivers/video/fsl_diu_fb.c | 21 +------ 3 files changed, 99 insertions(+), 89 deletions(-) Please pull. Thanks! Anatolij

3 6

[U-Boot] [PATCH 0/4] arm:samsung: Cleanup code for trats and universal boards
by Piotr Wilczek 28 Sep '12

28 Sep '12

This patch fixes SDRAM configuration and size visibility for trats board. Common code is set for trats and universal boards. Low level initialisation in U-boot is eliminated for universal_c210 board. Piotr Wilczek (4): arm:exynos4:trats: Correct SDRAM configuration for trats arm:exynos4:trats: Fix SDRAM size arm:exynos4:trats&universal_c210: Set common code for trats and universal_c210 boards arm:exynos4:universal_c210: Eliminate low level initialisation board/samsung/exynos4_common/exynos4_common.c | 139 +++++++++ board/samsung/trats/trats.c | 98 +------ board/samsung/universal_c210/Makefile | 1 - board/samsung/universal_c210/lowlevel_init.S | 395 ------------------------- board/samsung/universal_c210/universal.c | 105 +------ include/configs/s5pc210_universal.h | 2 + include/configs/trats.h | 17 +- 7 files changed, 163 insertions(+), 594 deletions(-) create mode 100644 board/samsung/exynos4_common/exynos4_common.c delete mode 100644 board/samsung/universal_c210/lowlevel_init.S -- 1.7.5.4

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[U-Boot] [PATCH 0/2] Move Tegra20 files to common subdirs, prep for T30
by Tom Warren 28 Sep '12

28 Sep '12

This patch series moves Tegra20 code and include files into common subdirs (../cpu/tegra-common, ../cpu/arm720t/tegra-common, and ../cpu/armv7/tegra-common, plus ../include/asm/arch-tegra). This is needed to prepare for Tegra30 support - T30 HW is (mostly) a super- set of T20 HW. MAKEALL -s tegra20 is OK, as is checkpatch.pl. Tom Warren (2): Tegra20: Move some code files to common directories for upcoming Tegra30 patches. Tegra20: Move some include files to arch-tegra for sharing with Tegra30 Makefile | 2 + .../cpu/arm720t/{tegra20 => tegra-common}/Makefile | 3 +- .../cpu/arm720t/{tegra20 => tegra-common}/board.h | 0 .../cpu/arm720t/{tegra20 => tegra-common}/cpu.h | 0 .../cpu/arm720t/{tegra20 => tegra-common}/spl.c | 12 +- arch/arm/cpu/arm720t/tegra20/Makefile | 1 - arch/arm/cpu/arm720t/tegra20/cpu.c | 12 +- .../cpu/armv7/{tegra20 => tegra-common}/Makefile | 3 +- .../armv7/{tegra20 => tegra-common}/cmd_enterrcm.c | 4 +- arch/arm/cpu/armv7/tegra20/Makefile | 1 - arch/arm/cpu/armv7/tegra20/usb.c | 8 +- .../cpu/{arm720t/tegra20 => tegra-common}/Makefile | 10 +- .../{tegra20-common/ap20.c => tegra-common/ap.c} | 12 +- .../cpu/{tegra20-common => tegra-common}/board.c | 8 +- .../lowlevel_init.S | 0 .../{tegra20-common => tegra-common}/sys_info.c | 0 .../cpu/{tegra20-common => tegra-common}/timer.c | 4 +- arch/arm/cpu/tegra20-common/Makefile | 3 +- arch/arm/cpu/tegra20-common/clock.c | 8 +- arch/arm/cpu/tegra20-common/emc.c | 4 +- arch/arm/cpu/tegra20-common/pinmux.c | 4 +- arch/arm/cpu/tegra20-common/pmu.c | 8 +- arch/arm/cpu/tegra20-common/warmboot.c | 18 +- arch/arm/cpu/tegra20-common/warmboot_avp.c | 12 +- .../asm/{arch-tegra20/ap20.h => arch-tegra/ap.h} | 0 .../asm/{arch-tegra20 => arch-tegra}/board.h | 0 .../asm/{arch-tegra20 => arch-tegra}/clk_rst.h | 0 .../asm/{arch-tegra20 => arch-tegra}/clock.h | 160 +-------- .../asm/{arch-tegra20 => arch-tegra}/fuse.h | 0 .../asm/{arch-tegra20/mmc.h => arch-tegra/gpio.h} | 21 +- .../include/asm/{arch-tegra20 => arch-tegra}/mmc.h | 0 .../include/asm/{arch-tegra20 => arch-tegra}/pmc.h | 0 .../include/asm/{arch-tegra20 => arch-tegra}/scu.h | 0 .../asm/{arch-tegra20 => arch-tegra}/sys_proto.h | 0 .../{arch-tegra20/tegra20.h => arch-tegra/tegra.h} | 14 +- .../asm/{arch-tegra20 => arch-tegra}/tegra_i2c.h | 4 +- .../asm/{arch-tegra20 => arch-tegra}/tegra_mmc.h | 0 .../asm/{arch-tegra20 => arch-tegra}/tegra_spi.h | 0 .../asm/{arch-tegra20 => arch-tegra}/timer.h | 0 .../asm/{arch-tegra20 => arch-tegra}/uart.h | 0 .../asm/{arch-tegra20 => arch-tegra}/warmboot.h | 0 arch/arm/include/asm/arch-tegra20/clock-tables.h | 183 +++++++++ arch/arm/include/asm/arch-tegra20/clock.h | 388 +------------------- arch/arm/include/asm/arch-tegra20/gpio.h | 22 +- .../asm/arch-tegra20/{sys_proto.h => tegra.h} | 17 +- board/avionic-design/common/tamonten.c | 13 +- board/compal/paz00/paz00.c | 4 +- board/compulab/trimslice/trimslice.c | 6 +- board/nvidia/common/board.c | 17 +- board/nvidia/common/emc.c | 8 +- board/nvidia/common/uart-spi-switch.c | 4 +- board/nvidia/harmony/harmony.c | 4 +- board/nvidia/seaboard/seaboard.c | 4 +- board/nvidia/whistler/whistler.c | 6 +- drivers/gpio/tegra_gpio.c | 2 +- drivers/i2c/tegra_i2c.c | 4 +- drivers/input/tegra-kbc.c | 2 +- drivers/mmc/tegra_mmc.c | 6 +- drivers/mtd/nand/tegra_nand.c | 5 +- drivers/spi/tegra_spi.c | 7 +- include/configs/tegra20-common.h | 2 +- spl/Makefile | 2 + 62 files changed, 343 insertions(+), 699 deletions(-) copy arch/arm/cpu/arm720t/{tegra20 => tegra-common}/Makefile (97%) rename arch/arm/cpu/arm720t/{tegra20 => tegra-common}/board.h (100%) rename arch/arm/cpu/arm720t/{tegra20 => tegra-common}/cpu.h (100%) rename arch/arm/cpu/arm720t/{tegra20 => tegra-common}/spl.c (94%) copy arch/arm/cpu/armv7/{tegra20 => tegra-common}/Makefile (95%) rename arch/arm/cpu/armv7/{tegra20 => tegra-common}/cmd_enterrcm.c (96%) copy arch/arm/cpu/{arm720t/tegra20 => tegra-common}/Makefile (86%) rename arch/arm/cpu/{tegra20-common/ap20.c => tegra-common/ap.c} (95%) rename arch/arm/cpu/{tegra20-common => tegra-common}/board.c (95%) rename arch/arm/cpu/{tegra20-common => tegra-common}/lowlevel_init.S (100%) rename arch/arm/cpu/{tegra20-common => tegra-common}/sys_info.c (100%) rename arch/arm/cpu/{tegra20-common => tegra-common}/timer.c (97%) rename arch/arm/include/asm/{arch-tegra20/ap20.h => arch-tegra/ap.h} (100%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/board.h (100%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/clk_rst.h (100%) copy arch/arm/include/asm/{arch-tegra20 => arch-tegra}/clock.h (72%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/fuse.h (100%) copy arch/arm/include/asm/{arch-tegra20/mmc.h => arch-tegra/gpio.h} (65%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/mmc.h (100%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/pmc.h (100%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/scu.h (100%) copy arch/arm/include/asm/{arch-tegra20 => arch-tegra}/sys_proto.h (100%) rename arch/arm/include/asm/{arch-tegra20/tegra20.h => arch-tegra/tegra.h} (90%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/tegra_i2c.h (98%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/tegra_mmc.h (100%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/tegra_spi.h (100%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/timer.h (100%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/uart.h (100%) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/warmboot.h (100%) create mode 100644 arch/arm/include/asm/arch-tegra20/clock-tables.h rename arch/arm/include/asm/arch-tegra20/{sys_proto.h => tegra.h} (76%)

4 11

Re: [U-Boot] Problems with a P2020 board
by Joakim Tjernlund 28 Sep '12

28 Sep '12

Joakim Tjernlund/Transmode wrote on 2012/08/30 15:12:08: > > > > > Hi. > > > > We have a new board which we are suing with U-boot. The CPU is a P2020. > > I am having a few minor problems, and I was hoping to get some help. > > > > - Boot Count. We are keen to use the boot counter feature, but I > > am struggling to find a suitable register in the P2020. The file > > arch/powerpc/lib/bootcount.c list a few locations that work with > > other PowerPC chips, but I can't find any of those registers in the > > P2020 documentation. > > Me too on finding such a register Did you find a register? > > > > > - SPI Flash seems very slow. The SPI flash accesses all seem to be very > > slow. I can increase the SPI clock (to 40 MHz) and this helps, but the > > real problem is the code in drivers/spi/fsl_espi.c. Here there is an 80us > > delay after each 32-bit value is written to the TX FIFO. I don't understand > > why this delay is there? If I reduce it to 2 usec everything still works, and > > SPI Flash accesses are much faster. I can easily produce a patch to > > remove or reduce this delay, but I'd rather know why it was there in the > > first place? > > > > - Timer Interrupts seem to stop. Once U-boot has started the timer > > interrupts seem to stop. I have added a test command that prints out > > the timestamp variable (from arch/powerpc/lib/interrupts.c). I can > > see that when we enter the interactive loop this variable stops > > incrementing. I can add boot scripts that output this value, and it > > is incrementing until the console becomes interactive. Has anyone > > else seen a problem like this? I wonder if you found out the cause? We have recently seen that running LocalBus with 150MHz sometimes makes out board instable(complete freeze) So far we have no clue as it is hard to reproduce. 37,5 MHz works fine tough. > I have but only when running from our BDI2000/BDI3000 emulator. We figured > it was something with the emulator settings but I was never convinced. > If you find out why, please let me know. > Oh, we have a P2010 though. Jocke

3 3

[U-Boot] [PATCH 0/2] arm/km: configuration of the mv88e6352 switch on kmnusa
by Valentin Longchamp 28 Sep '12

28 Sep '12

This series adds supoort for the configuration of the mv88e6352 external switch on kmnusa. It has a clear dependancy to the minimal mv88e6352 net/phy driver: http://patchwork.ozlabs.org/patch/177953/ Valentin Longchamp (2): arm/km: add mv88e6352 configuration for kmnusa km_kirkwood: enable MV88E6352_SWITCH support for kmnusa board/keymile/km_arm/km_arm.c | 63 +++++++++++++++++++++++++++++++++++++++++ include/configs/km_kirkwood.h | 2 + 2 files changed, 65 insertions(+), 0 deletions(-)

2 12

[U-Boot] [PATCH] edminiv2: increase malloc len to 256K
by Albert ARIBAUD 28 Sep '12

28 Sep '12

Malloc len of 128K caused a warning from ehci_hcd asking for more. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- Note: this has been tested on target -- actually, target is now flashed with the merge of u-boot/arm and u-boot master branches plus this patch. include/configs/edminiv2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index f2cfaf8..adb505e 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -222,7 +222,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ /* * Other required minimal configurations -- 1.7.9.5

2 2

[U-Boot] [RFC PATCH 0/5] Add environment call-back capability
by Joe Hershberger 28 Sep '12

28 Sep '12

When a variable with a registered callback is inserted, deleted, or overwritten the callback is called and gives the system an opportunity to do something in response to the change. It also has the opportunuty to reject the change by returning non-zero. Before I go much further, I want to get a little feedback if this is a good implementation. It certainly cleans up cmd_nvedit.c significantly! Joe Hershberger (5): env: Add support for callbacks to environment vars env: Add a loadaddr env handler env: Add a bootfile env handler env: Add a baudrate env handler env: Add a console env handler arch/arm/cpu/u-boot.lds | 7 +++ common/Makefile | 4 +- common/cmd_load.c | 24 +++++++- common/cmd_nvedit.c | 87 -------------------------- common/console.c | 46 ++++++++++++++ common/env_attr.c | 159 ++++++++++++++++++++++++++++++++++++++++++++++++ common/env_callback.c | 114 ++++++++++++++++++++++++++++++++++ common/serial.c | 58 ++++++++++++++++++ include/env_attr.h | 35 +++++++++++ include/env_callback.h | 64 +++++++++++++++++++ include/environment.h | 2 + include/search.h | 5 ++ lib/hashtable.c | 65 +++++++++++++++++++- net/net.c | 16 +++++ 14 files changed, 595 insertions(+), 91 deletions(-) create mode 100644 common/env_attr.c create mode 100644 common/env_callback.c create mode 100644 include/env_attr.h create mode 100644 include/env_callback.h -- 1.7.11.5

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[U-Boot] New patch tracking tool - where to now?
by Graeme Russ 28 Sep '12

28 Sep '12

Hi All, A while ago I wrote this: http://www.denx.de/wiki/U-Boot/ToolsPatchTracking Where to now (brown cow)? Regards, Graeme

1 0