September 2012 - U-Boot

[U-Boot] [PATCH] Fix checkpatch warnings about externs in *.c
by Pavel Herrmann 29 Sep '12

29 Sep '12

Move all extern declarations of sata_dev_desc into a single header file. Signed-off-by: Pavel Herrmann <morpheus.ibis(a)gmail.com> --- drivers/block/ata_piix.c | 4 +--- drivers/block/dwc_ahsata.c | 1 + drivers/block/dwc_ahsata.h | 2 -- drivers/block/fsl_sata.c | 3 +-- drivers/block/pata_bfin.c | 1 + drivers/block/pata_bfin.h | 2 -- drivers/block/sata_dwc.c | 3 +-- drivers/block/sata_extern.h | 30 ++++++++++++++++++++++++++++++ drivers/block/sata_sil.c | 1 + drivers/block/sata_sil.h | 2 -- drivers/block/sata_sil3114.c | 2 +- 11 files changed, 37 insertions(+), 14 deletions(-) create mode 100644 drivers/block/sata_extern.h diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c index c81d11a..de8d563 100644 --- a/drivers/block/ata_piix.c +++ b/drivers/block/ata_piix.c @@ -34,9 +34,7 @@ #include <part.h> #include <ide.h> #include <ata.h> - -extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; -extern int sata_curr_device; +#include "sata_extern.h" #define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */ diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c index 2703d3d..4b32466 100644 --- a/drivers/block/dwc_ahsata.c +++ b/drivers/block/dwc_ahsata.c @@ -33,6 +33,7 @@ #include <linux/bitops.h> #include <asm/arch/clock.h> #include "dwc_ahsata.h" +#include "sata_extern.h" struct sata_port_regs { u32 clb; diff --git a/drivers/block/dwc_ahsata.h b/drivers/block/dwc_ahsata.h index 84860ea..4dac5dc 100644 --- a/drivers/block/dwc_ahsata.h +++ b/drivers/block/dwc_ahsata.h @@ -330,6 +330,4 @@ #define READ_CMD 0 #define WRITE_CMD 1 -extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; - #endif /* __FSL_SATA_H__ */ diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 3026ade..9691f2e 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -27,8 +27,7 @@ #include <libata.h> #include <fis.h> #include "fsl_sata.h" - -extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; +#include "sata_extern.h" #ifndef CONFIG_SYS_SATA1_FLAGS #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c index cce21fb..6aacde0 100644 --- a/drivers/block/pata_bfin.c +++ b/drivers/block/pata_bfin.c @@ -19,6 +19,7 @@ #include <ata.h> #include <libata.h> #include "pata_bfin.h" +#include "sata_extern.h" static struct ata_port port[CONFIG_SYS_SATA_MAX_DEVICE]; diff --git a/drivers/block/pata_bfin.h b/drivers/block/pata_bfin.h index 2b3425b..2093cf0 100644 --- a/drivers/block/pata_bfin.h +++ b/drivers/block/pata_bfin.h @@ -41,8 +41,6 @@ struct ata_port { unsigned char dev_mask; }; -extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; - #define DRV_NAME "pata-bfin" #define DRV_VERSION "0.9" #define __iomem diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c index 75101b5..cc41316 100644 --- a/drivers/block/sata_dwc.c +++ b/drivers/block/sata_dwc.c @@ -38,6 +38,7 @@ #include <linux/ctype.h> #include "sata_dwc.h" +#include "sata_extern.h" #define DMA_NUM_CHANS 1 #define DMA_NUM_CHAN_REGS 8 @@ -268,8 +269,6 @@ static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class, unsigned int flags, u16 *id); static int check_sata_dev_state(void); -extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; - static const struct ata_port_info sata_dwc_port_info[] = { { .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | diff --git a/drivers/block/sata_extern.h b/drivers/block/sata_extern.h new file mode 100644 index 0000000..3bf9df9 --- /dev/null +++ b/drivers/block/sata_extern.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2012 + * Pavel Herrmann <morpheus.ibis(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLOCK_SATA_EXTERN_H_ +#define _BLOCK_SATA_EXTERN_H_ + +extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; +extern int sata_curr_device; + +#endif diff --git a/drivers/block/sata_sil.c b/drivers/block/sata_sil.c index fb7cd2a..ee9194c 100644 --- a/drivers/block/sata_sil.c +++ b/drivers/block/sata_sil.c @@ -27,6 +27,7 @@ #include <fis.h> #include <libata.h> #include "sata_sil.h" +#include "sata_extern.h" /* Convert sectorsize to wordsize */ #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2) diff --git a/drivers/block/sata_sil.h b/drivers/block/sata_sil.h index 2dfd4a5..9f3a37f 100644 --- a/drivers/block/sata_sil.h +++ b/drivers/block/sata_sil.h @@ -24,8 +24,6 @@ #define READ_CMD 0 #define WRITE_CMD 1 -extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; - /* * SATA device driver struct for each dev */ diff --git a/drivers/block/sata_sil3114.c b/drivers/block/sata_sil3114.c index 34fe038..da55385 100644 --- a/drivers/block/sata_sil3114.c +++ b/drivers/block/sata_sil3114.c @@ -30,6 +30,7 @@ #include <ide.h> #include <libata.h> #include "sata_sil3114.h" +#include "sata_extern.h" /* Convert sectorsize to wordsize */ #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2) @@ -48,7 +49,6 @@ static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus); static void msleep (int count); static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */ -extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE]; -- 1.7.12

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[U-Boot] [PATCH 0/6] add zip command support for uboot
by adrian.wenl＠gmail.com 29 Sep '12

29 Sep '12

From: Lei Wen <leiwen(a)marvell.com> This patch set add zip command support for uboot. The first two patches import deflate and trees functions from zlib 1.2.5 without any change. While the third patch did the necessary change to make the import file could be built passed in uboot environment. The fourth patch make us could zip the memory from 0 in the address space. The latter fifth and sixth patch does the adding gzip lib function exporting and zip command support. Patch set test with zip&unzip and compared with original memory content. Lei Wen (6): lib: zlib: import deflate source file from 1.2.5 lib: zlib: import trees file from 1.2.5 lib: zlib: include deflate into zlib build lib: zlib: remove the limitation for cannot using 0 as start lib: add gzip lib function callback common: add zip command support common/Makefile | 1 + common/cmd_zip.c | 60 ++ include/common.h | 7 + include/u-boot/zlib.h | 40 +- lib/Makefile | 1 + lib/gzip.c | 143 ++++ lib/zlib/deflate.c | 1831 +++++++++++++++++++++++++++++++++++++++++++++++++ lib/zlib/deflate.h | 342 +++++++++ lib/zlib/trees.c | 1244 +++++++++++++++++++++++++++++++++ lib/zlib/trees.h | 128 ++++ lib/zlib/zlib.c | 8 + lib/zlib/zutil.h | 4 + 12 files changed, 3804 insertions(+), 5 deletions(-) create mode 100644 common/cmd_zip.c create mode 100644 lib/gzip.c create mode 100644 lib/zlib/deflate.c create mode 100644 lib/zlib/deflate.h create mode 100644 lib/zlib/trees.c create mode 100644 lib/zlib/trees.h -- 1.7.5.4

8 40

[U-Boot] [PATCH] tegra: nand: make ONFI detection work
by Lucas Stach 29 Sep '12

29 Sep '12

Add the missing bits to the Tegra NAND driver to make ONFI detection work properly. Also add it to the Tegra default config, as it seems to be a reasonable thing to have it available on all boards that use any kind of NAND. Signed-off-by: Lucas Stach <dev(a)lynxeye.de> --- drivers/mtd/nand/tegra_nand.c | 36 ++++++++++++++++++++++++++++++++++++ include/configs/tegra20-common.h | 1 + 2 Dateien geändert, 37 Zeilen hinzugefügt(+) diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index 2c1b533..0d7ca5d 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -219,6 +219,34 @@ static uint8_t read_byte(struct mtd_info *mtd) } /** + * Read len bytes from the chip into a buffer + * + * @param mtd MTD device structure + * @param buf buffer to store data to + * @param len number of bytes to read + * + * Read function for 8bit bus-width + */ +static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i, s; + unsigned int reg; + struct nand_chip *chip = mtd->priv; + struct nand_drv *info = (struct nand_drv *)chip->priv; + + for (i = 0; i < len; i += 4) { + s = (len - i) > 4 ? 4 : len - i; + writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 | + ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO, + &info->reg->command); + if (!nand_waitfor_cmd_completion(info->reg)) + printf("Command timeout during read_buf\n"); + reg = readl(&info->reg->resp); + memcpy(buf + i, &reg, s); + } +} + +/** * Check NAND status to see if it is ready or not * * @param mtd MTD device structure @@ -317,6 +345,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, switch (command) { case NAND_CMD_READID: writel(NAND_CMD_READID, &info->reg->cmd_reg1); + writel(column & 0xFF, &info->reg->addr_reg1); writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO | CMD_RX | ((4 - 1) << CMD_TRANS_SIZE_SHIFT) @@ -324,6 +353,12 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, &info->reg->command); info->pio_byte_index = 0; break; + case NAND_CMD_PARAM: + writel(NAND_CMD_PARAM, &info->reg->cmd_reg1); + writel(column & 0xFF, &info->reg->addr_reg1); + writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0, + &info->reg->command); + break; case NAND_CMD_READ0: writel(NAND_CMD_READ0, &info->reg->cmd_reg1); writel(NAND_CMD_READSTART, &info->reg->cmd_reg2); @@ -976,6 +1011,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum) nand->options = LP_OPTIONS; nand->cmdfunc = nand_command; nand->read_byte = read_byte; + nand->read_buf = read_buf; nand->ecc.read_page = nand_read_page_hwecc; nand->ecc.write_page = nand_write_page_hwecc; nand->ecc.read_page_raw = nand_read_page_raw; diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 744dc59..9e60020 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -204,5 +204,6 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" #define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION #endif /* __TEGRA20_COMMON_H */ -- 1.7.11.4

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[U-Boot] [GIT PULL] Pull request: u-boot-imx
by Stefano Babic 29 Sep '12

29 Sep '12

Hi Albert, some fixes for the release. Please pull from u-boot-imx, thanks. The following changes since commit 1d9b033269263a69f7402f508c17b242fc7fea43: mx35pdk: README: Remove NAND references (2012-09-17 13:17:17 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to 7577a4b3c27af9ad21a4aedf732754ae96225448: mx28evk: Add missing 'setexpr' command (2012-09-24 11:00:08 +0200) ---------------------------------------------------------------- Benoît Thébaudeau (2): mx51evk: Add CONFIG_REVISION_TAG KARO TX25: Fix NAND Flash R/W cycle times Eric Nelson (2): i.MX: mxc_ipuv3_fb: add ipuv3_fb_shutdown() routine to stop IPU frame buffer i.MX: shut down video before launch of O/S Fabio Estevam (1): mx28evk: Remove fecmxc_mii_postcall() Otavio Salvador (1): mx28evk: Add missing 'setexpr' command arch/arm/imx-common/cpu.c | 9 +++++++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 2 ++ board/freescale/mx28evk/mx28evk.c | 25 ------------------------- board/freescale/mx51evk/mx51evk.c | 8 ++++++++ board/karo/tx25/lowlevel_init.S | 8 ++++++++ drivers/video/mxc_ipuv3_fb.c | 20 ++++++++++++++++++++ include/configs/mx28evk.h | 1 + include/configs/mx51evk.h | 1 + include/ipu_pixfmt.h | 1 + 9 files changed, 50 insertions(+), 25 deletions(-) -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

2 1

[U-Boot] [PATCH] powerpc/srio: Workaround for srio erratrm a004034
by Liu Gang 29 Sep '12

29 Sep '12

Erratum: A-004034 Affects: SRIO Description: During port initialization, the SRIO port performs lane synchronization (detecting valid symbols on a lane) and lane alignment (coordinating multiple lanes to receive valid data across lanes). Internal errors in lane synchronization and lane alignment may cause failure to achieve link initialization at the configured port width. An SRIO port configured as a 4x port may see one of these scenarios: 1. One or more lanes fails to achieve lane synchronization. Depending on which lanes fail, this may result in downtraining from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane). 2. The link may fail to achieve lane alignment as a 4x, even though all 4 lanes achieve lane synchronization, and downtrain to a 1x. An SRIO port configured as a 1x port may fail to complete port initialization (PnESCSR[PU] never deasserts) because of scenario 1. Impact: SRIO port may downtrain to 1x, or may fail to complete link initialization. Once a port completes link initialization successfully, it will operate normally. Signed-off-by: Liu Gang <Gang.Liu(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 + arch/powerpc/cpu/mpc8xxx/srio.c | 191 +++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 4 + 3 files changed, 198 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index e8989bd..98038a3 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -127,6 +127,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 puts("Work-around for Erratum A004510 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 + puts("Work-around for Erratum SRIO-A004034 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 0cb65b3..e7ff59a 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -22,6 +22,7 @@ #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> +#include <asm/errno.h> #define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_IB_ATMU_AR 0x80f55000 @@ -52,6 +53,185 @@ #error "No defines for DEVDISR_SRIO" #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 +/* + * Erratum A-004034 + * Affects: SRIO + * Description: During port initialization, the SRIO port performs + * lane synchronization (detecting valid symbols on a lane) and + * lane alignment (coordinating multiple lanes to receive valid data + * across lanes). Internal errors in lane synchronization and lane + * alignment may cause failure to achieve link initialization at + * the configured port width. + * An SRIO port configured as a 4x port may see one of these scenarios: + * 1. One or more lanes fails to achieve lane synchronization. Depending + * on which lanes fail, this may result in downtraining from 4x to 1x + * on lane 0, 4x to 1x on lane R (redundant lane). + * 2. The link may fail to achieve lane alignment as a 4x, even though + * all 4 lanes achieve lane synchronization, and downtrain to a 1x. + * An SRIO port configured as a 1x port may fail to complete port + * initialization (PnESCSR[PU] never deasserts) because of scenario 1. + * Impact: SRIO port may downtrain to 1x, or may fail to complete + * link initialization. Once a port completes link initialization + * successfully, it will operate normally. + */ +static int srio_erratum_a004034(u8 port) +{ + serdes_corenet_t *srds_regs; + u32 conf_lane; + u32 init_lane; + int idx, first, last; + u32 i; + unsigned long long end_tick; + struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + + srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); + conf_lane = (in_be32((void *)&srds_regs->srdspccr0) + >> (12 - port * 4)) & 0x3; + init_lane = (in_be32((void *)&srio_regs->lp_serial + .port[port].pccsr) >> 27) & 0x7; + + /* + * Start a counter set to ~2 ms after the SERDES reset is + * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n + * corresponding to the SERDES bank/PLL for the SRIO port). + */ + if (in_be32((void *)&srds_regs->bank[0].rstctl) + & SRDS_RSTCTL_RSTDONE) { + /* + * Poll the port uninitialized status (SRIO PnESCSR[PO]) until + * PO=1 or the counter expires. If the counter expires, the + * port has failed initialization: go to recover steps. If PO=1 + * and the desired port width is 1x, go to normal steps. If + * PO = 1 and the desired port width is 4x, go to recover steps. + */ + end_tick = usec2ticks(2000) + get_ticks(); + do { + if (in_be32((void *)&srio_regs->lp_serial + .port[port].pescsr) & 0x2) { + if (conf_lane == 0x1) + goto host_ok; + else { + if (init_lane == 0x2) + goto host_ok; + else + break; + } + } + } while (end_tick > get_ticks()); + + /* recover at most 3 times */ + for (i = 0; i < 3; i++) { + /* Set SRIO PnCCSR[PD]=1 */ + setbits_be32((void *)&srio_regs->lp_serial + .port[port].pccsr, + 0x800000); + /* + * Set SRIO PnPCR[OBDEN] on the host to + * enable the discarding of any pending packets. + */ + setbits_be32((void *)&srio_regs->impl.port[port].pcr, + 0x04); + /* Wait 50 us */ + udelay(50); + /* Run sync command */ + isync(); + + if (port) + first = serdes_get_first_lane(SRIO2); + else + first = serdes_get_first_lane(SRIO1); + if (unlikely(first < 0)) + return -ENODEV; + if (conf_lane == 0x1) + last = first; + else + last = first + 3; + /* + * Set SERDES BnGCRm0[RRST]=0 for each SRIO + * bank n and lane m. + */ + for (idx = first; idx <= last; idx++) + clrbits_be32(&srds_regs->lane[idx].gcr0, + SRDS_GCR0_RRST); + /* + * Read SERDES BnGCRm0 for each SRIO + * bank n and lane m + */ + for (idx = first; idx <= last; idx++) + in_be32(&srds_regs->lane[idx].gcr0); + /* Run sync command */ + isync(); + /* Wait >= 100 ns */ + udelay(1); + /* + * Set SERDES BnGCRm0[RRST]=1 for each SRIO + * bank n and lane m. + */ + for (idx = first; idx <= last; idx++) + setbits_be32(&srds_regs->lane[idx].gcr0, + SRDS_GCR0_RRST); + /* + * Read SERDES BnGCRm0 for each SRIO + * bank n and lane m + */ + for (idx = first; idx <= last; idx++) + in_be32(&srds_regs->lane[idx].gcr0); + /* Run sync command */ + isync(); + /* Wait >= 300 ns */ + udelay(1); + + /* Write 1 to clear all bits in SRIO PnSLCSR */ + out_be32((void *)&srio_regs->impl.port[port].slcsr, + 0xffffffff); + /* Clear SRIO PnPCR[OBDEN] on the host */ + clrbits_be32((void *)&srio_regs->impl.port[port].pcr, + 0x04); + /* Set SRIO PnCCSR[PD]=0 */ + clrbits_be32((void *)&srio_regs->lp_serial + .port[port].pccsr, + 0x800000); + /* Wait >= 24 ms */ + udelay(24000); + /* Poll the state of the port again */ + init_lane = + (in_be32((void *)&srio_regs->lp_serial + .port[port].pccsr) >> 27) & 0x7; + if (in_be32((void *)&srio_regs->lp_serial + .port[port].pescsr) & 0x2) { + if (conf_lane == 0x1) + goto host_ok; + else { + if (init_lane == 0x2) + goto host_ok; + } + } + if (i == 2) + return -ENODEV; + } + } else + return -ENODEV; + +host_ok: + /* Poll PnESCSR[OES] on the host until it is clear */ + end_tick = usec2ticks(1000000) + get_ticks(); + do { + if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr) + & 0x10000)) { + out_be32(((void *)&srio_regs->lp_serial + .port[port].pescsr), 0xffffffff); + out_be32(((void *)&srio_regs->phys_err + .port[port].edcsr), 0); + out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0); + return 0; + } + } while (end_tick > get_ticks()); + + return -ENODEV; +} +#endif + void srio_init(void) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; @@ -62,6 +242,11 @@ void srio_init(void) law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), LAW_TRGT_IF_RIO_1); srio1_used = 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 + if (srio_erratum_a004034(0) < 0) + printf("SRIO1: enabled but port error\n"); + else +#endif printf("SRIO1: enabled\n"); } else { printf("SRIO1: disabled\n"); @@ -73,7 +258,13 @@ void srio_init(void) law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), LAW_TRGT_IF_RIO_2); srio2_used = 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 + if (srio_erratum_a004034(1) < 0) + printf("SRIO2: enabled but port error\n"); + else +#endif printf("SRIO2: enabled\n"); + } else { printf("SRIO2: disabled\n"); } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index aa27741..525eec3 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -338,6 +338,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -367,6 +368,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ #define CONFIG_MAX_CPUS 8 @@ -406,6 +408,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 +#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ #define CONFIG_MAX_CPUS 2 @@ -432,6 +435,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A004510 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 +#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 #elif defined(CONFIG_BSC9131) #define CONFIG_MAX_CPUS 1 -- 1.7.1

1 0

[U-Boot] [PULL} please pull u-boot-atmel/master into u-boot-arm/master
by Andreas Bießmann 29 Sep '12

29 Sep '12

Dear Albert Aribaud, as mentioned before there are some fixes left for this upcoming release, here they are. The following changes since commit 057df193b40d31799d41d43bc832a972f658bfe4: Merge remote-tracking branch 'u-boot-ti/master' into m (2012-09-05 20:20:04 +0200) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to dc3e30bab7c5ef87bd24ebcbb7cdfc3fb2b44555: Atmel: sam9g10/9m10/9x5: Add support to boot DT kernel (2012-09-17 19:02:44 +0200) ---------------------------------------------------------------- Bo Shen (3): spi: add atmel at25df321 serial flash support spiflash: at25: using common spi flash operation Atmel: sam9g10/9m10/9x5: Add support to boot DT kernel Wu, Josh (2): at91sam9x5: set default EBI I/O drive configuration. atmel_nand: fix the U-Boot output information about nand flash with PMECC enable. board/atmel/at91sam9x5ek/at91sam9x5ek.c | 4 ++++ drivers/mtd/nand/atmel_nand.c | 5 +++-- drivers/mtd/spi/atmel.c | 17 ++++++++++++++++- include/configs/at91sam9261ek.h | 2 ++ include/configs/at91sam9m10g45ek.h | 2 ++ include/configs/at91sam9x5ek.h | 2 ++ 6 files changed, 29 insertions(+), 3 deletions(-) Best regards Andreas Bießmann

2 5

[U-Boot] [RFC] [PATCH 0/3] Linker-generated arrays
by Marek Vasut 29 Sep '12

29 Sep '12

5 44

[U-Boot] question
by pflora＠libero.it 28 Sep '12

28 Sep '12

Hi to everybody, I am new and just put the hands inside u-boot. I am working on ARM cortex M3 on board lpc178x from emcraft using u-boot 2010. I enabled the fat and cmd_fat modules and have the following problems: - compile error on section .bss too large due 2 arrays defined in fat.c with MAX_CLUSTSIZE (65535) elements. I reduced the size up to 7000 elements and only 1 array, disabling VFAT support. In this way I compile and get the u-boot working. - the system becomes unstable using fat commands like fatls and fatload. - tried to download u-2012 and configure my board in the new release, but no hope. I cannot configure the file boards.cfg and I don't know where to put my board directories in the u-2012 tree. What can I do ? Thanks for your support.

1 0

[U-Boot] [PATCH 1/4 v3] serial: Add Zynq serial driver
by Michal Simek 28 Sep '12

28 Sep '12

The driver is used on Xilinx Zynq platform. Signed-off-by: Michal Simek <monstr(a)monstr.eu> CC: Joe Hershberger <joe.hershberger(a)gmail.com> CC: Marek Vasut <marex(a)denx.de> --- v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART Rename driver name Remove driver description v3: SERIAL_MULTI support Rename xdfuart to uart_zynq --- common/serial.c | 8 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_zynq.c | 246 ++++++++++++++++++++++++++++++++++++++++++ include/serial.h | 5 + 4 files changed, 260 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_zynq.c diff --git a/common/serial.c b/common/serial.c index 75cc1bb..4f2bc7f 100644 --- a/common/serial.c +++ b/common/serial.c @@ -122,6 +122,14 @@ void serial_initialize(void) serial_register(&uartlite_serial3_device); # endif /* XILINX_UARTLITE_BASEADDR3 */ #endif /* CONFIG_XILINX_UARTLITE */ +#if defined(CONFIG_ZYNQ_SERIAL) +# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 + serial_register(&uart_zynq_serial0_device); +# endif +# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 + serial_register(&uart_zynq_serial1_device); +# endif +#endif serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 65d0f23..dfc22a4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o +COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c new file mode 100644 index 0000000..30f2445 --- /dev/null +++ b/drivers/serial/serial_zynq.c @@ -0,0 +1,246 @@ +/* + * Copyright (C) 2012 Michal Simek <monstr(a)monstr.eu> + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include <linux/compiler.h> +#include <serial.h> + +#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ + +#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ +#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ +#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ +#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ + +#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ + +/* Some clock/baud constants */ +#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ +#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ + +struct uart_zynq { + u32 control; /* Control Register [8:0] */ + u32 mode; /* Mode Register [10:0] */ + u32 reserved1[4]; + u32 baud_rate_gen; /* Baud Rate Generator [15:0] */ + u32 reserved2[4]; + u32 channel_sts; /* Channel Status [11:0] */ + u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */ + u32 baud_rate_divider; /* Baud Rate Divider [7:0] */ +}; + +static struct uart_zynq *uart_zynq_ports[2] = { +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 + [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0, +#endif +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 + [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1, +#endif +}; + +struct uart_zynq_params { + u32 baudrate; + u32 clock; +}; + +static struct uart_zynq_params uart_zynq_ports_param[2] = { +#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) + [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, + [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, +#endif +#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) + [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, + [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, +#endif +}; + +/* Set up the baud rate in gd struct */ +static void uart_zynq_serial_setbrg(const int port) +{ + /* Calculation results. */ + unsigned int calc_bauderror, bdiv, bgen; + unsigned long calc_baud = 0; + unsigned long baud = uart_zynq_ports_param[port].baudrate; + unsigned long clock = uart_zynq_ports_param[port].clock; + struct uart_zynq *regs = uart_zynq_ports[port]; + + /* master clock + * Baud rate = ------------------ + * bgen * (bdiv + 1) + * + * Find acceptable values for baud generation. + */ + for (bdiv = 4; bdiv < 255; bdiv++) { + bgen = clock / (baud * (bdiv + 1)); + if (bgen < 2 || bgen > 65535) + continue; + + calc_baud = clock / (bgen * (bdiv + 1)); + + /* + * Use first calculated baudrate with + * an acceptable (<3%) error + */ + if (baud > calc_baud) + calc_bauderror = baud - calc_baud; + else + calc_bauderror = calc_baud - baud; + if (((calc_bauderror * 100) / baud) < 3) + break; + } + + writel(bdiv, &regs->baud_rate_divider); + writel(bgen, &regs->baud_rate_gen); +} + +/* Initialize the UART, with...some settings. */ +static int uart_zynq_serial_init(const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + if (!regs) + return -1; + + /* RX/TX enabled & reset */ + writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ + ZYNQ_UART_CR_RXRST, &regs->control); + writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */ + uart_zynq_serial_setbrg(port); + + return 0; +} + +static void uart_zynq_serial_putc(const char c, const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) + WATCHDOG_RESET(); + + if (c == '\n') { + writel('\r', &regs->tx_rx_fifo); + while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) + WATCHDOG_RESET(); + } + writel(c, &regs->tx_rx_fifo); +} + +static void uart_zynq_serial_puts(const char *s, const int port) +{ + while (*s) + uart_zynq_serial_putc(*s++, port); +} + +static int uart_zynq_serial_tstc(const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + return (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; +} + +static int uart_zynq_serial_getc(const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + while (!uart_zynq_serial_tstc(port)) + WATCHDOG_RESET(); + return readl(&regs->tx_rx_fifo); +} + +#if !defined(CONFIG_SERIAL_MULTI) +int serial_init(void) +{ + return uart_zynq_serial_init(0); +} + +void serial_setbrg(void) +{ + uart_zynq_serial_setbrg(0); +} + +void serial_putc(const char c) +{ + uart_zynq_serial_putc(c, 0); +} + +void serial_puts(const char *s) +{ + uart_zynq_serial_puts(s, 0); +} + +int serial_getc(void) +{ + return uart_zynq_serial_getc(0); +} + +int serial_tstc(void) +{ + return uart_zynq_serial_tstc(0); +} +#else +/* Multi serial device functions */ +#define DECLARE_PSSERIAL_FUNCTIONS(port) \ + int uart_zynq##port##_init(void) \ + { return uart_zynq_serial_init(port); } \ + void uart_zynq##port##_setbrg(void) \ + { return uart_zynq_serial_setbrg(port); } \ + int uart_zynq##port##_getc(void) \ + { return uart_zynq_serial_getc(port); } \ + int uart_zynq##port##_tstc(void) \ + { return uart_zynq_serial_tstc(port); } \ + void uart_zynq##port##_putc(const char c) \ + { uart_zynq_serial_putc(c, port); } \ + void uart_zynq##port##_puts(const char *s) \ + { uart_zynq_serial_puts(s, port); } + +/* Serial device descriptor */ +#define INIT_PSSERIAL_STRUCTURE(port, name) {\ + name,\ + uart_zynq##port##_init,\ + NULL,\ + uart_zynq##port##_setbrg,\ + uart_zynq##port##_getc,\ + uart_zynq##port##_tstc,\ + uart_zynq##port##_putc,\ + uart_zynq##port##_puts, } + +DECLARE_PSSERIAL_FUNCTIONS(0); +struct serial_device uart_zynq_serial0_device = + INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); +DECLARE_PSSERIAL_FUNCTIONS(1); +struct serial_device uart_zynq_serial1_device = + INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); + +__weak struct serial_device *default_serial_console(void) +{ + if (uart_zynq_ports[0]) + return &uart_zynq_serial0_device; + if (uart_zynq_ports[1]) + return &uart_zynq_serial1_device; + + return NULL; +} +#endif diff --git a/include/serial.h b/include/serial.h index cbdf8a9..dc8e9b4 100644 --- a/include/serial.h +++ b/include/serial.h @@ -89,6 +89,11 @@ extern struct serial_device bfin_serial2_device; extern struct serial_device bfin_serial3_device; #endif +#if defined(CONFIG_ZYNQ_SERIAL) +extern struct serial_device uart_zynq_serial0_device; +extern struct serial_device uart_zynq_serial1_device; +#endif + extern void serial_register(struct serial_device *); extern void serial_initialize(void); extern void serial_stdio_init(void); -- 1.7.0.4

5 27

[U-Boot] [PATCH 4/4 v5] xilinx: Add new Zynq board
by Michal Simek 28 Sep '12

28 Sep '12

Add support for Xilinx Zynq board. Signed-off-by: Michal Simek <monstr(a)monstr.eu> Acked-by: Marek Vasut <marex(a)denx.de> CC: Joe Hershberger <joe.hershberger(a)gmail.com> --- v2: Forget to also add config file v3: Change name for serial driver Remove lowlevel_init from board folder Remove XPSS part from timer baseaddr Change name for Zynq gem driver Clean coding style Remove mac + ip addresses from config file Remove additional PHYs v4: Move reset_cpu to cpu folder Remove empty board_late_init Enable SERIAL_MULTI Setup SYS_TEXT_BASE Changed eth initialization v5: Add board to MAINTAINERS file --- MAINTAINERS | 4 ++ board/xilinx/zynq/Makefile | 54 +++++++++++++++++++++ board/xilinx/zynq/board.c | 54 +++++++++++++++++++++ boards.cfg | 1 + include/configs/zynq.h | 112 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 225 insertions(+), 0 deletions(-) create mode 100644 board/xilinx/zynq/Makefile create mode 100644 board/xilinx/zynq/board.c create mode 100644 include/configs/zynq.h diff --git a/MAINTAINERS b/MAINTAINERS index aa54fe1..e5a5a43 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -890,6 +890,10 @@ Matt Sealey <matt(a)genesi-usa.com> Bo Shen <voice.shen(a)atmel.com> at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC) +Michal Simek <monstr(a)monstr.eu> + + zynq ARM ARMV7 (Zynq SoC) + Nick Thompson <nick.thompson(a)gefanuc.com> da830evm ARM926EJS (DA830/OMAP-L137) diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile new file mode 100644 index 0000000..ef4faa1 --- /dev/null +++ b/board/xilinx/zynq/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := board.o + +COBJS := $(sort $(COBJS-y)) + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c new file mode 100644 index 0000000..8ed75c3 --- /dev/null +++ b/board/xilinx/zynq/board.c @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2012 Michal Simek <monstr(a)monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + icache_enable(); + + return 0; +} + + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + u32 ret = 0; + +#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0) + ret = zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0); +#endif + + return ret; +} +#endif + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 091c79f..5d82499 100644 --- a/boards.cfg +++ b/boards.cfg @@ -272,6 +272,7 @@ ventana arm armv7:arm720t ventana nvidia whistler arm armv7:arm720t whistler nvidia tegra20 u8500_href arm armv7 u8500 st-ericsson u8500 snowball arm armv7 snowball st-ericsson u8500 +zynq arm armv7 zynq xilinx zynq actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/include/configs/zynq.h b/include/configs/zynq.h new file mode 100644 index 0000000..34ac3ef --- /dev/null +++ b/include/configs/zynq.h @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2012 Michal Simek <monstr(a)monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_ZYNQ_H +#define __CONFIG_ZYNQ_H + +#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +#define CONFIG_ZYNQ + +/* CPU clock */ +#define CONFIG_CPU_FREQ_HZ 800000000 +#define CONFIG_SYS_HZ 1000 + +/* Ram */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_TEXT_BASE 0 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CONFIG_BAUDRATE 115200 + +/* XPSS Serial driver */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_ZYNQ_SERIAL +#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 +#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE +#define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 + +/* SCU timer address is hardcoded */ +#define CONFIG_SCUTIMER_BASEADDR 0xF8F00600 + +/* Ethernet driver */ +#define CONFIG_NET_MULTI +#define CONFIG_ZYNQ_GEM +#define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000 + +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_MAY_FAIL + +/* MII and Phylib */ +#define CONFIG_MII +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_PHYLIB +#define CONFIG_PHY_MARVELL + +/* Environment */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x10000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MALLOC_LEN 0x400000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_SYS_LOAD_ADDR 0 +#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* OF */ +#define CONFIG_FIT +#define CONFIG_OF_LIBFDT + +/* Commands */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII + +#endif /* __CONFIG_ZYNQ_H */ -- 1.7.0.4

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