September 2012 - U-Boot

[U-Boot] FW: Don't get any interrupts once I boot into Linux
by Greg Topmiller 14 Sep '12

14 Sep '12

Thanks Benoit, I also tried changing the uboot V2012.07, file arm/cpu/armv7/timer.c to use the IPG clock rather than the 32Khz but no difference. It looks like the FSL interrupt initialization is in arch/arm/plat-mxc/tzic.c file. I don't see anything obvious. It's not real big. I have a Lauterbach debugger that I have been using to step thru the Linux code. The mxc_timer_interrupt never occurs. Best Regards, Greg -----Original Message----- From: Benoît Thébaudeau [mailto:benoit.thebaudeau@advansee.com] Sent: Friday, September 14, 2012 12:06 PM To: Fabio Estevam Cc: u-boot(a)lists.denx.de; Greg Topmiller; gildas allain Subject: Re: [U-Boot] Don't get any interrupts once I boot into Linux Hi Fabio, Greg, On Friday, September 14, 2012 5:15:17 PM, Fabio Estevam wrote: > On Fri, Sep 14, 2012 at 12:04 PM, Greg Topmiller > <Greg.Topmiller(a)jdsu.com> wrote: > > I downloaded the V2012.07 version of u-boot from the git.denx.de > > repository and built it for our target. U-boot boots up properly > > and I can use the commands but now when I boot into Linux I don't > > seem to be getting interrupts. The Linux kernel hangs in the > > calculate_delay function waiting for ticks != jiffies. I do not get > > the interrupt for the timer. I have verified that our previous > > u-boot that is based on the 2009.12 version with Freescale patches > > does work. The timer interrupt occurs and jiffies is incremented > > allowing the loop to exit. Any help would be appreciated. > > > > Which board are you using? Same here with a custom i.MX51-based board and a FSL-based Linux. It works fine with the FSL-based U-Boot (2009.12). Some debugging has shown that: - The Linux timer is based on GPT. - The GPT counter runs fine at 8 Mincrements/s as expected. - The interrupt handler is never called. - The interrupt is based on output compare, but forcing the OC value a little bit after the counter value does not trigger the interrupt handler. - Resetting the GPT and clearing its registers prior to Linux timer init does not help. - There does not seem to be any wait or sleep modes involved. - In this loop, CPSR shows supervisor mode with FIQ disabled and IRQ enabled (same for both U-Boot versions). - This version of Linux does not set VBAR. Neither does the older U-Boot contrary to the latest, but setting VBAR to 0 like with the older U-Boot does not help. The differences in system registers between these U-Boots are really small and seem insignificant. The GPT clock source used by these versions is different, but that should not be an issue with proper reinitialization in Linux. The i.MX51 errata don't mention any issue like that, at least for GPT. ENGcm09114 is similar, but in a very different context. The next step is to dig into the interrupt controller settings and vectors to check that Linux sets up everything properly. This issue is very likely caused by this FSL Linux that unduly relies on the bootloader to initialize something. Best regards, Benoît

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Re: [U-Boot] Don't get any interrupts once I boot into Linux
by Benoît Thébaudeau 14 Sep '12

14 Sep '12

On Friday, September 14, 2012 6:08:15 PM, Greg Topmiller wrote: > Thanks Benoit, > > I also tried changing the uboot V2012.07, file arm/cpu/armv7/timer.c > to use the IPG clock rather than the 32Khz but no difference. OK, as expected. > It looks like the FSL interrupt initialization is in > arch/arm/plat-mxc/tzic.c file. I don't see anything obvious. It's > not real big. I have a Lauterbach debugger that I have been using > to step thru the Linux code. The mxc_timer_interrupt never occurs. We'll look into the interrupt controller next week. Please keep us informed if you find anything. We'll do the same. Will you please answer the following questions? - Which SoC are you using? i.MX51? - Which board? mx51evk? - Which Linux version? Mainline or FSL's? Best regards, Benoît

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[U-Boot] [PATCH] Correct the first byte of idcode1 for S25FL256S part
by 402jagan＠gmail.com 14 Sep '12

14 Sep '12

From: Jagannadha Sutradharudu Teki <402jagan(a)gmail.com> First byte of idcode1 for S25FL256S was miss assinged, so I was corrected and tested the same. Regards, Jagan. Jagannadha Sutradharudu Teki (1): sf: spansion: Correct the idcode1 of S25FL256S part drivers/mtd/spi/spansion.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

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[U-Boot] [PATCH 1/4 v4] serial: Add Zynq serial driver
by Michal Simek 14 Sep '12

14 Sep '12

The driver is used on Xilinx Zynq platform. Signed-off-by: Michal Simek <monstr(a)monstr.eu> CC: Joe Hershberger <joe.hershberger(a)gmail.com> CC: Marek Vasut <marex(a)denx.de> --- v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART Rename driver name Remove driver description v3: SERIAL_MULTI support Rename xdfuart to uart_zynq v4: Properly spell out the structure member names of serial_driver --- common/serial.c | 8 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_zynq.c | 247 ++++++++++++++++++++++++++++++++++++++++++ include/serial.h | 5 + 4 files changed, 261 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_zynq.c diff --git a/common/serial.c b/common/serial.c index 75cc1bb..4f2bc7f 100644 --- a/common/serial.c +++ b/common/serial.c @@ -122,6 +122,14 @@ void serial_initialize(void) serial_register(&uartlite_serial3_device); # endif /* XILINX_UARTLITE_BASEADDR3 */ #endif /* CONFIG_XILINX_UARTLITE */ +#if defined(CONFIG_ZYNQ_SERIAL) +# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 + serial_register(&uart_zynq_serial0_device); +# endif +# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 + serial_register(&uart_zynq_serial1_device); +# endif +#endif serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 65d0f23..dfc22a4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o +COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c new file mode 100644 index 0000000..3832236 --- /dev/null +++ b/drivers/serial/serial_zynq.c @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2012 Michal Simek <monstr(a)monstr.eu> + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include <linux/compiler.h> +#include <serial.h> + +#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ + +#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ +#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ +#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ +#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ + +#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ + +/* Some clock/baud constants */ +#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ +#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ + +struct uart_zynq { + u32 control; /* Control Register [8:0] */ + u32 mode; /* Mode Register [10:0] */ + u32 reserved1[4]; + u32 baud_rate_gen; /* Baud Rate Generator [15:0] */ + u32 reserved2[4]; + u32 channel_sts; /* Channel Status [11:0] */ + u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */ + u32 baud_rate_divider; /* Baud Rate Divider [7:0] */ +}; + +static struct uart_zynq *uart_zynq_ports[2] = { +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 + [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0, +#endif +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 + [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1, +#endif +}; + +struct uart_zynq_params { + u32 baudrate; + u32 clock; +}; + +static struct uart_zynq_params uart_zynq_ports_param[2] = { +#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) + [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, + [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, +#endif +#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) + [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, + [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, +#endif +}; + +/* Set up the baud rate in gd struct */ +static void uart_zynq_serial_setbrg(const int port) +{ + /* Calculation results. */ + unsigned int calc_bauderror, bdiv, bgen; + unsigned long calc_baud = 0; + unsigned long baud = uart_zynq_ports_param[port].baudrate; + unsigned long clock = uart_zynq_ports_param[port].clock; + struct uart_zynq *regs = uart_zynq_ports[port]; + + /* master clock + * Baud rate = ------------------ + * bgen * (bdiv + 1) + * + * Find acceptable values for baud generation. + */ + for (bdiv = 4; bdiv < 255; bdiv++) { + bgen = clock / (baud * (bdiv + 1)); + if (bgen < 2 || bgen > 65535) + continue; + + calc_baud = clock / (bgen * (bdiv + 1)); + + /* + * Use first calculated baudrate with + * an acceptable (<3%) error + */ + if (baud > calc_baud) + calc_bauderror = baud - calc_baud; + else + calc_bauderror = calc_baud - baud; + if (((calc_bauderror * 100) / baud) < 3) + break; + } + + writel(bdiv, &regs->baud_rate_divider); + writel(bgen, &regs->baud_rate_gen); +} + +/* Initialize the UART, with...some settings. */ +static int uart_zynq_serial_init(const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + if (!regs) + return -1; + + /* RX/TX enabled & reset */ + writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ + ZYNQ_UART_CR_RXRST, &regs->control); + writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */ + uart_zynq_serial_setbrg(port); + + return 0; +} + +static void uart_zynq_serial_putc(const char c, const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) + WATCHDOG_RESET(); + + if (c == '\n') { + writel('\r', &regs->tx_rx_fifo); + while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) + WATCHDOG_RESET(); + } + writel(c, &regs->tx_rx_fifo); +} + +static void uart_zynq_serial_puts(const char *s, const int port) +{ + while (*s) + uart_zynq_serial_putc(*s++, port); +} + +static int uart_zynq_serial_tstc(const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + return (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; +} + +static int uart_zynq_serial_getc(const int port) +{ + struct uart_zynq *regs = uart_zynq_ports[port]; + + while (!uart_zynq_serial_tstc(port)) + WATCHDOG_RESET(); + return readl(&regs->tx_rx_fifo); +} + +#if !defined(CONFIG_SERIAL_MULTI) +int serial_init(void) +{ + return uart_zynq_serial_init(0); +} + +void serial_setbrg(void) +{ + uart_zynq_serial_setbrg(0); +} + +void serial_putc(const char c) +{ + uart_zynq_serial_putc(c, 0); +} + +void serial_puts(const char *s) +{ + uart_zynq_serial_puts(s, 0); +} + +int serial_getc(void) +{ + return uart_zynq_serial_getc(0); +} + +int serial_tstc(void) +{ + return uart_zynq_serial_tstc(0); +} +#else +/* Multi serial device functions */ +#define DECLARE_PSSERIAL_FUNCTIONS(port) \ + int uart_zynq##port##_init(void) \ + { return uart_zynq_serial_init(port); } \ + void uart_zynq##port##_setbrg(void) \ + { return uart_zynq_serial_setbrg(port); } \ + int uart_zynq##port##_getc(void) \ + { return uart_zynq_serial_getc(port); } \ + int uart_zynq##port##_tstc(void) \ + { return uart_zynq_serial_tstc(port); } \ + void uart_zynq##port##_putc(const char c) \ + { uart_zynq_serial_putc(c, port); } \ + void uart_zynq##port##_puts(const char *s) \ + { uart_zynq_serial_puts(s, port); } + +/* Serial device descriptor */ +#define INIT_PSSERIAL_STRUCTURE(port, __name) { \ + .name = __name, \ + .init = uart_zynq##port##_init, \ + .uninit = NULL, \ + .setbrg = uart_zynq##port##_setbrg, \ + .getc = uart_zynq##port##_getc, \ + .tstc = uart_zynq##port##_tstc, \ + .putc = uart_zynq##port##_putc, \ + .puts = uart_zynq##port##_puts, \ +} + +DECLARE_PSSERIAL_FUNCTIONS(0); +struct serial_device uart_zynq_serial0_device = + INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); +DECLARE_PSSERIAL_FUNCTIONS(1); +struct serial_device uart_zynq_serial1_device = + INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); + +__weak struct serial_device *default_serial_console(void) +{ + if (uart_zynq_ports[0]) + return &uart_zynq_serial0_device; + if (uart_zynq_ports[1]) + return &uart_zynq_serial1_device; + + return NULL; +} +#endif diff --git a/include/serial.h b/include/serial.h index d76d6df..826b488 100644 --- a/include/serial.h +++ b/include/serial.h @@ -90,6 +90,11 @@ extern struct serial_device bfin_serial2_device; extern struct serial_device bfin_serial3_device; #endif +#if defined(CONFIG_ZYNQ_SERIAL) +extern struct serial_device uart_zynq_serial0_device; +extern struct serial_device uart_zynq_serial1_device; +#endif + extern void serial_register(struct serial_device *); extern void serial_initialize(void); extern void serial_stdio_init(void); -- 1.7.0.4

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[U-Boot] [PATCH 1/2] mmc: at91: add multi block read/write support.
by Josh Wu 14 Sep '12

14 Sep '12

Since the at91sam9263, the mmc hardware support multi blocks read/write. So this driver enable it. This patch also change delay time to max value, which can avoid the timeout error in rare case. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- drivers/mmc/gen_atmel_mci.c | 16 +++++++++++++--- include/atmel_mci.h | 5 ++++- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 4968c5e..ec075f7 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -24,7 +24,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include <common.h> #include <mmc.h> #include <part.h> @@ -87,6 +86,11 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) | MMCI_BF(BLKLEN, blklen) | MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF)), &mci->mr); + /* + * On some new platforms BLKLEN in mci->mr is ignored. + * Should use the BLKLEN in the block register. + */ + writel(blklen << MMCI_BLKLEN_OFFSET, &mci->blkr); initialized = 1; } @@ -183,6 +187,12 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Figure out the transfer arguments */ cmdr = mci_encode_cmd(cmd, data, &error_flags); + /* For multi blocks read/write, set the block register */ + if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) + || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) + writel(data->blocks | mmc->read_bl_len << MMCI_BLKLEN_OFFSET, + &mci->blkr); + /* Send the command */ writel(cmd->cmdarg, &mci->argr); writel(cmdr, &mci->cmdr); @@ -310,8 +320,8 @@ static int mci_init(struct mmc *mmc) writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */ writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */ - /* Initial Time-outs */ - writel(0x5f, &mci->dtor); + /* This delay can be optimized, but stick with max value */ + writel(0x7f, &mci->dtor); /* Disable Interrupts */ writel(~0UL, &mci->idr); diff --git a/include/atmel_mci.h b/include/atmel_mci.h index 3dd5d67..85468d4 100644 --- a/include/atmel_mci.h +++ b/include/atmel_mci.h @@ -38,7 +38,7 @@ typedef struct atmel_mci { u32 sdcr; /* 0x0c */ u32 argr; /* 0x10 */ u32 cmdr; /* 0x14 */ - u32 _18; /* 0x18 */ + u32 blkr; /* 0x18 */ u32 _1c; /* 0x1c */ u32 rspr; /* 0x20 */ u32 rspr1; /* 0x24 */ @@ -118,6 +118,9 @@ typedef struct atmel_mci { #define MMCI_TRTYP_OFFSET 19 #define MMCI_TRTYP_SIZE 2 +/* Bitfields in BLKR */ +#define MMCI_BLKLEN_OFFSET 16 + /* Bitfields in RSPRx */ #define MMCI_RSP_OFFSET 0 #define MMCI_RSP_SIZE 32 -- 1.7.9.5

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[U-Boot] [Question] [ARM] global data array defined in board.c linkage problem : overlapping with relocation sections
by Sun Eric 14 Sep '12

14 Sep '12

Hi all, Recently I tried to bring up a new platform with the latest U-Boot code (the git hash is e66443f). For recording some info before UART becomes functional, I added a circular array in "arch/arm/lib/board.c", together with some "printf" like function which simply write the debug string to the array. Things works fine until the code goes to "relocate_code()", the "copy_loop" is finished but once the code goes to "fixloop", quite soon the code will attempt to write to some invalid address, then the system will hang. Further debugging shows that the root cause is that, the circular array I added in board.c is linked to some address which in between "__rel_dyn_start" and "__rel_dyn_end". Originally the area contains all relocation section entries, which has the format " address_to_fix 0x17 address_to_fix 0x17 ....". Now for some reason the linker put the circular array here, and write to this circular array will overwrite it with some random data, thus later "address fix" algorithm will easily write to invalid address. On the other hand, this issue seems only happen to board.c. If I experimentally add it to another file, say "net/bootp.c". The linkage becomes correct, the array is linked to BSS section which is after "__rel_dyn_end". I looked at the build log, and don't find a difference on how "board.o" and "bootp.o" is linked to the final u-boot elf file. So I can't understand why the final linkage result is different. Can someone please help me out? The array I added is as the following: ----------------------------------------------------------- static uchar local_log_buf[LOCAL_BUF_SIZE] = {0}; static ushort local_log_buf_index = 0; static void initlocalbuf(void) {...} void writelocalbuf(char* fmt, ...) {...} void dumplocalbuf(void) {...} ----------------------------------------------------------- Regards, Eric

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[U-Boot] [PATCH 1/4 v2] serial: Add Zynq serial driver
by Michal Simek 14 Sep '12

14 Sep '12

The driver is used on Xilinx Zynq platform. Signed-off-by: Michal Simek <monstr(a)monstr.eu> --- v2: Use Zynq name instead of Dragonfire and XPSS/XDFUART Rename driver name Remove driver description --- drivers/serial/Makefile | 1 + drivers/serial/serial_zynq.c | 200 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 201 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_zynq.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 65d0f23..dfc22a4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o +COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c new file mode 100644 index 0000000..c49da3b --- /dev/null +++ b/drivers/serial/serial_zynq.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2012 Michal Simek <monstr(a)monstr.eu> + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include <serial.h> + +#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ + +#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ +#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ +#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ +#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ + +#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ + +/* Some clock/baud constants */ +#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ +#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ + +struct xdfuart { + u32 control; /* Control Register [8:0] */ + u32 mode; /* Mode Register [10:0] */ + u32 reserved1[4]; + u32 baud_rate_gen; /* Baud Rate Generator [15:0] */ + u32 reserved2[4]; + u32 channel_sts; /* Channel Status [11:0] */ + u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */ + u32 baud_rate_divider; /* Baud Rate Divider [7:0] */ +}; + +static struct xdfuart *xdf_ports[2] = { +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 + [0] = (struct xdfuart *)CONFIG_ZYNQ_SERIAL_BASEADDR0, +#endif +#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 + [1] = (struct xdfuart *)CONFIG_ZYNQ_SERIAL_BASEADDR1, +#endif +}; + +struct xdfuart_params { + u32 baudrate; + u32 clock; +}; + +static struct xdfuart_params xdf_ports_param[2] = { +#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) + [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, + [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, +#endif +#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) + [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, + [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, +#endif +}; + +/* Set up the baud rate in gd struct */ +static void xdfuart_serial_setbrg(const int port) +{ + /* Calculation results. */ + unsigned int calc_bauderror, bdiv, bgen; + unsigned long calc_baud = 0; + unsigned long baud = xdf_ports_param[port].baudrate; + unsigned long clock = xdf_ports_param[port].clock; + struct xdfuart *regs = xdf_ports[port]; + + /* master clock + * Baud rate = ------------------ + * bgen * (bdiv + 1) + * + * Find acceptable values for baud generation. + */ + for (bdiv = 4; bdiv < 255; bdiv++) { + bgen = clock / (baud * (bdiv + 1)); + if (bgen < 2 || bgen > 65535) + continue; + + calc_baud = clock / (bgen * (bdiv + 1)); + + /* + * Use first calculated baudrate with + * an acceptable (<3%) error + */ + if (baud > calc_baud) + calc_bauderror = baud - calc_baud; + else + calc_bauderror = calc_baud - baud; + if (((calc_bauderror * 100) / baud) < 3) + break; + } + + writel(bdiv, &regs->baud_rate_divider); + writel(bgen, &regs->baud_rate_gen); +} + +/* Initialize the UART, with...some settings. */ +static int xdfuart_serial_init(const int port) +{ + struct xdfuart *regs = xdf_ports[port]; + + if (!regs) + return -1; + + /* RX/TX enabled & reset */ + writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ + ZYNQ_UART_CR_RXRST, &regs->control); + writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */ + xdfuart_serial_setbrg(port); + + return 0; +} + +static void xdfuart_serial_putc(const char c, const int port) +{ + struct xdfuart *regs = xdf_ports[port]; + + while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) + WATCHDOG_RESET(); + + if (c == '\n') { + writel('\r', &regs->tx_rx_fifo); + while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) + WATCHDOG_RESET(); + } + writel(c, &regs->tx_rx_fifo); +} + +static void xdfuart_serial_puts(const char *s, const int port) +{ + while (*s) + xdfuart_serial_putc(*s++, port); +} + +static int xdfuart_serial_tstc(const int port) +{ + struct xdfuart *regs = xdf_ports[port]; + + return (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; +} + +static int xdfuart_serial_getc(const int port) +{ + struct xdfuart *regs = xdf_ports[port]; + + while (!xdfuart_serial_tstc(port)) + WATCHDOG_RESET(); + return readl(&regs->tx_rx_fifo); +} + +int serial_init(void) +{ + return xdfuart_serial_init(0); +} + +void serial_setbrg(void) +{ + xdfuart_serial_setbrg(0); +} + +void serial_putc(const char c) +{ + xdfuart_serial_putc(c, 0); +} + +void serial_puts(const char *s) +{ + xdfuart_serial_puts(s, 0); +} + +int serial_getc(void) +{ + return xdfuart_serial_getc(0); +} + +int serial_tstc(void) +{ + return xdfuart_serial_tstc(0); +} -- 1.7.0.4

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Re: [U-Boot] [PATCH 2/4 v2] net: Add driver for Zynq Gem IP
by Marek Vasut 14 Sep '12

14 Sep '12

Dear Joe Hershberger, > On Thu, Sep 13, 2012 at 11:45 PM, Marek Vasut <marex(a)denx.de> wrote: > > Dear Joe Hershberger, > > > >> Hi Marek, > >> > >> On Thu, Sep 13, 2012 at 4:28 AM, Marek Vasut <marex(a)denx.de> wrote: > >> > Dear Michal Simek, > >> > > >> >> + /* > >> >> + * Following is the setup for Network Control register. > >> >> + * Bit 2: Set to enable Receive operation. > >> >> + * Bit 3: Set to enable Transmitt operation. > >> >> + * Bit 4: Set to enable MDIO operation. > >> >> + */ > >> >> + tmp = readl(&regs->nwctrl); > >> >> + /* MDIO, Rx and Tx enable */ > >> >> + tmp |= ZYNQ_GEM_NWCTRL_MDEN_MASK | ZYNQ_GEM_NWCTRL_RXEN_MASK | > >> >> + ZYNQ_GEM_NWCTRL_TXEN_MASK; > >> >> + writel(tmp, &regs->nwctrl); > >> > > >> > setbits_le32() > >> > >> This is not equivalent. Using setbits_le32() will not provide a dmb() > >> on the operations the way that readl(), writel() does. I believe this > >> will cause problems when the dcache is enabled, right? > > > > Not when dcache is enabled, the register space isn't cached. But the > > compiler can run some wild optimizations across that. So where's the > > problem, do we add dmb() to clrsetbits() calls ? > > I'm not grokking this paragraph. The only thing that is ever cached is DRAM. It's the only cacheable area configured in the MMU tables. The rest is uncached. And the dmb() doesn't have anything to do with caches, it has to do with compiler reordering the register accesses, which might screw things up. But wait, I shouldn't reply to emails when I've been awake for 20+ hours. Look at the macro again. Let's see an example: clrbits_le32 expands to clrbits(le32, ...) clrbits(le32, ...) expands to out_le32(..., in_le32(...) & ~...) out_le32() expands to out_arch() which expands to __raw_writel() in_le32() expands to in_arch() which expands to __raw_readl() __raw_writel() expands to __arch_putl() __raw_readl() expands to __arch_getl() arch_putl() is *(volatile unsigned long *), therefore compiler reordering doesn't happen accross this (because of the volatile). So is arch_getl() . Bottom line, no need for explicit dmb() in clrsetbits_le32() and friends. But whew, you got me scared there ;-) > You are saying that when the dcache is enabled, that the register > space is not cached? Why would it not be? It doesn't know those > addresses from any other memory, right? > > clrsetbits() does not call dmb(). Perhaps it should. It's never been > clear to me why writeX/readX used dmb, but out_XY/in_XY/clrsetbits_XY > do not. Are they not both for accessing registers? > > Perhaps test all of these drivers with write-back cache enabled and > make sure they work. > > -Joe Best regards, Marek Vasut

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[U-Boot] [PATCH] USB: musb_udc: Bugfix musb_peri_rx_ep
by Tom Rini 14 Sep '12

14 Sep '12

From: Pankaj Bharadiya <pankaj.bharadiya(a)ti.com> The endpoint rx count register value will be zero if it is read before receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set. Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before reading endpoint rx count register. Proceed with rx count read and FIFO read only if RXPKTRDY bit is set. As this makes the function fit less-well within 80 columns, use __func__ in some debug statements rather than __PRETTY_FUNCTION__ as they are identical for C programs. Signed-off-by: Pankaj Bharadiya <pankaj.bharadiya(a)ti.com> Signed-off-by: Tom Rini <trini(a)ti.com> --- drivers/usb/musb/musb_udc.c | 97 +++++++++++++++++++++++-------------------- 1 file changed, 52 insertions(+), 45 deletions(-) diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c index 09cdec3..7180de8 100644 --- a/drivers/usb/musb/musb_udc.c +++ b/drivers/usb/musb/musb_udc.c @@ -640,58 +640,65 @@ static void musb_peri_ep0(void) static void musb_peri_rx_ep(unsigned int ep) { - u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount); - - if (peri_rxcount) { - struct usb_endpoint_instance *endpoint; - u32 length; - u8 *data; - - endpoint = GET_ENDPOINT(udc_device, ep); - if (endpoint && endpoint->rcv_urb) { - struct urb *urb = endpoint->rcv_urb; - unsigned int remaining_space = urb->buffer_length - - urb->actual_length; - - if (remaining_space) { - int urb_bad = 0; /* urb is good */ - - if (peri_rxcount > remaining_space) - length = remaining_space; - else - length = peri_rxcount; - - data = (u8 *) urb->buffer_data; - data += urb->actual_length; - - /* The common musb fifo reader */ - read_fifo(ep, length, data); - - musb_peri_rx_ack(ep); - - /* - * urb's actual_length is updated in - * usbd_rcv_complete - */ - usbd_rcv_complete(endpoint, length, urb_bad); + u8 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr); + if ((peri_rxcsr & MUSB_RXCSR_RXPKTRDY)) { + u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount); + if (peri_rxcount) { + struct usb_endpoint_instance *endpoint; + u32 length; + u8 *data; + endpoint = GET_ENDPOINT(udc_device, ep); + if (endpoint && endpoint->rcv_urb) { + struct urb *urb = endpoint->rcv_urb; + unsigned int remaining_space = + urb->buffer_length - + urb->actual_length; + + if (remaining_space) { + int urb_bad = 0; /* urb is good */ + + if (peri_rxcount > remaining_space) + length = remaining_space; + else + length = peri_rxcount; + + data = (u8 *) urb->buffer_data; + data += urb->actual_length; + + /* The common musb fifo reader */ + read_fifo(ep, length, data); + + musb_peri_rx_ack(ep); + + /* + * urb's actual_length is updated in + * usbd_rcv_complete + */ + usbd_rcv_complete(endpoint, length, + urb_bad); + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d" + " no space " + "in rcv " + "buffer\n", + __func__, + ep); + } } else { if (debug_level > 0) - serial_printf("ERROR : %s %d no space " - "in rcv buffer\n", - __PRETTY_FUNCTION__, ep); + serial_printf("ERROR : %s %d problem " + "with endpoint\n", + __func__, ep); + } } else { if (debug_level > 0) - serial_printf("ERROR : %s %d problem with " - "endpoint\n", - __PRETTY_FUNCTION__, ep); + serial_printf("ERROR : %s %d with nothing " + "to do\n", __func__, ep); } - - } else { - if (debug_level > 0) - serial_printf("ERROR : %s %d with nothing to do\n", - __PRETTY_FUNCTION__, ep); } } -- 1.7.9.5

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[U-Boot] How to understand the code flow of u-boot
by Manoj.J 14 Sep '12

14 Sep '12

Hi, Can anyone tell how to understand the flow of u-boot source code, In specific i want to know how u-boot handles nand flash. It would be of great help in starting to learn about u-boot. -- *Regards* *Manoj.J*

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