September 2012 - U-Boot

[U-Boot] [PATCH] MX6: drop binary constants from iomux header
by Stefano Babic 16 Sep '12

16 Sep '12

Constants set with binary value (0b...) are not compiled from old toolchain when used by the clrsetbits_le32 macro. Replaces them with the corresponding hex value. The error reported (for example with the mx6qsabrelite board) is something like: mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- arch/arm/include/asm/arch-mx6/iomux.h | 124 ++++++++++++++++----------------- 1 file changed, 62 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index a1255f9..d23abd7 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -34,21 +34,21 @@ #define IOMUXC_GPR13_SATA_PHY_2_MASK (0x1f<<2) #define IOMUXC_GPR13_SATA_PHY_1_MASK (3<<0) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0b000<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (0b001<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (0b010<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (0b011<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (0b100<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (0b101<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (0b110<<24) -#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (0b111<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB (3<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB (4<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB (5<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB (6<<24) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB (7<<24) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19) -#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19) +#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19) #define IOMUXC_GPR13_SATA_SPEED_1P5G (0<<15) #define IOMUXC_GPR13_SATA_SPEED_3G (1<<15) @@ -63,55 +63,55 @@ #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 (4<<11) #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16 (5<<11) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0b0000<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (0b0001<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (0b0010<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (0b0011<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (0b0100<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (0b0101<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (0b0110<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (0b0111<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (0b1000<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (0b1001<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0b1010<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0b1011<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0b1100<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0b1101<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0b1110<<7) -#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0b1111<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB (0<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB (1<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB (2<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB (3<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB (4<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB (5<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB (6<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB (7<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB (8<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB (9<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB (0xA<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB (0xB<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB (0xC<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB (0xD<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB (0xE<<7) +#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB (0xF<<7) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0b00000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (0b00001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (0b00010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (0b00011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (0b00100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (0b00101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (0b00110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (0b00111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (0b01000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (0b01001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0b01010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0b01011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0b01100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0b01101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0b01110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0b01111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0b10000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0b10001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0b10010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0b10011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0b10100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0b10101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0b10110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0b10111<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0b11000<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0b11001<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0b11010<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0b11011<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0b11100<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0b11101<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0b11110<<2) -#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0b11111<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V (0<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V (1<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V (2<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V (3<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V (4<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V (5<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V (6<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V (7<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V (8<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V (9<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V (0xA<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V (0xB<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V (0xC<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V (0xD<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V (0xE<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V (0xF<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V (0x10<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V (0x11<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V (0x12<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V (0x13<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V (0x14<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V (0x15<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V (0x16<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V (0x17<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V (0x18<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V (0x19<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V (0x1A<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V (0x1B<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V (0x1C<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V (0x1D<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V (0x1E<<2) +#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V (0x1F<<2) #define IOMUXC_GPR13_SATA_PHY_1_FAST 0 #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1 -- 1.7.9.5

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[U-Boot] Don't get any interrupts once I boot into Linux
by Greg Topmiller 16 Sep '12

16 Sep '12

I downloaded the V2012.07 version of u-boot from the git.denx.de repository and built it for our target. U-boot boots up properly and I can use the commands but now when I boot into Linux I don't seem to be getting interrupts. The Linux kernel hangs in the calculate_delay function waiting for ticks != jiffies. I do not get the interrupt for the timer. I have verified that our previous u-boot that is based on the 2009.12 version with Freescale patches does work. The timer interrupt occurs and jiffies is incremented allowing the loop to exit. Any help would be appreciated. Thanks, Greg

4 4

[U-Boot] [PATCH] fdt: Check if the FDT address is configured
by Marek Vasut 15 Sep '12

15 Sep '12

In case the "fdt addr" command wasn't ran yet and any other "fdt" subcommand was issued, the system crashed due to NULL pointer being used. This is caused by "fdt addr" command setting up a pointer to the FDT memory location. Prior issuing "fdt addr", the pointer is NULL so calling any other subcommands crashed the u-boot. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> --- common/cmd_fdt.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) Note: Damn, I'm falling asleep already :-( I hope the text above at least makes sense though. diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 9a5c53e..e2225c4 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -114,10 +114,21 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } } + return CMD_RET_SUCCESS; + } + + if (!working_fdt) { + puts( + "No FDT memory address configured. Please configure\n" + "the FDT address via \"fdt addr <address>\" command.\n" + "Aborting!\n"); + return CMD_RET_FAILURE; + } + /* * Move the working_fdt */ - } else if (strncmp(argv[1], "mo", 2) == 0) { + if (strncmp(argv[1], "mo", 2) == 0) { struct fdt_header *newaddr; int len; int err; -- 1.7.10.4

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[U-Boot] A little introduction
by Henrik Nordström 15 Sep '12

15 Sep '12

A little introduction to let you know who I am and why I am here. I am maintaining u-boot support for Allwinner A1x class CPUs, and ARM Cortex A8 class SoC by chineese Allwinner Tech. http://www.github.com/hno/uboot-allwinner/ To be honest I am not guilty to much of the code. The bulk of the A10 support was kindly donated by Allwinner via Tom Cubie, including a SPL support enabling the A10 boot rom to boot u-boot dir4ectly from sd cards. So far for th A10 I have mostly managed to produce failed ports to later u-boot versions where SPL crashes and cleaned things up a little. For the last couple of months I have been staring at A13, the newer little brother of A10, trying to get SPL to work there and now finally I have got the pieces together and we have a working (but not optimal) SPL for A13. Also involved in the free kernel development for Allwinner A1x class SoCs and other supporting tools for the SoC family. Outside u-boot I am the proud father of 6 wonderful kids, president of the Squid Software Foundation, and an independent IT consultant focusing on Linux & networking. Been hacking on computers for more than 3 decades, ranging from demo programming, game development, web interfaces, application level proxies, kernel drivers, and now back to bare metal in u-boot. My work on u-boot is done by interest in both the SoCs in question and bare metal development, and plan to continue looking after this class of SoCs for quite some time. Kind regards Henrik Nordström Sweden

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[U-Boot] u-boot support for reading USB sticks formatted as NTFS
by Bill 14 Sep '12

14 Sep '12

In the u-boot command line, I can use fatls & fatload to read files from a formatted USB stick formatted as fat16/fat32. However, is there support to read files from a USB stick formatted as NTFS? Bill

2 1

Re: [U-Boot] Don't get any interrupts once I boot into Linux
by Benoît Thébaudeau 14 Sep '12

14 Sep '12

Greg, On Friday, September 14, 2012 9:35:28 PM, Greg Topmiller wrote: > I've made some progress. Yes, the TZIC is not being set up properly. > This is because the system and rev information is not being put > into the ATAG that is passed to the Linux kernel. What is added is > " #define CONFIG_REVISION_TAG 1" in the config file but then > "get_board_rev" needs to be implemented. I am going to take what is > in FSL u-boot for that. I have to get going now but hope to finish > this on Monday. Good news! This function can easily be added locally to your board init file. I don't think that mainline U-Boot should be changed for that since it is an issue in FSL's Linux that relies on the revision tag instead of extracting itself the revision information from the hardware. Best regards, Benoît

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[U-Boot] [PATCHv3] ARM: Add Altera SOCFPGA Cyclone5
by dinguyen＠altera.com 14 Sep '12

14 Sep '12

From: Dinh Nguyen <dinguyen(a)altera.com> Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Applied on top of trini/WIP/spl-improvements v6 Test building edminiv2_config and km_kirkwood_config w/o errors. Signed-off-by: Dinh Nguyen <dinguyen(a)altera.com> Signed-off-by: Chin Liang See <clsee(a)altera.com> Signed-off-by: Pavel Machek <pavel(a)denx.de> --- MAINTAINERS | 5 + arch/arm/cpu/armv7/socfpga/Makefile | 51 ++++ arch/arm/cpu/armv7/socfpga/config.mk | 16 ++ arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 77 +++++++ arch/arm/cpu/armv7/socfpga/misc.c | 54 +++++ arch/arm/cpu/armv7/socfpga/spl.c | 48 ++++ arch/arm/cpu/armv7/socfpga/timer.c | 105 +++++++++ arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 57 +++++ arch/arm/include/asm/arch-kirkwood/cpu.h | 1 - arch/arm/include/asm/arch-orion5x/cpu.h | 1 - arch/arm/include/asm/arch-socfpga/reset_manager.h | 36 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 27 +++ arch/arm/include/asm/arch-socfpga/spl.h | 26 ++ arch/arm/include/asm/arch-socfpga/timer.h | 29 +++ board/altera/socfpga_cyclone5/Makefile | 50 ++++ board/altera/socfpga_cyclone5/socfpga_cyclone5.c | 85 +++++++ boards.cfg | 1 + include/common.h | 2 +- include/configs/socfpga_cyclone5.h | 240 ++++++++++++++++++++ 19 files changed, 908 insertions(+), 3 deletions(-) create mode 100644 arch/arm/cpu/armv7/socfpga/Makefile create mode 100644 arch/arm/cpu/armv7/socfpga/config.mk create mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/socfpga/misc.c create mode 100644 arch/arm/cpu/armv7/socfpga/spl.c create mode 100644 arch/arm/cpu/armv7/socfpga/timer.c create mode 100644 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-socfpga/reset_config.h create mode 100644 arch/arm/include/asm/arch-socfpga/reset_manager.h create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h create mode 100644 arch/arm/include/asm/arch-socfpga/spl.h create mode 100644 arch/arm/include/asm/arch-socfpga/timer.h create mode 100644 board/altera/socfpga_cyclone5/Makefile create mode 100644 board/altera/socfpga_cyclone5/socfpga_cyclone5.c create mode 100644 include/configs/socfpga_cyclone5.h diff --git a/MAINTAINERS b/MAINTAINERS index c5a6f2f..df48dea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -765,6 +765,11 @@ Nagendra T S <nagendra(a)mistralsolutions.com> am3517_crane ARM ARMV7 (AM35x SoC) +Dinh Nguyen <dinguyen(a)altera.com> +Chin Liang See <clsee(a)altera.com> + + socfpga socfpga_cyclone5 + Kyungmin Park <kyungmin.park(a)samsung.com> apollon ARM1136EJS diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile new file mode 100644 index 0000000..376a4bd --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Copyright (C) 2012 Altera Corporation <www.altera.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS-y := misc.o timer.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk new file mode 100644 index 0000000..b72ed1e --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/config.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +ifndef CONFIG_SPL_BUILD +ALL-y += $(obj)u-boot.img +endif diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S new file mode 100644 index 0000000..001b37d --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <config.h> +#include <version.h> + +/* Save the parameter pass in by previous boot loader */ +.global save_boot_params +save_boot_params: + /* save the parameter here */ + + /* + * Setup stack for exception, which is located + * at the end of on-chip RAM. We don't expect exception prior to + * relocation and if that happens, we won't worry -- it will overide + * global data region as the code will goto reset. After relocation, + * this region won't be used by other part of program. + * Hence it is safe. + */ + ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) + ldr r1, =IRQ_STACK_START_IN + str r0, [r1] + + bx lr + + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + + /* Remap */ +#ifdef CONFIG_SPL_BUILD + /* + * SPL : configure the remap (L3 NIC-301 GPV) + * so the on-chip RAM at lower memory instead ROM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x19 + str r1, [r0] +#else + /* + * U-Boot : configure the remap (L3 NIC-301 GPV) + * so the SDRAM at lower memory instead on-chip RAM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x2 + str r1, [r0] + + /* Private components security */ + + /* + * U-Boot : configure private timer, global timer and cpu + * component access as non secure for kernel stage (as required + * by kernel) + */ + mrc p15,4,r0,c15,c0,0 + add r1, r0, #0x54 + ldr r2, [r1] + orr r2, r2, #0xff + orr r2, r2, #0xf00 + str r2, [r1] +#endif /* #ifdef CONFIG_SPL_BUILD */ + mov pc, lr diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c new file mode 100644 index 0000000..49d4f4d --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset + */ +__attribute__((noreturn)) void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor. + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + return 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c new file mode 100644 index 0000000..944238b --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <version.h> +#include <image.h> +#include <malloc.h> +#include <asm/arch/reset_manager.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_RAM; +} + +/* + * Board initialization after bss clearance + */ +void spl_board_init(void) +{ + /* init timer for enabling delay function */ + timer_init(); + + /* de-assert reset for peripherals and bridges based on handoff */ + reset_deassert_peripherals_handoff(); + + /* enable console uart printing */ + preloader_console_init(); +} diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c new file mode 100644 index 0000000..1ceb6e9 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; + +/* + * Timer initialization + */ +int timer_init(void) +{ + writel(TIMER_LOAD_VAL, &timer_base->load_val); + writel(TIMER_LOAD_VAL, &timer_base->curr_val); + setbits_le32(&timer_base->ctrl, 0x3); + return 0; +} + +static u32 read_timer(void) +{ + return readl(&timer_base->curr_val); +} + +/* + * Delay x useconds + */ +void __udelay(unsigned long usec) +{ + unsigned long now, last; + /* + * get the tmo value based on timer clock speed + * tmo = delay required / period of timer clock + */ + long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000; + + last = read_timer(); + while (tmo > 0) { + now = read_timer(); + if (last >= now) + /* normal mode (non roll) */ + tmo -= last - now; + else + /* we have overflow of the count down timer */ + tmo -= TIMER_LOAD_VAL - last + now; + last = now; + } +} + +/* + * Get the timer value + */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * Timer : get the time difference + * Unit of tick is based on the CONFIG_SYS_HZ + */ +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + if (gd->lastinc >= now) { + /* normal mode (non roll) */ + /* move stamp forward with absolute diff ticks */ + gd->tbl += gd->lastinc - now; + } else { + /* we have overflow of the count down timer */ + gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now; + } + gd->lastinc = now; + return gd->tbl; +} + +/* + * Reset the timer + */ +void reset_timer(void) +{ + /* capture current decrementer value time */ + gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + /* start "advancing" time stamp from 0 */ + gd->tbl = 0; +} + diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds new file mode 100644 index 0000000..0236daa --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sram + + . = ALIGN(8); + __malloc_start = .; + . = . + CONFIG_SPL_MALLOC_SIZE; + __malloc_end = .; + + . = . + CONFIG_SPL_STACK_SIZE; + . = ALIGN(8); + __stack_start = .; +} diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index d28c51a..7a53c8f 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -155,7 +155,6 @@ struct kwgpio_registers { /* * functions */ -void reset_cpu(unsigned long ignored); unsigned char get_random_hex(void); unsigned int kw_sdram_bar(enum memory_bank bank); unsigned int kw_sdram_bs(enum memory_bank bank); diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 2f52ca8..17b9b69 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -251,7 +251,6 @@ struct orion5x_ddr_addr_decode_registers { /* * functions */ -void reset_cpu(unsigned long ignored); u32 orion5x_device_id(void); u32 orion5x_device_rev(void); unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); diff --git a/arch/arm/include/asm/arch-socfpga/reset_config.h b/arch/arm/include/asm/arch-socfpga/reset_config.h new file mode 100644 index 0000000..e69de29 diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h new file mode 100644 index 0000000..dd4a0c6 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _RESET_MANAGER_H_ +#define _RESET_MANAGER_H_ + +void reset_deassert_peripherals_handoff(void); + +struct socfpga_reset_manager { + u32 padding1; + u32 ctrl; + u32 padding2; + u32 padding3; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; +}; + +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 + +#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h new file mode 100644 index 0000000..f353eb2 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_BASE_ADDRS_H_ +#define _SOCFPGA_BASE_ADDRS_H_ + +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 + +#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h new file mode 100644 index 0000000..c2014c5 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/spl.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2012 Pavel Machek <pavel(a)denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_SPL_H_ +#define _SOCFPGA_SPL_H_ + +/* Symbols from linker script */ +extern void __malloc_start, __malloc_end, __stack_start; + +#define BOOT_DEVICE_RAM 1 + +#endif diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h new file mode 100644 index 0000000..830c94a --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/timer.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_TIMER_H_ +#define _SOCFPGA_TIMER_H_ + +struct socfpga_timer { + u32 load_val; + u32 curr_val; + u32 ctrl; + u32 eoi; + u32 int_stat; +}; + +#endif diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile new file mode 100644 index 0000000..43bbc37 --- /dev/null +++ b/board/altera/socfpga_cyclone5/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := socfpga_cyclone5.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c new file mode 100644 index 0000000..858ab3c --- /dev/null +++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> + +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +void show_boot_progress(int progress) +{ + debug("Boot reached stage %d\n", progress); +} + +/* + * Print CPU information + */ +int print_cpuinfo(void) +{ + puts("CPU : Altera SOCFPGA Platform\n"); + return 0; +} + +/* + * Print Board information + */ +int checkboard(void) +{ + puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + return 0; +} + +/* + * Initialization function which happen at early stage of c code + */ +int board_early_init_f(void) +{ + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + icache_enable(); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + return 0; +} +#endif + +/* + * DesignWare Ethernet initialization + */ +/* We know all the init functions have been run now */ +int board_eth_init(bd_t *bis) +{ + return 0; +} diff --git a/boards.cfg b/boards.cfg index fdb84ad..1b5c860 100644 --- a/boards.cfg +++ b/boards.cfg @@ -261,6 +261,7 @@ seaboard arm armv7 seaboard nvidia ventana arm armv7 ventana nvidia tegra2 whistler arm armv7 whistler nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 +socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/include/common.h b/include/common.h index 55025c0..e57301f 100644 --- a/include/common.h +++ b/include/common.h @@ -582,7 +582,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); -void reset_cpu (ulong addr); +void reset_cpu (ulong addr) __attribute__((noreturn)); #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd); #ifdef CONFIG_PCI diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h new file mode 100644 index 0000000..bb96274 --- /dev/null +++ b/include/configs/socfpga_cyclone5.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/socfpga_base_addrs.h> + +/* + * High level configuration + */ + +#define CONFIG_ARMV7 +#define CONFIG_L2_OFF +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_USE_IRQ + +#define CONFIG_MISC_INIT_R +#define CONFIG_SINGLE_BOOTLOADER +#define CONFIG_SOCFPGA + +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#define V_NS16550_CLK 1000000 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_TIMER_CLOCK_KHZ 2400 +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Enable early stage initialization at C environment + */ +#define CONFIG_BOARD_EARLY_INIT_F + +/* flat device tree */ +#define CONFIG_OF_LIBFDT +/* skip updating the FDT blob */ +#define CONFIG_FDT_BLOB_SKIP_UPDATE +/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ +#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) + +/* + * Memory allocation (MALLOC) + */ +/* Room required on the stack for the environment data */ +#define CONFIG_ENV_SIZE 1024 +/* Size of DRAM reserved for malloc() use */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +/* Reserving 0x100 space at back of scratch RAM for debug info */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + + +/* + * Command line configuration. + */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +/* FAT file system support */ +#define CONFIG_CMD_FAT + + +/* + * Misc + */ +#define CONFIG_DOS_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif + +/* + * Environment setup + */ + +/* Delay before automatically booting the default image */ +#define CONFIG_BOOTDELAY 3 +/* Enable auto completion of commands using TAB */ +#define CONFIG_AUTO_COMPLETE +/* use "hush" command parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMD_RUN + +#define CONFIG_BOOTCOMMAND "run ramboot" + +/* + * arguments passed to the bootm command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=uImage\0" \ + "fdt_addr=100\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* using environment setting for stdin, stdout, stderr */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* Enable the call to overwrite_console() */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +/* Enable overwrite of previous console environment settings */ +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + + +/* + * Hardware drivers + */ + +/* + * SDRAM Memory Map + */ +/* We have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +/* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* SDRAM memory size */ +#define PHYS_SDRAM_1_SIZE 0x80000000 + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE + +/* + * NS16550 Configuration + */ +#define UART0_BASE SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 UART0_BASE + +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * FLASH + */ +#define CONFIG_SYS_NO_FLASH + +/* + * L4 OSC1 Timer 0 + */ +/* This timer use eosc1 where the clock frequency is fixed + * throughout any condition */ +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS + +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +#define CONFIG_ENV_IS_NOWHERE + +/* + * SPL "Second Program Loader" aka Initial Software + */ + +/* Enable building of SPL globally */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK + +/* TEXT_BASE for linking the SPL binary */ +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 + +/* Stack size for SPL */ +#define CONFIG_SPL_STACK_SIZE (4 * 1024) +#define CONFIG_SPL_MAX_SIZE (64 * 1024) + +/* MALLOC size for SPL */ +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) + +#define CONFIG_SPL_STACK (&__stack_start) +#define CONFIG_SYS_SPL_MALLOC_START (&__malloc_start) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) + +#define CONFIG_SPL_BSS_START_ADDR 0x08000040 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE + +#define CHUNKSZ_CRC32 (1 * 1024) + +#define CONFIG_CRC32_VERIFY + +/* Linker script for SPL */ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" + +/* Support for common/libcommon.o in SPL binary */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT +/* Support for lib/libgeneric.o in SPL binary */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#endif /* __CONFIG_H */ -- 1.7.7.4

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Re: [U-Boot] [PATCH v2 02/11] S3C24XX: Add core support for Samsung's S3C24XX SoCs
by Marek Vasut 14 Sep '12

14 Sep '12

Dear José Miguel Gonçalves, > Hi Marek, > > On 14-09-2012 19:03, Marek Vasut wrote: > > Dear José Miguel Gonçalves, > > > > It's getting better :) > > Hopefully :-) > > > [...] > > > >> + > >> +typedef ulong(*getfreq) (void); > > > > Is this used? > > In the array declaration bellow... Why, these are only values, no ? > >> +static const getfreq freq_f[] = { > > > > const array const members, no? > > Do you mean I should declare it like this: > > static const getfreq const freq[] = { ... Yes > I don't see the point because an array has no other storage besides it's > elements. Moreover GCC generates the same object code in both ways. Type checking, if you ever decided to write into the array, it'll prevent you from doing so. > >> + get_FCLK, > >> + get_HCLK, > >> + get_PCLK, > >> + get_UCLK, > >> +}; > >> + > >> +static const char freq_c[] = { 'F', 'H', 'P', 'U' }; > > > > Same here. > > > >> +int print_cpuinfo(void) > >> +{ > >> + int i; > >> + char buf[32]; > >> + ulong cpuid; > >> + struct s3c24xx_gpio *const gpio = s3c24xx_get_base_gpio(); > >> + > >> + cpuid = readl(&gpio->gstatus[1]); > >> + printf("CPU: %8s (id %08lX) @ %s MHz\n", s3c24xx_get_cpu_name(), > >> + cpuid, strmhz(buf, get_ARMCLK())); > >> + for (i = 0; i < ARRAY_SIZE(freq_f); i++) > >> + printf("%cCLK: %8s MHz\n", freq_c[i], > >> + strmhz(buf, freq_f[i] ())); > >> + > >> + return 0; > >> +} > > > > [...] > > > >> +ulong get_HCLK(void) > >> +{ > >> + struct s3c2412_sysctl *const sysctl = s3c2412_get_base_sysctl(); > >> + u32 clkdivn; > >> + u16 hclk_div, arm_div; > >> + > >> + clkdivn = readl(&sysctl->clkdivn); > >> + hclk_div = (clkdivn & 0x3) + 1; > >> + arm_div = ((clkdivn >> 3) & 0x1) + 1; > > > > Magic. > > Missed that... I will fix it. > There's more, globally please. [...] > >> diff --git a/include/common.h b/include/common.h > >> index 55025c0..36f0636 100644 > >> --- a/include/common.h > >> +++ b/include/common.h > >> @@ -628,6 +628,7 @@ ulong get_OPB_freq (void); > >> > >> ulong get_PCI_freq (void); > >> #endif > >> #if defined(CONFIG_S3C24X0) || \ > >> > >> + defined(CONFIG_S3C24XX) || \ > >> > >> defined(CONFIG_LH7A40X) || \ > >> defined(CONFIG_S3C6400) || \ > >> defined(CONFIG_EP93XX) > > > > What's this change? Split into different patch please. > > This is related. I need this to export the functions get_FCLK(), > get_HCLK(), get_PCLK() and get_UCLK() used in > arch/arm/cpu/arm926ejs/s3c24xx/cpu_info.c OK > Best regards, > José Gonçalves

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[U-Boot] [PATCH 0/7] [RFC] Driver model, take 1
by Marek Vasut 14 Sep '12

14 Sep '12

I'm submitting hereby the initial code for the driver model. This is a RFC patch, please give it a spin and scream :-) The GPIO api should now use the new approach on the sandbox target. There's also "dm" command, that allows dumping the driver tree. Marek Vasut (5): dm: sandbox: Add necessary linker sections dm: sandbox: Add necessary GD sections dm: REMOVE: sandbox binding experiment dm: gpio: Add draft GPIO core and convert sandbox to use it dm: Add "dm dump" command Pavel Herrmann (2): dm: Add skeleton support for cores and drivers dm: add dummy demo driver and core Makefile | 3 + arch/sandbox/cpu/u-boot.lds | 35 ++- arch/sandbox/include/asm/global_data.h | 9 + arch/sandbox/lib/board.c | 25 ++ common/dm/Makefile | 40 ++++ common/dm/core.c | 150 ++++++++++++ common/dm/debug.c | 106 +++++++++ common/dm/driver.c | 404 ++++++++++++++++++++++++++++++++ common/dm/lists.c | 138 +++++++++++ common/dm/root.c | 103 ++++++++ common/dm/tree.c | 164 +++++++++++++ common/dm/tree.h | 31 +++ drivers/demo/Makefile | 42 ++++ drivers/demo/core.c | 236 +++++++++++++++++++ drivers/demo/demo.c | 67 ++++++ drivers/gpio/Makefile | 2 + drivers/gpio/core.c | 365 +++++++++++++++++++++++++++++ drivers/gpio/sandbox.c | 58 ++++- include/asm-generic/gpio.h | 19 ++ include/configs/sandbox.h | 2 + include/dm/core_numbering.h | 35 +++ include/dm/debug.h | 33 +++ include/dm/demo.h | 37 +++ include/dm/manager.h | 57 +++++ include/dm/options.h | 46 ++++ include/dm/structures.h | 154 ++++++++++++ 26 files changed, 2352 insertions(+), 9 deletions(-) create mode 100644 common/dm/Makefile create mode 100644 common/dm/core.c create mode 100644 common/dm/debug.c create mode 100644 common/dm/driver.c create mode 100644 common/dm/lists.c create mode 100644 common/dm/root.c create mode 100644 common/dm/tree.c create mode 100644 common/dm/tree.h create mode 100644 drivers/demo/Makefile create mode 100644 drivers/demo/core.c create mode 100644 drivers/demo/demo.c create mode 100644 drivers/gpio/core.c create mode 100644 include/dm/core_numbering.h create mode 100644 include/dm/debug.h create mode 100644 include/dm/demo.h create mode 100644 include/dm/manager.h create mode 100644 include/dm/options.h create mode 100644 include/dm/structures.h -- 1.7.10.4

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Re: [U-Boot] Don't get any interrupts once I boot into Linux
by Benoît Thébaudeau 14 Sep '12

14 Sep '12

On Friday, September 14, 2012 7:04:14 PM, Greg Topmiller wrote: > SoC: i.MX51 > Board: mx51evk and our own board that is based on the mx51evk. > Linux: FSL version. Perfect, so we are in exactly the same test conditions, except for mx51evk. Can you try mx51evk with U-Boot 2012.07 and mainline Linux 3.5.3, using the default configs and unpatched code? My debug plan for the next steps is: - Find out if FSL's U-Boot 2009.12 touches TZIC in some way. - Using a JTAG probe in the calibrate_delay() loop, dump TZIC registers to check GPT interrupt security, priority, pending status, FIQ vs. IRQ vs. CPSR and wakeup stuff. - If not pending, then the issue probably comes from the GPT; otherwise, from interrupt propagation. - Use the TZIC registers to trigger the GPT interrupt to see if the handler gets called. Best regards, Benoît

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