September 2012 - U-Boot

[U-Boot] Please pull u-boot-ti/master (updated)
by Tom Rini 25 Sep '12

25 Sep '12

Hello, The following changes since commit d193c1b6eb05041c94ad9aacd8c94189d1dbc5f8: Merge remote-tracking branch 'u-boot-imx/master' (2012-09-21 00:26:19 +0200) are available in the git repository at: git://git.denx.de/u-boot-ti master for you to fetch changes up to 16f452e1cfc3580683752d0d52cfe0dda15125b9: am33xx: Fix fetching of mmc1 bootmode from bootrom for AM33XX (2012-09-21 14:16:03 -0700) ---------------------------------------------------------------- Andreas Bießmann (1): devkit8000: add rootwait to mmcboot option Bastian Ruppert (6): davinci: ea20: reorganisation LCD startup davinci: ea20: the console is always set to the serial line video: cfb_console: logo can be positioned via the splashpos variable video: cfb_console: add function to plot the logo area black da850/omap-l138: davinci_emac: Suppress auto negotiation if needed davinci: ea20: add some configs and default environmet variables Ilya Yanok (4): net/bootp: add VCI support for BOOTP also OMAP: spl: call timer_init() from SPL am335x_evm: enable networking in SPL OMAP: networking support for SPL Joel A Fernandes (1): am33xx: Fix fetching of mmc1 bootmode from bootrom for AM33XX arch/arm/cpu/armv7/omap-common/Makefile | 3 + arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 6 +- arch/arm/cpu/armv7/omap-common/spl.c | 11 ++ arch/arm/cpu/armv7/omap-common/spl_net.c | 52 +++++++++ arch/arm/include/asm/omap_common.h | 13 ++- board/davinci/ea20/ea20.c | 32 ++++-- board/ti/beagle/beagle.c | 2 +- common/Makefile | 4 + common/cmd_nvedit.c | 8 ++ common/env_common.c | 7 +- drivers/net/davinci_emac.c | 3 +- drivers/video/cfb_console.c | 140 +++++++++++++++++++----- include/bootstage.h | 6 +- include/config_uncmd_spl.h | 44 ++++++++ include/configs/am335x_evm.h | 5 +- include/configs/devkit8000.h | 1 + include/configs/ea20.h | 108 +++++++++++------- lib/Makefile | 9 +- lib/hashtable.c | 2 + mkconfig | 1 + net/bootp.c | 27 ++++- spl/Makefile | 3 + 22 files changed, 391 insertions(+), 96 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/spl_net.c create mode 100644 include/config_uncmd_spl.h I've re-built all of ARM and everything builds the same as before these changes. -- Tom

1 1

[U-Boot] Resets on mx6qsabrelite
by Fabio Estevam 25 Sep '12

25 Sep '12

Hi, I am getting reset when using latest U-boot mainline with mx6qsabrelite and loading a kernel. U-Boot 2012.07-00580-g49b3962 (Sep 19 2012 - 09:56:23) CPU: Freescale i.MX6Q rev1.0 at 792 MHz Reset cause: POR Board: MX6Q-Sabre Lite DRAM: 1 GiB WARNING: Caches not enabled MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: FEC Hit any key to stop autoboot: 0 Using FEC device TFTP from server 192.168.1.103; our IP address is 192.168.1.108 Filename 'uImage'. Load address: 0x12000000 Loading: ################################################################# ################################################################# ################################################################# ######################### done Bytes transferred = 3220080 (312270 hex) Using FEC device TFTP from server 192.168.1.103; our IP address is 192.168.1.108 Filename 'imx6q-sabrelite.dtb'. Load address: 0x11ff0000 Loading: # done Bytes transferred = 13715 (3593 hex) ## Booting kernel from Legacy Image at 12000000 ... Image Name: Linux-3.5.3 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3220016 Bytes = 3.1 MiB Load Address: 10008000 Entry Point: 10008000 Verifying Checksum ... OK ## Flattened Device Tree blob at 11ff0000 Booting using the fdt blob at 0x11ff0000 Loading Kernel Image ... OK OK Using Device Tree in place at 11ff0000, end 11ff6592 data abort pc : [<4ff81fd8>] lr : [<4ff75950>] sp : 4fd6fb90 ip : 11ff028c fp : 00000000 r10: 4ffae980 r9 : 00000000 r8 : 4fd6ff60 r7 : 11ff0000 r6 : 00000000 r5 : 00000000 r4 : 4ffae980 r3 : 00000000 r2 : 4ffa2529 r1 : 4fd6fb88 r0 : 11ff0000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... U-Boot 2012.07-00580-g49b3962 (Sep 19 2012 - 09:56:23) Does anyone experience the same issue? Any ideas before I start bisecting this? Thanks, Fabio Estevam

6 20

[U-Boot] [PATCHv2] ARM: Add Altera SOCFPGA Cyclone5
by dinguyen＠altera.com 25 Sep '12

25 Sep '12

From: Dinh Nguyen <dinguyen(a)altera.com> Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Applied on top of trini/WIP/spl-improvements v6 Signed-off-by: Dinh Nguyen <dinguyen(a)altera.com> Signed-off-by: Chin Liang See <clsee(a)altera.com> Signed-off-by: Pavel Machek <pavel(a)denx.de> --- MAINTAINERS | 5 + arch/arm/cpu/armv7/socfpga/Makefile | 51 +++++ arch/arm/cpu/armv7/socfpga/config.mk | 16 ++ arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 77 +++++++ arch/arm/cpu/armv7/socfpga/misc.c | 54 +++++ arch/arm/cpu/armv7/socfpga/spl.c | 48 ++++ arch/arm/cpu/armv7/socfpga/timer.c | 105 +++++++++ arch/arm/cpu/armv7/socfpga/u-boot-spl.lds | 57 +++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 37 +++ .../include/asm/arch-socfpga/socfpga_base_addrs.h | 27 +++ arch/arm/include/asm/arch-socfpga/spl.h | 26 +++ arch/arm/include/asm/arch-socfpga/timer.h | 29 +++ board/altera/socfpga_cyclone5/Makefile | 50 ++++ board/altera/socfpga_cyclone5/socfpga_cyclone5.c | 85 +++++++ boards.cfg | 1 + include/common.h | 2 +- include/configs/socfpga_cyclone5.h | 240 ++++++++++++++++++++ 17 files changed, 909 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/Makefile create mode 100644 arch/arm/cpu/armv7/socfpga/config.mk create mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/socfpga/misc.c create mode 100644 arch/arm/cpu/armv7/socfpga/spl.c create mode 100644 arch/arm/cpu/armv7/socfpga/timer.c create mode 100644 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-socfpga/reset_config.h create mode 100644 arch/arm/include/asm/arch-socfpga/reset_manager.h create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h create mode 100644 arch/arm/include/asm/arch-socfpga/spl.h create mode 100644 arch/arm/include/asm/arch-socfpga/timer.h create mode 100644 board/altera/socfpga_cyclone5/Makefile create mode 100644 board/altera/socfpga_cyclone5/socfpga_cyclone5.c create mode 100644 include/configs/socfpga_cyclone5.h diff --git a/MAINTAINERS b/MAINTAINERS index c5a6f2f..df48dea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -765,6 +765,11 @@ Nagendra T S <nagendra(a)mistralsolutions.com> am3517_crane ARM ARMV7 (AM35x SoC) +Dinh Nguyen <dinguyen(a)altera.com> +Chin Liang See <clsee(a)altera.com> + + socfpga socfpga_cyclone5 + Kyungmin Park <kyungmin.park(a)samsung.com> apollon ARM1136EJS diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile new file mode 100644 index 0000000..376a4bd --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Copyright (C) 2012 Altera Corporation <www.altera.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS-y := misc.o timer.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk new file mode 100644 index 0000000..b72ed1e --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/config.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +ifndef CONFIG_SPL_BUILD +ALL-y += $(obj)u-boot.img +endif diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S new file mode 100644 index 0000000..001b37d --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <config.h> +#include <version.h> + +/* Save the parameter pass in by previous boot loader */ +.global save_boot_params +save_boot_params: + /* save the parameter here */ + + /* + * Setup stack for exception, which is located + * at the end of on-chip RAM. We don't expect exception prior to + * relocation and if that happens, we won't worry -- it will overide + * global data region as the code will goto reset. After relocation, + * this region won't be used by other part of program. + * Hence it is safe. + */ + ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) + ldr r1, =IRQ_STACK_START_IN + str r0, [r1] + + bx lr + + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + + /* Remap */ +#ifdef CONFIG_SPL_BUILD + /* + * SPL : configure the remap (L3 NIC-301 GPV) + * so the on-chip RAM at lower memory instead ROM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x19 + str r1, [r0] +#else + /* + * U-Boot : configure the remap (L3 NIC-301 GPV) + * so the SDRAM at lower memory instead on-chip RAM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x2 + str r1, [r0] + + /* Private components security */ + + /* + * U-Boot : configure private timer, global timer and cpu + * component access as non secure for kernel stage (as required + * by kernel) + */ + mrc p15,4,r0,c15,c0,0 + add r1, r0, #0x54 + ldr r2, [r1] + orr r2, r2, #0xff + orr r2, r2, #0xf00 + str r2, [r1] +#endif /* #ifdef CONFIG_SPL_BUILD */ + mov pc, lr diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c new file mode 100644 index 0000000..15aa18e --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset + */ +void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor. + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + return 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c new file mode 100644 index 0000000..944238b --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <version.h> +#include <image.h> +#include <malloc.h> +#include <asm/arch/reset_manager.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_RAM; +} + +/* + * Board initialization after bss clearance + */ +void spl_board_init(void) +{ + /* init timer for enabling delay function */ + timer_init(); + + /* de-assert reset for peripherals and bridges based on handoff */ + reset_deassert_peripherals_handoff(); + + /* enable console uart printing */ + preloader_console_init(); +} diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c new file mode 100644 index 0000000..1ceb6e9 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; + +/* + * Timer initialization + */ +int timer_init(void) +{ + writel(TIMER_LOAD_VAL, &timer_base->load_val); + writel(TIMER_LOAD_VAL, &timer_base->curr_val); + setbits_le32(&timer_base->ctrl, 0x3); + return 0; +} + +static u32 read_timer(void) +{ + return readl(&timer_base->curr_val); +} + +/* + * Delay x useconds + */ +void __udelay(unsigned long usec) +{ + unsigned long now, last; + /* + * get the tmo value based on timer clock speed + * tmo = delay required / period of timer clock + */ + long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000; + + last = read_timer(); + while (tmo > 0) { + now = read_timer(); + if (last >= now) + /* normal mode (non roll) */ + tmo -= last - now; + else + /* we have overflow of the count down timer */ + tmo -= TIMER_LOAD_VAL - last + now; + last = now; + } +} + +/* + * Get the timer value + */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * Timer : get the time difference + * Unit of tick is based on the CONFIG_SYS_HZ + */ +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + if (gd->lastinc >= now) { + /* normal mode (non roll) */ + /* move stamp forward with absolute diff ticks */ + gd->tbl += gd->lastinc - now; + } else { + /* we have overflow of the count down timer */ + gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now; + } + gd->lastinc = now; + return gd->tbl; +} + +/* + * Reset the timer + */ +void reset_timer(void) +{ + /* capture current decrementer value time */ + gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + /* start "advancing" time stamp from 0 */ + gd->tbl = 0; +} + diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds new file mode 100644 index 0000000..0236daa --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sram + + . = ALIGN(8); + __malloc_start = .; + . = . + CONFIG_SPL_MALLOC_SIZE; + __malloc_end = .; + + . = . + CONFIG_SPL_STACK_SIZE; + . = ALIGN(8); + __stack_start = .; +} diff --git a/arch/arm/include/asm/arch-socfpga/reset_config.h b/arch/arm/include/asm/arch-socfpga/reset_config.h new file mode 100644 index 0000000..e69de29 diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h new file mode 100644 index 0000000..d9d2c1c --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _RESET_MANAGER_H_ +#define _RESET_MANAGER_H_ + +void reset_cpu(ulong addr); +void reset_deassert_peripherals_handoff(void); + +struct socfpga_reset_manager { + u32 padding1; + u32 ctrl; + u32 padding2; + u32 padding3; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; +}; + +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 + +#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h new file mode 100644 index 0000000..f353eb2 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_BASE_ADDRS_H_ +#define _SOCFPGA_BASE_ADDRS_H_ + +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 + +#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h new file mode 100644 index 0000000..c2014c5 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/spl.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2012 Pavel Machek <pavel(a)denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_SPL_H_ +#define _SOCFPGA_SPL_H_ + +/* Symbols from linker script */ +extern void __malloc_start, __malloc_end, __stack_start; + +#define BOOT_DEVICE_RAM 1 + +#endif diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h new file mode 100644 index 0000000..830c94a --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/timer.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_TIMER_H_ +#define _SOCFPGA_TIMER_H_ + +struct socfpga_timer { + u32 load_val; + u32 curr_val; + u32 ctrl; + u32 eoi; + u32 int_stat; +}; + +#endif diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile new file mode 100644 index 0000000..43bbc37 --- /dev/null +++ b/board/altera/socfpga_cyclone5/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := socfpga_cyclone5.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c new file mode 100644 index 0000000..858ab3c --- /dev/null +++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> + +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +void show_boot_progress(int progress) +{ + debug("Boot reached stage %d\n", progress); +} + +/* + * Print CPU information + */ +int print_cpuinfo(void) +{ + puts("CPU : Altera SOCFPGA Platform\n"); + return 0; +} + +/* + * Print Board information + */ +int checkboard(void) +{ + puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + return 0; +} + +/* + * Initialization function which happen at early stage of c code + */ +int board_early_init_f(void) +{ + return 0; +} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + icache_enable(); + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + return 0; +} +#endif + +/* + * DesignWare Ethernet initialization + */ +/* We know all the init functions have been run now */ +int board_eth_init(bd_t *bis) +{ + return 0; +} diff --git a/boards.cfg b/boards.cfg index fdb84ad..1b5c860 100644 --- a/boards.cfg +++ b/boards.cfg @@ -261,6 +261,7 @@ seaboard arm armv7 seaboard nvidia ventana arm armv7 ventana nvidia tegra2 whistler arm armv7 whistler nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 +socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/include/common.h b/include/common.h index 55025c0..e57301f 100644 --- a/include/common.h +++ b/include/common.h @@ -582,7 +582,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); -void reset_cpu (ulong addr); +void reset_cpu (ulong addr) __attribute__((noreturn)); #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd); #ifdef CONFIG_PCI diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h new file mode 100644 index 0000000..bb96274 --- /dev/null +++ b/include/configs/socfpga_cyclone5.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/socfpga_base_addrs.h> + +/* + * High level configuration + */ + +#define CONFIG_ARMV7 +#define CONFIG_L2_OFF +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_USE_IRQ + +#define CONFIG_MISC_INIT_R +#define CONFIG_SINGLE_BOOTLOADER +#define CONFIG_SOCFPGA + +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#define V_NS16550_CLK 1000000 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_TIMER_CLOCK_KHZ 2400 +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Enable early stage initialization at C environment + */ +#define CONFIG_BOARD_EARLY_INIT_F + +/* flat device tree */ +#define CONFIG_OF_LIBFDT +/* skip updating the FDT blob */ +#define CONFIG_FDT_BLOB_SKIP_UPDATE +/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ +#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) + +/* + * Memory allocation (MALLOC) + */ +/* Room required on the stack for the environment data */ +#define CONFIG_ENV_SIZE 1024 +/* Size of DRAM reserved for malloc() use */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +/* Reserving 0x100 space at back of scratch RAM for debug info */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + + +/* + * Command line configuration. + */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +/* FAT file system support */ +#define CONFIG_CMD_FAT + + +/* + * Misc + */ +#define CONFIG_DOS_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif + +/* + * Environment setup + */ + +/* Delay before automatically booting the default image */ +#define CONFIG_BOOTDELAY 3 +/* Enable auto completion of commands using TAB */ +#define CONFIG_AUTO_COMPLETE +/* use "hush" command parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMD_RUN + +#define CONFIG_BOOTCOMMAND "run ramboot" + +/* + * arguments passed to the bootm command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=uImage\0" \ + "fdt_addr=100\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* using environment setting for stdin, stdout, stderr */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* Enable the call to overwrite_console() */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +/* Enable overwrite of previous console environment settings */ +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + + +/* + * Hardware drivers + */ + +/* + * SDRAM Memory Map + */ +/* We have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +/* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* SDRAM memory size */ +#define PHYS_SDRAM_1_SIZE 0x80000000 + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE + +/* + * NS16550 Configuration + */ +#define UART0_BASE SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 UART0_BASE + +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * FLASH + */ +#define CONFIG_SYS_NO_FLASH + +/* + * L4 OSC1 Timer 0 + */ +/* This timer use eosc1 where the clock frequency is fixed + * throughout any condition */ +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS + +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +#define CONFIG_ENV_IS_NOWHERE + +/* + * SPL "Second Program Loader" aka Initial Software + */ + +/* Enable building of SPL globally */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK + +/* TEXT_BASE for linking the SPL binary */ +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 + +/* Stack size for SPL */ +#define CONFIG_SPL_STACK_SIZE (4 * 1024) +#define CONFIG_SPL_MAX_SIZE (64 * 1024) + +/* MALLOC size for SPL */ +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) + +#define CONFIG_SPL_STACK (&__stack_start) +#define CONFIG_SYS_SPL_MALLOC_START (&__malloc_start) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) + +#define CONFIG_SPL_BSS_START_ADDR 0x08000040 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_RAM_DEVICE + +#define CHUNKSZ_CRC32 (1 * 1024) + +#define CONFIG_CRC32_VERIFY + +/* Linker script for SPL */ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" + +/* Support for common/libcommon.o in SPL binary */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT +/* Support for lib/libgeneric.o in SPL binary */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#endif /* __CONFIG_H */ -- 1.7.9.5

5 13

[U-Boot] [PATCH] imx: Use MXC_I2C_CLK in imx i2c driver
by Matthias Weisser 25 Sep '12

25 Sep '12

i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm(a)arcor.de> --- arch/arm/cpu/arm1136/mx31/generic.c | 1 + arch/arm/cpu/arm1136/mx35/generic.c | 1 + arch/arm/cpu/armv7/mx5/clock.c | 1 + arch/arm/cpu/armv7/mx6/clock.c | 1 + arch/arm/include/asm/arch-mx31/clock.h | 1 + arch/arm/include/asm/arch-mx35/clock.h | 1 + arch/arm/include/asm/arch-mx5/clock.h | 1 + arch/arm/include/asm/arch-mx6/clock.h | 1 + drivers/i2c/mxc_i2c.c | 4 ++-- 9 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 93f429c..b9f9b43 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -104,6 +104,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_CSPI_CLK: case MXC_UART_CLK: case MXC_ESDHC_CLK: + case MXC_I2C_CLK: return mx31_get_ipg_clk(); case MXC_IPU_CLK: return mx31_get_hsp_clk(); diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index ef65176..7dc1a8e 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -357,6 +357,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_IPG_CLK: return get_ipg_clk(); case MXC_IPG_PERCLK: + case MXC_I2C_CLK: return get_ipg_per_clk(); case MXC_UART_CLK: return imx_get_uartclk(); diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index c67c3cf..8fa737a 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -482,6 +482,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_IPG_CLK: return get_ipg_clk(); case MXC_IPG_PERCLK: + case MXC_I2C_CLK: return get_ipg_per_clk(); case MXC_UART_CLK: return get_uart_clk(); diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fddb373..44a81b2 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -355,6 +355,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_IPG_CLK: return get_ipg_clk(); case MXC_IPG_PERCLK: + case MXC_I2C_CLK: return get_ipg_per_clk(); case MXC_UART_CLK: return get_uart_clk(); diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 9468b45..1dbb8da 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -46,6 +46,7 @@ enum mxc_clock { MXC_UART_CLK, MXC_IPU_CLK, MXC_ESDHC_CLK, + MXC_I2C_CLK, }; unsigned int mxc_get_clock(enum mxc_clock clk); diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h index eb7458a..2eff08d 100644 --- a/arch/arm/include/asm/arch-mx35/clock.h +++ b/arch/arm/include/asm/arch-mx35/clock.h @@ -48,6 +48,7 @@ enum mxc_clock { MXC_USB_CLK, MXC_CSPI_CLK, MXC_FEC_CLK, + MXC_I2C_CLK, }; enum mxc_main_clock { diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 8d8fa18..21febd8 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -36,6 +36,7 @@ enum mxc_clock { MXC_DDR_CLK, MXC_NFC_CLK, MXC_PERIPH_CLK, + MXC_I2C_CLK, }; u32 imx_get_uartclk(void); diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index c55c18d..2af04f0 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -41,6 +41,7 @@ enum mxc_clock { MXC_ESDHC4_CLK, MXC_SATA_CLK, MXC_NFC_CLK, + MXC_I2C_CLK, }; u32 imx_get_uartclk(void); diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 73d8958..18270b9 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -98,7 +98,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate) #endif /* Divider value calculation */ - i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); + i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); div = (i2c_clk_rate + rate - 1) / rate; if (div < i2c_clk_div[0][0]) clk_div = 0; @@ -142,7 +142,7 @@ unsigned int bus_i2c_get_bus_speed(void *base) for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++) ; - return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0]; + return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0]; } #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) -- 1.7.9.5

3 3

[U-Boot] [PATCH v2 1/2] mx25: add CPU revision 1.2
by Eric Bénard 25 Sep '12

25 Sep '12

tested on a MCIMX257CJM4A which now reports : CPU: Freescale i.MX25 rev1.2 at 399 MHz Signed-off-by: Eric Bénard <eric(a)eukrea.com> Acked-by: Otavio Salvador <otavio(a)ossystems.com.br> --- v2 : rebased against 2012.10-rc1, added Otavio's ack arch/arm/cpu/arm926ejs/mx25/generic.c | 3 +++ arch/arm/include/asm/arch-mx25/imx-regs.h | 1 + 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index a5c15ce..3b7f327 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -140,6 +140,9 @@ u32 get_cpu_rev(void) case 0x01: system_rev |= CHIP_REV_1_1; break; + case 0x02: + system_rev |= CHIP_REV_1_2; + break; default: system_rev |= 0x8000; break; diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 672f9d7..e780296 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -357,5 +357,6 @@ struct aips_regs { #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 +#define CHIP_REV_1_2 0x12 #endif /* _IMX_REGS_H */ -- 1.7.7.6

3 6

[U-Boot] [PATCH v2 1/2] configs: mx6: Add a common config file
by Fabio Estevam 25 Sep '12

25 Sep '12

Add a common mx6 config file that can be shared between some mx6 boards. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - No changes. Newly introduced in this series. include/configs/mx6qsabre_common.h | 179 ++++++++++++++++++++++++++++++++++++ include/configs/mx6qsabresd.h | 170 ++-------------------------------- 2 files changed, 185 insertions(+), 164 deletions(-) create mode 100644 include/configs/mx6qsabre_common.h diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h new file mode 100644 index 0000000..c541691 --- /dev/null +++ b/include/configs/mx6qsabre_common.h @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6Q SabreSD board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MX6QSABRE_COMMON_CONFIG_H +#define __MX6QSABRE_COMMON_CONFIG_H + +#define CONFIG_MX6Q +#define CONFIG_SYS_MX6_HCLK 24000000 +#define CONFIG_SYS_MX6_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#include <asm/arch/imx-regs.h> + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x10800000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +#define CONFIG_OF_LIBFDT + +#define CONFIG_SYS_DCACHE_OFF + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h index a2d2c65..ca91aa5 100644 --- a/include/configs/mx6qsabresd.h +++ b/include/configs/mx6qsabresd.h @@ -14,170 +14,12 @@ * GNU General Public License for more details. */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MX6Q -#define CONFIG_SYS_MX6_HCLK 24000000 -#define CONFIG_SYS_MX6_CLK32 32768 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#ifndef __MX6QSABRESD_CONFIG_H +#define __MX6QSABRESD_CONFIG_H +#include "mx6qsabre_common.h" #define CONFIG_MACH_TYPE 3980 +#define CONFIG_MXC_UART_BASE UART1_BASE +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#include <asm/arch/imx-regs.h> - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MXC_GPIO - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* MMC Configs */ -#define CONFIG_FSL_ESDHC -#define CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_MMC -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_MII -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 - -#define CONFIG_PHYLIB -#define CONFIG_PHY_ATHEROS - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Command definition */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_IMLS - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_LOADADDR 0x10800000 -#define CONFIG_SYS_TEXT_BASE 0x17800000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan ${mmcdev}; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "MX6QSABRESD U-Boot > " -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_CMDLINE_EDITING -#define CONFIG_STACKSIZE (128 * 1024) - -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ENV_SIZE (8 * 1024) - -#define CONFIG_ENV_IS_IN_MMC - -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#define CONFIG_OF_LIBFDT - -#define CONFIG_SYS_DCACHE_OFF - -#ifndef CONFIG_SYS_DCACHE_OFF -#define CONFIG_CMD_CACHE -#endif - -#endif /* __CONFIG_H */ +#endif /* __MX6QSABRESD_CONFIG_H */ -- 1.7.9.5

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[U-Boot] [PATCH] i.MX6: get rid of redundant struct src_regs (dupe of struct src)
by Eric Nelson 25 Sep '12

25 Sep '12

Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> --- arch/arm/cpu/armv7/mx6/soc.c | 2 +- arch/arm/include/asm/arch-mx6/imx-regs.h | 21 --------------------- 2 files changed, 1 insertions(+), 22 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 7380ffe..bc65767 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -146,7 +146,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) void boot_mode_apply(unsigned cfg_val) { unsigned reg; - struct src_regs *psrc = (struct src_regs *)SRC_BASE_ADDR; + struct src *psrc = (struct src *)SRC_BASE_ADDR; writel(cfg_val, &psrc->gpr9); reg = readl(&psrc->gpr10); if (cfg_val) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8834c59..3651cdf 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -448,26 +448,5 @@ struct iomuxc_base_regs { u32 daisy[104]; /* 0x7b0..94c */ }; -struct src_regs { - u32 scr; /* 0x00 */ - u32 sbmr1; /* 0x04 */ - u32 srsr; /* 0x08 */ - u32 reserved1; /* 0x0c */ - u32 reserved2; /* 0x10 */ - u32 sisr; /* 0x14 */ - u32 simr; /* 0x18 */ - u32 sbmr2; /* 0x1c */ - u32 gpr1; /* 0x20 */ - u32 gpr2; /* 0x24 */ - u32 gpr3; /* 0x28 */ - u32 gpr4; /* 0x2c */ - u32 gpr5; /* 0x30 */ - u32 gpr6; /* 0x34 */ - u32 gpr7; /* 0x38 */ - u32 gpr8; /* 0x3c */ - u32 gpr9; /* 0x40 */ - u32 gpr10; /* 0x44 */ -}; - #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ -- 1.7.9

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[U-Boot] SPI for MPC8323
by SETTE AGOSTINO - technolabs 25 Sep '12

25 Sep '12

Hi all, I have a board with MPC8323 and I would like to use the SPI but, as far as I see, the device on this processor is different from the others of the family. The file u-boot/arch/powerpc/include/asm/mpc8xxx_spi.h does not define the CONFIG_MPC8323 for the structure spi8xxx. Are there some patches to apply to the lastest u-boot (2012-10rc1) to use the SPI on the MPC8323? Thanks in advance for your support. Best Regards, Agostino Sette

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[U-Boot] [PATCH 1/3] mmc: sdhci: increase the timeout value for data transfer
by Jaehoon Chung 25 Sep '12

25 Sep '12

Timeout value is tunable. When run read/write operation, sometime returned the timeout error. Because the timeout value is too short. So increased the enough timeout value. (This timeout value is used to prevent the infinite loop.) Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- drivers/mmc/sdhci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 2e3c408..9329874 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -83,7 +83,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, { unsigned int stat, rdy, mask, timeout, block = 0; - timeout = 10000; + timeout = 1000000; rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; do { -- 1.7.4.1

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[U-Boot] [PATCH V3 0/4] common/lcd cleanup
by Nikita Kiryanov 25 Sep '12

25 Sep '12

This patch series attempts to simplify #ifdef complexity in common/lcd.c. It was compile tested on Arm and PowerPC using MAKEALL Changes in V3: - Rebased on latest u-boot-video - Removed volatile qualifiers in patch 3 since the use of volatile is discouraged and it looks like it is safe to remove them. Changes in V2: - Rebased on u-boot-video - patches 2 and 3 of original patchset dropped because I'm not sure what to do about them - simplify lcd_logo: used bitmap_display() to further simplify code - simplify lcd_display_bitmap: fixed pointer increment error - simplify lcd_display_bitmap: change to simplify lcd_logo breaks MCC200 board because it does not #define CONFIG_CMD_BMP. Added a local implementation of bitmap_display(). Nikita Kiryanov (4): common lcd: simplify lcd_logo common lcd: simplify lcd_display common lcd: simplify core functions common lcd: simplify lcd_display_bitmap board/mcc200/lcd.c | 20 +++++++ common/lcd.c | 145 +++++++++++++++++++++++++++------------------------- 2 files changed, 96 insertions(+), 69 deletions(-) -- 1.7.5.4

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