July 2012 - U-Boot

[U-Boot] [PATCH 0/8 V6] EXYNOS5: Enable I2C support
by Rajeshwari Shinde 23 Jul '12

23 Jul '12

This patch set enables I2C support for EXYNOS5. This patchset modifies the s3c24x0 I2C driver to use same for EXYNOS5. Multichannel support has been added to the s3c24x0 I2C driver. s3c24x0_i2c struct has been moved to a common place as it can used by different SOC's. Changes in V2: - Incorporated review comments from Simon Glass. - Aligned the pinmux functionality as per latest comments Changes in V3: - Incorporated review comments from Joonyoung Shim for I2C driver. Changes in V4: - Resolved build error for S3C2410. Changes in V5: - Pinmux setting moved to board file. - Multi Bus I2C offset calculation done based on EXYNOS_I2C_SPACE. - Peripheral id calculation removed from i2c driver. Changes in V6: - Incorporated review comments from Simon Glass. Rajeshwari Shinde (8): EXYNOS: CLK: Add i2c clock EXYNOS: Add I2C base address. EXYNOS5: Define EXYNOS5_I2C_SPACING EXYNOS: PINMUX: Add pinmux support for I2C I2C: Move struct s3c24x0_i2c to a common place. I2C: Modify the I2C driver for EXYNOS5 I2C: Add support for Multi channel CONFIG: SMDK5250: I2C: Enable I2C arch/arm/cpu/armv7/exynos/clock.c | 33 ++++ arch/arm/cpu/armv7/exynos/pinmux.c | 52 +++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/cpu.h | 5 + arch/arm/include/asm/arch-exynos/periph.h | 8 + arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 10 -- board/samsung/smdk5250/smdk5250.c | 23 +++- drivers/i2c/s3c24x0_i2c.c | 220 ++++++++++++++++++--------- drivers/i2c/s3c24x0_i2c.h | 33 ++++ include/configs/smdk5250.h | 8 + 10 files changed, 307 insertions(+), 86 deletions(-) create mode 100644 drivers/i2c/s3c24x0_i2c.h -- 1.7.4.4

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[U-Boot] [STATUS] v2012.07-rc2 is out - release date July 30
by Wolfgang Denk 22 Jul '12

22 Jul '12

Hi everybody, this is to let you know that the v2012.07-rc2 prerelease is out. Please help testing, so we can fix any remaining issues before the release, which I decided to shift by another week, i. e. the new schedule for the release is July 23. Please also note that you can now send pull requests for the "next" branch. Thanks to all. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Alliance: In international politics, the union of two thieves who have their hands so deeply inserted in each other's pocket that they cannot separately plunder a third. - Ambrose Bierce

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[U-Boot] [PATCH 1/2] BC3450 board: change debug code to using debug()
by Wolfgang Denk 22 Jul '12

22 Jul '12

Signed-off-by: Wolfgang Denk <wd(a)denx.de> Cc: Detlev Zundel <dzu(a)denx.de> --- board/bc3450/cmd_bc3450.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c index a9e4902..935769b 100644 --- a/board/bc3450/cmd_bc3450.c +++ b/board/bc3450/cmd_bc3450.c @@ -32,13 +32,6 @@ */ #if defined(CONFIG_CMD_BSP) -#undef DEBUG -#ifdef DEBUG -# define dprintf(fmt,args...) printf(fmt, ##args) -#else -# define dprintf(fmt,args...) -#endif - /* * Definitions for DS1620 chip */ @@ -129,7 +122,7 @@ int sm501_gpio_init (void) static int init_done = 0; if (init_done) { -/* dprintf("sm501_gpio_init: nothing to be done.\n"); */ + debug("sm501_gpio_init: nothing to be done.\n"); return 1; } @@ -162,7 +155,8 @@ int sm501_gpio_init (void) (PWR_OFF | BUZZER | FP_DATA_TRI); init_done = 1; -/* dprintf("sm501_gpio_init: done.\n"); */ + debug("sm501_gpio_init: done.\n"); + return 0; } -- 1.7.10.4

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[U-Boot] [PATCH v3] kirkwood: add support for Iomega iConnect board
by Luka Perkov 22 Jul '12

22 Jul '12

Add support for new board iConnect from Iomega. More information about the device can be found here: http://go.iomega.com/en/products/network-storage-desktop/wireless-data-stat… Signed-off-by: Luka Perkov <uboot(a)lukaperkov.net> Tested-by: Wojciech Dubowik <wojciech.dubowik(a)neratec.com> Tested-by: Tim Fletcher <tim(a)night-shade.org.uk> --- Changes from v2: * verify that kwbimage.cfg is unique * change CONFIG_IDENT_STRING * document kwmpp_config[] MPPs Changes from v1: * remove #ifdef CONFIG_CMD_IDE part from include/configs/iconnect.h (board does not have IDE ports) * add compression defines in include/configs/iconnect.h MAINTAINERS | 1 + board/iomega/iconnect/Makefile | 43 ++++++++++ board/iomega/iconnect/iconnect.c | 107 +++++++++++++++++++++++ board/iomega/iconnect/iconnect.h | 39 +++++++++ board/iomega/iconnect/kwbimage.cfg | 165 ++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/iconnect.h | 129 ++++++++++++++++++++++++++++ 7 files changed, 485 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fd0c65c..9e9d8d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -787,6 +787,7 @@ Linus Walleij <linus.walleij(a)linaro.org> Luka Perkov <uboot(a)lukaperkov.net> ib62x0 ARM926EJS + iconnect ARM926EJS Dave Peverley <dpeverley(a)mpc-data.co.uk> diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile new file mode 100644 index 0000000..f77fcfb --- /dev/null +++ b/board/iomega/iconnect/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := iconnect.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c new file mode 100644 index 0000000..e70cd34 --- /dev/null +++ b/board/iomega/iconnect/iconnect.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "iconnect.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(ICONNECT_OE_VAL_LOW, + ICONNECT_OE_VAL_HIGH, + ICONNECT_OE_LOW, ICONNECT_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, /* Reset signal */ + MPP7_GPO, + MPP8_TW_SDA, /* I2C */ + MPP9_TW_SCK, /* I2C */ + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPIO, /* Reset button */ + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GPIO, /* OTB button */ + MPP36_AUDIO_SPDIFI, + MPP37_AUDIO_SPDIFO, + MPP38_GPIO, + MPP39_TDM_SPI_CS0, + MPP40_TDM_SPI_SCK, + MPP41_GPIO, /* LED brightness */ + MPP42_GPIO, /* LED power (blue) */ + MPP43_GPIO, /* LED power (red) */ + MPP44_GPIO, /* LED USB 1 */ + MPP45_GPIO, /* LED USB 2 */ + MPP46_GPIO, /* LED USB 3 */ + MPP47_GPIO, /* LED USB 4 */ + MPP48_GPIO, /* LED OTB */ + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/iomega/iconnect/iconnect.h b/board/iomega/iconnect/iconnect.h new file mode 100644 index 0000000..2fb3e5e --- /dev/null +++ b/board/iomega/iconnect/iconnect.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __ICONNECT_H +#define __ICONNECT_H + +#define ICONNECT_OE_LOW (~(1 << 7)) +#define ICONNECT_OE_HIGH (~(1 << 10)) +#define ICONNECT_OE_VAL_LOW (0) +#define ICONNECT_OE_VAL_HIGH (1 << 10) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __ICONNECT_H */ diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg new file mode 100644 index 0000000..6c9dfe3 --- /dev/null +++ b/board/iomega/iconnect/kwbimage.cfg @@ -0,0 +1,165 @@ +# +# (C) Copyright 2009-2012 +# Wojciech Dubowik <wojciech.dubowik(a)neratec.com> +# Luka Perkov <uboot(a)lukaperkov.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30, (3120 DDR2 clks refresh rate) +# bit23-14: 0x0, +# bit24: 0x1, enable exit self refresh mode on DDR access +# bit25: 0x1, required +# bit29-26: 0x0, +# bit31-30: 0x1, + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit4: 0x0, addr/cmd in smame cycle +# bit5: 0x0, clk is driven during self refresh, we don't care for APX +# bit6: 0x0, use recommended falling edge of clk for addr/cmd +# bit14: 0x0, input buffer always powered up +# bit18: 0x1, cpu lock transaction enabled +# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 0x3, required +# bit31: 0x0, no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11-8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: 0x0, required + +DATA 0xffd01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width (x8) +# bit3-2: 11, Cs0size (1Gb) +# bit5-4: 00, Cs1width (x8) +# bit7-6: 11, Cs1size (1Gb) +# bit9-8: 00, Cs2width (nonexistent) +# bit11-10: 00, Cs2size (nonexistent) +# bit13-12: 00, Cs3width (nonexistent) +# bit15-14: 00, Cs3size (nonexistent) +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0x0, required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0x0, required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0x0, required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 0x2, BurstLen=2 required +# bit3: 0x0, BurstType=0 required +# bit6-4: 0x4, CL=5 +# bit7: 0x0, TestMode=0 normal +# bit8: 0x0, DLL reset=0 normal +# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit12: 0x0, PD must be zero +# bit31-13: 0x0, required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 0x0, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 0x0, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0x0, required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 0x7, required +# bit3: 0x1, MBUS Burst Chop disabled +# bit6-4: 0x7, required +# bit7: 0x0, +# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0x0, no half clock cycle addition to dataout +# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf, required +# bit31-16: 0x0, required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 0x1, Window enabled +# bit1: 0x0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff, required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above +# bit3-2: 0x1, ODT1 active NEVER! +# bit31-4: 0x0, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +# bit0: 0x1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 2d36d83..6dd8a05 100644 --- a/boards.cfg +++ b/boards.cfg @@ -140,6 +140,7 @@ enbw_cmc arm arm926ejs enbw_cmc enbw calimain arm arm926ejs calimain omicron davinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood +iconnect arm arm926ejs - iomega kirkwood lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h new file mode 100644 index 0000000..2b523c9 --- /dev/null +++ b/include/configs/iconnect.h @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _CONFIG_ICONNECT_H +#define _CONFIG_ICONNECT_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING " Iomega iConnect" + +/* + * High level configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Machine type + */ +#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT + +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "iconnect => " + +/* + * Environment variables configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part rootfs; " \ + "ubifsmount rootfs; " \ + "ubifsload 0x800000 ${kernel}; " \ + "bootm 0x800000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0x80000@0x0(uboot)," \ + "0x20000@0x80000(uboot_env)," \ + "-@0xa0000(rootfs)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/uImage\0" \ + "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" + +/* + * Ethernet driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 11 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + +#endif /* _CONFIG_ICONNECT_H */

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[U-Boot] Pull request #3 : u-boot-arm/master
by Albert ARIBAUD 22 Jul '12

22 Jul '12

Hi Wolfgang, The following changes since commit a21c65115bd95572cc80092a31b0e9ecb8710e9f: ARM: lib: Remove CONFIG_ARCH_CPU_INIT dependency (2012-07-20 14:24:08 +0200) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to f8f09dd40423b7f9ea0f0b810a8f5da9cd580a17: ARM1136: Fix cache range checks (2012-07-21 23:24:25 +0200) ---------------------------------------------------------------- Anatolij Gustschin (1): mx28: Fix elftosb source link in README.mx28_common Ashok (1): mx6: Make pad name macro consistent with the datasheet Benoît Thébaudeau (1): ARM1136: Fix cache range checks Fabio Estevam (1): doc: README.mx28_common: Add missing entry into Contents arch/arm/cpu/arm1136/cpu.c | 6 +++--- arch/arm/include/asm/arch-mx6/mx6x_pins.h | 4 ++-- doc/README.mx28_common | 9 +++++---- 3 files changed, 10 insertions(+), 9 deletions(-) Amicalement, -- Albert.

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[U-Boot] [PATCH] MPC85XX: compile stub cache function
by Stefano Babic 21 Jul '12

21 Jul '12

An empty flush_dcache_range() was added into MPC85xx to work with drivers shared with other architecture. However, it is compiled only if USB is set, but it is required for other drivers (FSL_ESDHC), too. Signed-off-by: Stefano Babic <sbabic(a)denx.de> CC: Andy Fleming <afleming(a)gmail.com> CC: Dirk Behme <dirk.behme(a)de.bosch.com> CC: Marek Vasut <marex(a)denx.de> CC: Wolfgang Denk <wd(a)denx.de> --- arch/powerpc/cpu/mpc85xx/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 7d65aa7..34f6c54 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -131,7 +131,7 @@ COBJS += tlb.o COBJS += traps.o # Stub implementations of cache management functions for USB -COBJS-$(CONFIG_USB_EHCI) += cache.o +COBJS += cache.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -- 1.7.9.5

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[U-Boot] Pull request #2: u-boot-arm/master
by Albert ARIBAUD 21 Jul '12

21 Jul '12

Hi Wolfgang, The following changes since commit a21c65115bd95572cc80092a31b0e9ecb8710e9f: ARM: lib: Remove CONFIG_ARCH_CPU_INIT dependency (2012-07-20 14:24:08 +0200) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to 6b8ac524e7bcfd4853bb4f494e539a63d894a46f: mx6: Make pad name macro consistent with the datasheet (2012-07-20 23:03:28 +0200) ---------------------------------------------------------------- Anatolij Gustschin (1): mx28: Fix elftosb source link in README.mx28_common Ashok (1): mx6: Make pad name macro consistent with the datasheet Fabio Estevam (1): doc: README.mx28_common: Add missing entry into Contents arch/arm/include/asm/arch-mx6/mx6x_pins.h | 4 ++-- doc/README.mx28_common | 9 +++++---- 2 files changed, 7 insertions(+), 6 deletions(-) Amicalement, -- Albert.

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Re: [U-Boot] [PATCH 10/10] dm: Select CONFIG_SPL_GPIO_SUPPORT on OMAP
by Marek Vasut 21 Jul '12

21 Jul '12

Dear Otavio Salvador, > On Sat, Jul 21, 2012 at 12:02 PM, Marek Vasut <marex(a)denx.de> wrote: > > This fixes the breakage with SPL on most OMAP boards after the GPIO > > driver was moved. > > It seems logical this to be merged on the GPIO move patch. Any reason > to not do that? This is rather a fix, maybe it should have been ordered before the GPIO move patch even. Best regards, Marek Vasut

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[U-Boot] [PATCH] tools/env: check flash length before probing
by Mike Frysinger 21 Jul '12

21 Jul '12

If we attempt to probe beyond the end of flash, MEMGETBADBLOCK will fail (as well it should), but we end up erroring out with the distracting: Cannot read bad block mark: Invalid argument Instead of the correct error: Too few good blocks within range Re-order the tests so we check for the end of the flash before probing so we don't probe blocks that don't exist. Reported-by: Mark Bishop <Mark.Bishop(a)cooperindustries.com> Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- tools/env/fw_env.c | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index e292d2b..d0fbbb0 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -712,10 +712,6 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count, /* This only runs once on NOR flash */ while (processed < count) { - rc = flash_bad_block (fd, mtd_type, &blockstart); - if (rc < 0) /* block test failed */ - return -1; - if (blockstart + block_seek + readlen > top_of_range) { /* End of range is reached */ fprintf (stderr, @@ -723,6 +719,10 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count, return -1; } + rc = flash_bad_block (fd, mtd_type, &blockstart); + if (rc < 0) /* block test failed */ + return -1; + if (rc) { /* block is bad */ blockstart += blocklen; continue; @@ -845,15 +845,15 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, /* This only runs once on NOR flash and SPI-dataflash */ while (processed < write_total) { - rc = flash_bad_block (fd, mtd_type, &blockstart); - if (rc < 0) /* block test failed */ - return rc; - if (blockstart + erasesize > top_of_range) { fprintf (stderr, "End of range reached, aborting\n"); return -1; } + rc = flash_bad_block (fd, mtd_type, &blockstart); + if (rc < 0) /* block test failed */ + return rc; + if (rc) { /* block is bad */ blockstart += blocklen; continue; -- 1.7.8.5

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[U-Boot] [PATCH V3 1/2] mtd/spi/spi_flash: support CMD_READ_ID=0x90 case
by Mikhail Kshevetskiy 21 Jul '12

21 Jul '12

current code does not support spi flashes that have 0x90 read_id command, so fix this Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy(a)gmail.com> --- Change for v3: * split SPI flash fixes to separate patch series (series 2/3) Change for v2: * fix checkpatch warnings --- drivers/mtd/spi/spi_flash.c | 66 +++++++++++++++++++++++----------- drivers/mtd/spi/spi_flash_internal.h | 1 + 2 files changed, 47 insertions(+), 20 deletions(-) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index f689cc4..530b7b3 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -306,13 +306,44 @@ static const struct { }; #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) +struct spi_flash *spi_analize_flash_probe(struct spi_slave *spi, + u8 *idcode, size_t idcode_len, u8 *id) +{ + struct spi_flash *flash = NULL; + int i, shift; + u8 *idp; + +#ifdef DEBUG + printf("SF: Got idcodes\n"); + print_buffer(0, idcode, 1, idcode_len, 0); +#endif + + /* count the number of continuation bytes */ + for (shift = 0, idp = idcode; + shift < idcode_len && *idp == 0x7f; + ++shift, ++idp) + continue; + + *id = *idp; + /* search the table for matches in shift and id */ + for (i = 0; i < ARRAY_SIZE(flashes); ++i) + if (flashes[i].shift == shift && flashes[i].idcode == *idp) { + /* we have a match, call probe */ + flash = flashes[i].probe(spi, idp); + if (flash) + break; + } + + return flash; +} + struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode) { struct spi_slave *spi; struct spi_flash *flash = NULL; - int ret, i, shift; - u8 idcode[IDCODE_LEN], *idp; + u8 cmd[4], idcode[IDCODE_LEN], id; + int ret; spi = spi_setup_slave(bus, cs, max_hz, spi_mode); if (!spi) { @@ -331,28 +362,23 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, if (ret) goto err_read_id; -#ifdef DEBUG - printf("SF: Got idcodes\n"); - print_buffer(0, idcode, 1, sizeof(idcode), 0); -#endif + flash = spi_analize_flash_probe(spi, idcode, sizeof(idcode), &id); + if (id == 0xff) { + /* try CMD_READ_ID_NEW command */ + cmd[0] = CMD_READ_ID_NEW; + spi_flash_addr(0x000000, cmd); - /* count the number of continuation bytes */ - for (shift = 0, idp = idcode; - shift < IDCODE_CONT_LEN && *idp == 0x7f; - ++shift, ++idp) - continue; + ret = spi_flash_cmd_read(spi, cmd, sizeof(cmd), + idcode, sizeof(idcode)); + if (ret) + goto err_read_id; - /* search the table for matches in shift and id */ - for (i = 0; i < ARRAY_SIZE(flashes); ++i) - if (flashes[i].shift == shift && flashes[i].idcode == *idp) { - /* we have a match, call probe */ - flash = flashes[i].probe(spi, idp); - if (flash) - break; - } + flash = spi_analize_flash_probe(spi, + idcode, sizeof(idcode), &id); + } if (!flash) { - printf("SF: Unsupported manufacturer %02x\n", *idp); + printf("SF: Unsupported manufacturer %02x\n", id); goto err_manufacturer_probe; } diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 91e036a..b8bd5d5 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -14,6 +14,7 @@ /* Common commands */ #define CMD_READ_ID 0x9f +#define CMD_READ_ID_NEW 0x90 #define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_FAST 0x0b -- 1.7.10.4

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