July 2012 - U-Boot

[U-Boot] [PATCH] powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
by Timur Tabi 25 Jul '12

25 Jul '12

The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows which PCI device tree node to look for. The calls to these macros are using a hard-coded string, but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we should use that. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- We don't update p3060_ids.c because support for that SOC is going away. arch/powerpc/cpu/mpc85xx/p2041_ids.c | 6 +++--- arch/powerpc/cpu/mpc85xx/p3041_ids.c | 8 ++++---- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 6 +++--- arch/powerpc/cpu/mpc85xx/p5020_ids.c | 8 ++++---- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index b99b54d..91d9cac 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -62,9 +62,9 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index c50b442..e46a714 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -62,10 +62,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index a6ea6af..5c287fb 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -52,9 +52,9 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 156), - SET_PCI_LIODN("fsl,p4080-pcie", 1, 193), - SET_PCI_LIODN("fsl,p4080-pcie", 2, 194), - SET_PCI_LIODN("fsl,p4080-pcie", 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_DMA_LIODN(1, 196), SET_DMA_LIODN(2, 197), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index ff57a19..e8c26bf 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -62,10 +62,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), -- 1.7.3.4

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[U-Boot] Binary file header
by Thiago De Quadros 25 Jul '12

25 Jul '12

Hey everyone, I'm trying to find the structure of the binary file header that's created after the u-boot compilation. For example, I already found several informations about the image header structure, and I know that a file u-boot.im is actually the file u-boot.bin with an extra header of 64bytes. However, I didn't find any information about the u-boot.bin header, and I know that it's present, since I can check some data in string format by opening the file with a text editor. I need this information to allow/block some files to be uploaded by my system. Can anyone help me? Thanks in advance, Thiago

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Re: [U-Boot] RFC - PatchTrack Specification (revised)
by Wolfgang Denk 25 Jul '12

25 Jul '12

Dear Andy, In message <004e01cd6a51$57d5ff70$0781fe50$@pont@sdcsystems.com> you wrote: > > I have been and had a look at the specification that you have posted and am > happy to get my hands dirty helping with implement and test this. Thanks in advance. > I know that a good proportion (possibly even all of it) could be implemented > in Python but is there a preference or consensus on what would be the best > language to do it in? Speaking for myself, I have no strict preferences. It may make a lot of sense to look into existing code - much of what we neeed (mail processing, collecting follow-ups, Acks etc.) is already availabe in PatchWork - can we re-use this code instead of re-inventing the wheel? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Computers are not intelligent. They only think they are.

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Re: [U-Boot] Query on S3C2412
by Chander Kashyap 25 Jul '12

25 Jul '12

ccng'g to minkyu On 25 July 2012 17:07, Subash Patel <subash.ramaswamy(a)linaro.org> wrote: > Hi Chander, > > Do you or Minku or someone in SLSI maintain mainline u-boot for old SoC's > like S3C24XX? > Your answer may be useful to Jose. > > Regards, > Subash > > > On 07/25/2012 04:42 PM, José Miguel Gonçalves wrote: >> >> Hi Subash, >> >> That board that I mentioned in the patch was a Silex SX-560: >> >> >> http://www.silexamerica.com/products/embedded_wireless/intelligent_modules/… >> >> You can get the open-source code for it (including u-boot) from here: >> >> http://www.silexamerica.com/opensource/index.html >> >> BTW, I have now switched to this S3C2416 based board: >> >> http://www.armdesigner.com/MINI2416.html >> >> and I'm in the process of updating the u-boot code supplied (a 1.3.4 >> version patched by Samsung for the SMDK2416) to the latest u-boot source >> code. Do you know if Samsung (or someone else) provided a more recent u-boot >> for the SMDK2416 (or any other S3C2416 board)? >> >> Best regards, >> José Gonçalves >> >> >> On 07/25/2012 11:52 AM, Subash Patel wrote: >>> >>> Including even Ben who posted your patch. >>> >>> Regards, >>> Subash >>> >>> On 07/25/2012 04:20 PM, Subash Patel wrote: >>>> >>>> Hi Jose, >>>> >>>> I am from Samsung Electronics, SLSI and work in the open source project >>>> called Linaro. >>>> >>>> I find that you have posted a patch to fix booting s3c2412 based board >>>> recently, and hence assume that you are using that SoC. I am trying to >>>> cleanup some code for these old boards now. Unfortunately my inside- >>>> contacts in company do not have any u-boot for this SoC. Although we >>>> work on the SMDK boards internally, I will try to fix up u-boot which >>>> you may be using for the same. Can you help me to get u-boot, the one >>>> you use if publicly available? >>>> >>>> Regards, >>>> Subash >>> >>> >> > -- with warm regards, Chander Kashyap

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[U-Boot] [PATCH] usb: fallback safely when a configuration descriptor is too large
by Vincent Palatin 25 Jul '12

25 Jul '12

When a USB configuration descriptor was larger than our USB buffer (512 bytes), we were skipping the full descriptor reading but then we were still parsing and using it, triggering memory corruptions. Now in that case, it just skips this device enumeration and displays the appropriate message to the user, so he can fix the buffer if he wants. This bug was triggered by some UVC webcams which have very large configuration descriptors (e.g. a couple of kB) describing all their supported video encodings. Signed-off-by: Vincent Palatin <vpalatin(a)chromium.org> --- common/usb.c | 12 +++++++++--- 1 files changed, 9 insertions(+), 3 deletions(-) diff --git a/common/usb.c b/common/usb.c index 63a11c8..cfa1ad7 100644 --- a/common/usb.c +++ b/common/usb.c @@ -485,8 +485,8 @@ int usb_get_configuration_no(struct usb_device *dev, tmp = le16_to_cpu(config->wTotalLength); if (tmp > USB_BUFSIZ) { - USB_PRINTF("usb_get_configuration_no: failed to get " \ - "descriptor - too long: %d\n", tmp); + printf("usb_get_configuration_no: failed to get " \ + "descriptor - too long: %d\n", tmp); return -1; } @@ -921,7 +921,13 @@ int usb_new_device(struct usb_device *dev) le16_to_cpus(&dev->descriptor.idProduct); le16_to_cpus(&dev->descriptor.bcdDevice); /* only support for one config for now */ - usb_get_configuration_no(dev, &tmpbuf[0], 0); + err = usb_get_configuration_no(dev, &tmpbuf[0], 0); + if (err < 0) { + printf("usb_new_device: Cannot read configuration, " \ + "skipping device %04x:%04x\n", + dev->descriptor.idVendor, dev->descriptor.idProduct); + return -1; + } usb_parse_config(dev, &tmpbuf[0], 0); usb_set_maxpacket(dev); /* we set the default configuration here */ -- 1.7.7.3

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[U-Boot] Unable to power the USB Keyboard on u-boot
by Atul Kumar 24 Jul '12

24 Jul '12

Dear All, I am trying to use "usb keyboard" on u-boot. I am using the u-boot stack which was shared by you. Can you help me to know where problem is going. I am sending some of debug prints which i found on my "Beagle board xM". I have connected usb mouse and usb keyboard on same side of port, here usb mouse lights up but the keyboard does not powers on. Both keyboard and Mouse are from logitech. Please help me to make this up as i have scheduled demo. /***************** usb reset *************************************/ OMAP3 beagleboard.org # usb reset (Re)start USB... USB: Initializing OMAP EHCI OMAP UHH_REVISION 0x10 OMAP EHCI init done Register 1313 NbrPorts 3 USB EHCI 1.00 scanning bus for devices... New Device 0 New Device 1 New Device 2 New Device 3 New Device 4 5 USB Device(s) found USB KBD: found set protocol... USB KBD: found set idle... USB KBD: enable interrupt pipe... USB KBD: found set up device. USB KBD: register. usb_kbd_dev.name- usbkbd before stdio register clone _dev->name-usbkbd,dev->name-usbkbd clone _dev->flag- 80000003 in stdio register,usb_kbd_dev.name- usbkbd After stdio register before strcmp stdin name- serial After strcmp stdin name- serial before over write before console assign before error test scan end scanning bus for storage devices... 0 Storage Device(s) found scanning bus for ethernet devices... Warning: failed to set MAC address 1 Ethernet Device(s) found OMAP3 beagleboard.org # /*****************************************************/ /******************* coninfo **************************/ OMAP3 beagleboard.org # coninfo List of available devices: serial 80000003 SIO stdout stderr usbtty 00000003 .IO usbkbd 80000003 SIO stdin OMAP3 beagleboard.org # ---------------------------------------------------------------> here i am able to switch the console using "setenv stdin usbkbd" but No power on keyboard does not help. /******************************************************/ /**************** usb info ***************************/ OMAP3 beagleboard.org# usb info 1: Hub, USB Revision 2.0 - u-boot EHCI Host Controller - Class: Hub - PacketSize: 64 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 1.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms 2: Hub, USB Revision 2.0 - Class: Hub - PacketSize: 64 Configurations: 1 - Vendor: 0x0424 Product 0x9514 Version 2.0 Configuration: 1 - Interfaces: 1 Self Powered Remote Wakeup 2mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 1 Interval 12ms - Endpoint 1 In Interrupt MaxPacket 1 Interval 12ms 3: Vendor specific, USB Revision 2.0 - Class: Vendor specific - PacketSize: 64 Configurations: 1 - Vendor: 0x0424 Product 0xec00 Version 2.0 Configuration: 1 - Interfaces: 1 Self Powered Remote Wakeup 2mA Interface: 0 - Alternate Setting 0, Endpoints: 3 - Class Vendor specific - Endpoint 1 In Bulk MaxPacket 512 - Endpoint 2 Out Bulk MaxPacket 512 - Endpoint 3 In Interrupt MaxPacket 16 Interval 4ms 4: Human Interface, USB Revision 1.10 - LITEON Technology USB Multimedia Keyboard - Class: (from Interface) Human Interface - PacketSize: 8 Configurations: 1 - Vendor: 0x046d Product 0xc312 Version 1.1 Configuration: 1 - Interfaces: 1 Bus Powered Remote Wakeup 70mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Human Interface, Subclass: Boot Keyboard - Endpoint 1 In Interrupt MaxPacket 8 Interval 24ms 5: Human Interface, USB Revision 2.0 - Logitech USB Optical Mouse - Class: (from Interface) Human Interface - PacketSize: 8 Configurations: 1 - Vendor: 0x046d Product 0xc018 Version 67.1 Configuration: 1 - Interfaces: 1 Bus Powered Remote Wakeup 100mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Human Interface, Subclass: Boot Mouse - Endpoint 1 In Interrupt MaxPacket 5 Interval 10ms OMAP3 beagleboard.org # /****************************************************/ Thanks & Regards Atul Kumar

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[U-Boot] [PATCH 4/4] net: sh_eth: add support for SH7757's GETHER
by Shimoda, Yoshihiro 24 Jul '12

24 Jul '12

SH7757 has 2 ETHERs and 2 GETHERs. This patch supports the SH7757's GETHER. If CONFIG_SH_ETHER_USE_GETHER is defined using SH7757, the driver handles the GETHER. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- drivers/net/sh_eth.h | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 13003ec..3703c55 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -282,8 +282,13 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xfee00000 #elif defined(CONFIG_CPU_SH7757) +#if defined(CONFIG_SH_ETHER_USE_GETHER) +#define SH_ETH_TYPE_GETHER +#define BASE_IO_ADDR 0xfee00000 +#else #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xfef00000 +#endif #elif defined(CONFIG_CPU_SH7724) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xA4600000 @@ -331,7 +336,11 @@ enum DMAC_T_BIT { /* GECMR */ enum GECMR_BIT { +#if defined(CONFIG_CPU_SH7757) + GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, +#else GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, +#endif }; /* EDRRR*/ -- 1.7.1

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[U-Boot] [PATCH 3/4] net: sh_eth: modify the definitions of regsiter
by Shimoda, Yoshihiro 24 Jul '12

24 Jul '12

The previous code had many similar definitions in each CPU. This patch borrows from the sh_eth driver of Linux kernel. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- drivers/net/sh_eth.c | 108 ++++++++--------- drivers/net/sh_eth.h | 331 +++++++++++++++++++++++++++++++------------------- 2 files changed, 258 insertions(+), 181 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 262762d..7b429e8 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -76,8 +76,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len) port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; /* Restart the transmitter if disabled */ - if (!(inl(EDTRR(port)) & EDTRR_TRNS)) - outl(EDTRR_TRNS, EDTRR(port)); + if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) + sh_eth_write(eth, EDTRR_TRNS, EDTRR); /* Wait until packet is transmitted */ timeout = TIMEOUT_CNT; @@ -129,25 +129,24 @@ int sh_eth_recv(struct eth_device *dev) } /* Restart the receiver if disabled */ - if (!(inl(EDRRR(port)) & EDRRR_R)) - outl(EDRRR_R, EDRRR(port)); + if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) + sh_eth_write(eth, EDRRR_R, EDRRR); return len; } static int sh_eth_reset(struct sh_eth_dev *eth) { - int port = eth->port; #if defined(SH_ETH_TYPE_GETHER) int ret = 0, i; /* Start e-dmac transmitter and receiver */ - outl(EDSR_ENALL, EDSR(port)); + sh_eth_write(eth, EDSR_ENALL, EDSR); /* Perform a software reset and wait for it to complete */ - outl(EDMR_SRST, EDMR(port)); + sh_eth_write(eth, EDMR_SRST, EDMR); for (i = 0; i < TIMEOUT_CNT ; i++) { - if (!(inl(EDMR(port)) & EDMR_SRST)) + if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) break; udelay(1000); } @@ -159,9 +158,9 @@ static int sh_eth_reset(struct sh_eth_dev *eth) return ret; #else - outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port)); + sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR); udelay(3000); - outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port)); + sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR); return 0; #endif @@ -207,11 +206,11 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the tx descriptor list. Must use physical addresses */ - outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); + sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); #if defined(SH_ETH_TYPE_GETHER) - outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); - outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); - outl(0x01, TDFFR(port));/* Last discriptor bit */ + sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); + sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); + sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ #endif err: @@ -275,11 +274,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) cur_rx_desc->rd0 |= RD_RDLE; /* Point the controller to the rx descriptor list */ - outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); + sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); #if defined(SH_ETH_TYPE_GETHER) - outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); - outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); - outl(RDFFR_RDLF, RDFFR(port)); + sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); + sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); + sh_eth_write(eth, RDFFR_RDLF, RDFFR); #endif return ret; @@ -364,38 +363,39 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) struct phy_device *phy; /* Configure e-dmac registers */ - outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); - outl(0, EESIPR(port)); - outl(0, TRSCER(port)); - outl(0, TFTR(port)); - outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); - outl(RMCR_RST, RMCR(port)); + sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL, + EDMR); + sh_eth_write(eth, 0, EESIPR); + sh_eth_write(eth, 0, TRSCER); + sh_eth_write(eth, 0, TFTR); + sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); + sh_eth_write(eth, RMCR_RST, RMCR); #if defined(SH_ETH_TYPE_GETHER) - outl(0, RPADIR(port)); + sh_eth_write(eth, 0, RPADIR); #endif - outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); + sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); /* Configure e-mac registers */ - outl(0, ECSIPR(port)); + sh_eth_write(eth, 0, ECSIPR); /* Set Mac address */ val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | dev->enetaddr[2] << 8 | dev->enetaddr[3]; - outl(val, MAHR(port)); + sh_eth_write(eth, val, MAHR); val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; - outl(val, MALR(port)); + sh_eth_write(eth, val, MALR); - outl(RFLR_RFL_MIN, RFLR(port)); + sh_eth_write(eth, RFLR_RFL_MIN, RFLR); #if defined(SH_ETH_TYPE_GETHER) - outl(0, PIPR(port)); - outl(APR_AP, APR(port)); - outl(MPR_MP, MPR(port)); - outl(TPAUSER_TPAUSE, TPAUSER(port)); + sh_eth_write(eth, 0, PIPR); + sh_eth_write(eth, APR_AP, APR); + sh_eth_write(eth, MPR_MP, MPR); + sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); #endif #if defined(CONFIG_CPU_SH7734) - outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port)); + sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); #endif /* Configure phy */ ret = sh_eth_phy_config(eth); @@ -412,34 +412,35 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) if (phy->speed == 100) { printf(SHETHER_NAME ": 100Base/"); #if defined(SH_ETH_TYPE_GETHER) - outl(GECMR_100B, GECMR(port)); + sh_eth_write(eth, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) - outl(1, RTRATE(port)); + sh_eth_write(eth, 1, RTRATE); #elif defined(CONFIG_CPU_SH7724) val = ECMR_RTM; #endif } else if (phy->speed == 10) { printf(SHETHER_NAME ": 10Base/"); #if defined(SH_ETH_TYPE_GETHER) - outl(GECMR_10B, GECMR(port)); + sh_eth_write(eth, GECMR_10B, GECMR); #elif defined(CONFIG_CPU_SH7757) - outl(0, RTRATE(port)); + sh_eth_write(eth, 0, RTRATE); #endif } #if defined(SH_ETH_TYPE_GETHER) else if (phy->speed == 1000) { printf(SHETHER_NAME ": 1000Base/"); - outl(GECMR_1000B, GECMR(port)); + sh_eth_write(eth, GECMR_1000B, GECMR); } #endif /* Check if full duplex mode is supported by the phy */ if (phy->duplex) { printf("Full\n"); - outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); + sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), + ECMR); } else { printf("Half\n"); - outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); + sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); } return ret; @@ -454,12 +455,12 @@ static void sh_eth_start(struct sh_eth_dev *eth) * Enable the e-dmac receiver only. The transmitter will be enabled when * we have something to transmit */ - outl(EDRRR_R, EDRRR(eth->port)); + sh_eth_write(eth, EDRRR_R, EDRRR); } static void sh_eth_stop(struct sh_eth_dev *eth) { - outl(~EDRRR_R, EDRRR(eth->port)); + sh_eth_write(eth, ~EDRRR_R, EDRRR); } int sh_eth_init(struct eth_device *dev, bd_t *bd) @@ -563,9 +564,8 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus) static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; - outl(inl(PIR(port)) | PIR_MMD, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR); return 0; } @@ -573,9 +573,8 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; - outl(inl(PIR(port)) & ~PIR_MMD, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR); return 0; } @@ -583,12 +582,11 @@ static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; if (v) - outl(inl(PIR(port)) | PIR_MDO, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR); else - outl(inl(PIR(port)) & ~PIR_MDO, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR); return 0; } @@ -596,9 +594,8 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; - *v = (inl(PIR(port)) & PIR_MDI) >> 3; + *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3; return 0; } @@ -606,12 +603,11 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; if (v) - outl(inl(PIR(port)) | PIR_MDC, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR); else - outl(inl(PIR(port)) & ~PIR_MDC, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR); return 0; } diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 401ef69..13003ec 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -97,140 +97,196 @@ struct sh_eth_dev { struct sh_eth_info port_info[MAX_PORT_NUM]; }; +/* from linux/drivers/net/ethernet/renesas/sh_eth.h */ +enum { + /* E-DMAC registers */ + EDSR = 0, + EDMR, + EDTRR, + EDRRR, + EESR, + EESIPR, + TDLAR, + TDFAR, + TDFXR, + TDFFR, + RDLAR, + RDFAR, + RDFXR, + RDFFR, + TRSCER, + RMFCR, + TFTR, + FDR, + RMCR, + EDOCR, + TFUCR, + RFOCR, + FCFTR, + RPADIR, + TRIMD, + RBWAR, + TBRAR, + + /* Ether registers */ + ECMR, + ECSR, + ECSIPR, + PIR, + PSR, + RDMLR, + PIPR, + RFLR, + IPGR, + APR, + MPR, + PFTCR, + PFRCR, + RFCR, + RFCF, + TPAUSER, + TPAUSECR, + BCFR, + BCFRR, + GECMR, + BCULR, + MAHR, + MALR, + TROCR, + CDCR, + LCCR, + CNDCR, + CEFCR, + FRECR, + TSFRCR, + TLFRCR, + CERCR, + CEECR, + MAFCR, + RTRATE, + CSMR, + RMII_MII, + + /* This value must be written at last. */ + SH_ETH_MAX_REGISTER_OFFSET, +}; + +static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PIR] = 0x0520, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, +}; + +static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { + [ECMR] = 0x0100, + [RFLR] = 0x0108, + [ECSR] = 0x0110, + [ECSIPR] = 0x0118, + [PIR] = 0x0120, + [PSR] = 0x0128, + [RDMLR] = 0x0140, + [IPGR] = 0x0150, + [APR] = 0x0154, + [MPR] = 0x0158, + [TPAUSER] = 0x0164, + [RFCF] = 0x0160, + [TPAUSECR] = 0x0168, + [BCFRR] = 0x016c, + [MAHR] = 0x01c0, + [MALR] = 0x01c8, + [TROCR] = 0x01d0, + [CDCR] = 0x01d4, + [LCCR] = 0x01d8, + [CNDCR] = 0x01dc, + [CEFCR] = 0x01e4, + [FRECR] = 0x01e8, + [TSFRCR] = 0x01ec, + [TLFRCR] = 0x01f0, + [RFCR] = 0x01f4, + [MAFCR] = 0x01f8, + [RTRATE] = 0x01fc, + + [EDMR] = 0x0000, + [EDTRR] = 0x0008, + [EDRRR] = 0x0010, + [TDLAR] = 0x0018, + [RDLAR] = 0x0020, + [EESR] = 0x0028, + [EESIPR] = 0x0030, + [TRSCER] = 0x0038, + [RMFCR] = 0x0040, + [TFTR] = 0x0048, + [FDR] = 0x0050, + [RMCR] = 0x0058, + [TFUCR] = 0x0064, + [RFOCR] = 0x0068, + [FCFTR] = 0x0070, + [RPADIR] = 0x0078, + [TRIMD] = 0x007c, + [RBWAR] = 0x00c8, + [RDFAR] = 0x00cc, + [TBRAR] = 0x00d4, + [TDFAR] = 0x00d8, +}; + /* Register Address */ -#ifdef CONFIG_CPU_SH7763 +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xfee00000 - -#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) - -#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) -#define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014) -#define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) -#define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c) - -#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) -#define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034) -#define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) -#define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c) - -#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400) -#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408) -#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410) -#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428) -#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430) -#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438) -#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448) -#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450) -#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458) -#define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460) -#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468) -#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500) -#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508) -#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518) -#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520) -#define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c) -#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554) -#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558) -#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564) -#define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0) -#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) -#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) - #elif defined(CONFIG_CPU_SH7757) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xfef00000 - -#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) -#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020) - -#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) -#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008) -#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) -#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028) -#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) -#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) -#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048) -#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050) -#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058) -#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070) -#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100) -#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108) -#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118) -#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120) -#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154) -#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158) -#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164) -#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0) -#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8) -#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc) - #elif defined(CONFIG_CPU_SH7724) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xA4600000 - -#define TDLAR(port) (BASE_IO_ADDR + 0x0018) -#define RDLAR(port) (BASE_IO_ADDR + 0x0020) - -#define EDMR(port) (BASE_IO_ADDR + 0x0000) -#define EDTRR(port) (BASE_IO_ADDR + 0x0008) -#define EDRRR(port) (BASE_IO_ADDR + 0x0010) -#define EESR(port) (BASE_IO_ADDR + 0x0028) -#define EESIPR(port) (BASE_IO_ADDR + 0x0030) -#define TRSCER(port) (BASE_IO_ADDR + 0x0038) -#define TFTR(port) (BASE_IO_ADDR + 0x0048) -#define FDR(port) (BASE_IO_ADDR + 0x0050) -#define RMCR(port) (BASE_IO_ADDR + 0x0058) -#define FCFTR(port) (BASE_IO_ADDR + 0x0070) -#define ECMR(port) (BASE_IO_ADDR + 0x0100) -#define RFLR(port) (BASE_IO_ADDR + 0x0108) -#define ECSIPR(port) (BASE_IO_ADDR + 0x0118) -#define PIR(port) (BASE_IO_ADDR + 0x0120) -#define APR(port) (BASE_IO_ADDR + 0x0154) -#define MPR(port) (BASE_IO_ADDR + 0x0158) -#define TPAUSER(port) (BASE_IO_ADDR + 0x0164) -#define MAHR(port) (BASE_IO_ADDR + 0x01c0) -#define MALR(port) (BASE_IO_ADDR + 0x01c8) - -#elif defined(CONFIG_CPU_SH7734) -#define SH_ETH_TYPE_GETHER -#define BASE_IO_ADDR 0xFEE00000 - -#define EDSR(port) (BASE_IO_ADDR) - -#define TDLAR(port) (BASE_IO_ADDR + 0x0010) -#define TDFAR(port) (BASE_IO_ADDR + 0x0014) -#define TDFXR(port) (BASE_IO_ADDR + 0x0018) -#define TDFFR(port) (BASE_IO_ADDR + 0x001c) -#define RDLAR(port) (BASE_IO_ADDR + 0x0030) -#define RDFAR(port) (BASE_IO_ADDR + 0x0034) -#define RDFXR(port) (BASE_IO_ADDR + 0x0038) -#define RDFFR(port) (BASE_IO_ADDR + 0x003c) - -#define EDMR(port) (BASE_IO_ADDR + 0x0400) -#define EDTRR(port) (BASE_IO_ADDR + 0x0408) -#define EDRRR(port) (BASE_IO_ADDR + 0x0410) -#define EESR(port) (BASE_IO_ADDR + 0x0428) -#define EESIPR(port) (BASE_IO_ADDR + 0x0430) -#define TRSCER(port) (BASE_IO_ADDR + 0x0438) -#define TFTR(port) (BASE_IO_ADDR + 0x0448) -#define FDR(port) (BASE_IO_ADDR + 0x0450) -#define RMCR(port) (BASE_IO_ADDR + 0x0458) -#define RPADIR(port) (BASE_IO_ADDR + 0x0460) -#define FCFTR(port) (BASE_IO_ADDR + 0x0468) -#define ECMR(port) (BASE_IO_ADDR + 0x0500) -#define RFLR(port) (BASE_IO_ADDR + 0x0508) -#define ECSIPR(port) (BASE_IO_ADDR + 0x0518) -#define PIR(port) (BASE_IO_ADDR + 0x0520) -#define PIPR(port) (BASE_IO_ADDR + 0x052c) -#define APR(port) (BASE_IO_ADDR + 0x0554) -#define MPR(port) (BASE_IO_ADDR + 0x0558) -#define TPAUSER(port) (BASE_IO_ADDR + 0x0564) -#define GECMR(port) (BASE_IO_ADDR + 0x05b0) -#define MAHR(port) (BASE_IO_ADDR + 0x05C0) -#define MALR(port) (BASE_IO_ADDR + 0x05C8) -#define RMII_MII(port) (BASE_IO_ADDR + 0x0790) - #endif /* @@ -506,3 +562,28 @@ enum RPADIR_BIT { enum FIFO_SIZE_BIT { FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, }; + +static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, + int enum_index) +{ +#if defined(SH_ETH_TYPE_GETHER) + const u16 *reg_offset = sh_eth_offset_gigabit; +#elif defined(SH_ETH_TYPE_ETHER) + const u16 *reg_offset = sh_eth_offset_fast_sh4; +#else +#error +#endif + return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; +} + +static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data, + int enum_index) +{ + outl(data, sh_eth_reg_addr(eth, enum_index)); +} + +static inline unsigned long sh_eth_read(struct sh_eth_dev *eth, + int enum_index) +{ + return inl(sh_eth_reg_addr(eth, enum_index)); +} -- 1.7.1

3 2

[U-Boot] [PATCH 2/4] net: sh_eth: add SH_ETH_TYPE_ condition
by Shimoda, Yoshihiro 24 Jul '12

24 Jul '12

At the moment, the driver supports the following CPUs: - GETHER (Gigabit Ethernet) : SH7763, SH7734 - ETHER (Fast Ethernet) : SH7724, SH7757 And the driver had the following "#if": #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) #if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) - Those are for GETHER #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) - This is for ETHER So, for clean up the code, this patch adds SH_ETH_TYPE_GETHER and SH_ETH_TYPE_ETHER. And then, the patch modifies the above "#if". Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- drivers/net/sh_eth.c | 22 +++++++++------------- drivers/net/sh_eth.h | 43 +++++++++++++++++++++++-------------------- 2 files changed, 32 insertions(+), 33 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 1825059..262762d 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -1,5 +1,5 @@ /* - * sh_eth.c - Driver for Renesas SH7763's ethernet controler. + * sh_eth.c - Driver for Renesas ethernet controler. * * Copyright (C) 2008, 2011 Renesas Solutions Corp. * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu @@ -138,7 +138,7 @@ int sh_eth_recv(struct eth_device *dev) static int sh_eth_reset(struct sh_eth_dev *eth) { int port = eth->port; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) int ret = 0, i; /* Start e-dmac transmitter and receiver */ @@ -208,7 +208,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the tx descriptor list. Must use physical addresses */ outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); outl(0x01, TDFFR(port));/* Last discriptor bit */ @@ -276,7 +276,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the rx descriptor list */ outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); outl(RDFFR_RDLF, RDFFR(port)); @@ -370,7 +370,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) outl(0, TFTR(port)); outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); outl(RMCR_RST, RMCR(port)); -#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) +#if defined(SH_ETH_TYPE_GETHER) outl(0, RPADIR(port)); #endif outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); @@ -387,14 +387,10 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) outl(val, MALR(port)); outl(RFLR_RFL_MIN, RFLR(port)); -#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) +#if defined(SH_ETH_TYPE_GETHER) outl(0, PIPR(port)); -#endif -#if !defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757) outl(APR_AP, APR(port)); outl(MPR_MP, MPR(port)); -#endif -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) outl(TPAUSER_TPAUSE, TPAUSER(port)); #endif @@ -415,7 +411,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) /* Set the transfer speed */ if (phy->speed == 100) { printf(SHETHER_NAME ": 100Base/"); -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) outl(GECMR_100B, GECMR(port)); #elif defined(CONFIG_CPU_SH7757) outl(1, RTRATE(port)); @@ -424,13 +420,13 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) #endif } else if (phy->speed == 10) { printf(SHETHER_NAME ": 10Base/"); -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) outl(GECMR_10B, GECMR(port)); #elif defined(CONFIG_CPU_SH7757) outl(0, RTRATE(port)); #endif } -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) else if (phy->speed == 1000) { printf(SHETHER_NAME ": 1000Base/"); outl(GECMR_1000B, GECMR(port)); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 5276be3..401ef69 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -99,6 +99,7 @@ struct sh_eth_dev { /* Register Address */ #ifdef CONFIG_CPU_SH7763 +#define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xfee00000 #define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) @@ -137,6 +138,7 @@ struct sh_eth_dev { #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) #elif defined(CONFIG_CPU_SH7757) +#define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xfef00000 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) @@ -164,6 +166,7 @@ struct sh_eth_dev { #define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc) #elif defined(CONFIG_CPU_SH7724) +#define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xA4600000 #define TDLAR(port) (BASE_IO_ADDR + 0x0018) @@ -190,6 +193,7 @@ struct sh_eth_dev { #define MALR(port) (BASE_IO_ADDR + 0x01c8) #elif defined(CONFIG_CPU_SH7734) +#define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xFEE00000 #define EDSR(port) (BASE_IO_ADDR) @@ -233,7 +237,7 @@ struct sh_eth_dev { * Register's bits * Copy from Linux driver source code */ -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) /* EDSR */ enum EDSR_BIT { EDSR_ENT = 0x01, EDSR_ENR = 0x02, @@ -244,15 +248,15 @@ enum EDSR_BIT { /* EDMR */ enum DMAC_M_BIT { EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) EDMR_SRST = 0x03, /* Receive/Send reset */ EMDR_DESC_R = 0x30, /* Descriptor reserve size */ EDMR_EL = 0x40, /* Litte endian */ -#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724) +#elif defined(SH_ETH_TYPE_ETHER) EDMR_SRST = 0x01, EMDR_DESC_R = 0x30, /* Descriptor reserve size */ EDMR_EL = 0x40, /* Litte endian */ -#else /* CONFIG_CPU_SH7763 */ +#else EDMR_SRST = 0x01, #endif }; @@ -262,7 +266,7 @@ enum DMAC_M_BIT { /* EDTRR */ enum DMAC_T_BIT { -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) EDTRR_TRNS = 0x03, #else EDTRR_TRNS = 0x01, @@ -302,7 +306,7 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; /* EESR */ enum EESR_BIT { -#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) +#if defined(SH_ETH_TYPE_ETHER) EESR_TWB = 0x40000000, #else EESR_TWB = 0xC0000000, @@ -312,14 +316,14 @@ enum EESR_BIT { #endif EESR_TABT = 0x04000000, EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, -#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) +#if defined(SH_ETH_TYPE_ETHER) EESR_ADE = 0x00800000, #endif EESR_ECI = 0x00400000, EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, -#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) +#if defined(SH_ETH_TYPE_ETHER) EESR_CND = 0x00000800, #endif EESR_DLC = 0x00000400, @@ -331,7 +335,7 @@ enum EESR_BIT { }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) # define TX_CHECK (EESR_TC1 | EESR_FTC) # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) @@ -391,8 +395,7 @@ enum FCFTR_BIT { /* Transfer descriptor bit */ enum TD_STS_BIT { -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \ - || defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) TD_TACT = 0x80000000, #else TD_TACT = 0x7fffffff, @@ -408,7 +411,7 @@ enum TD_STS_BIT { enum RECV_RST_BIT { RMCR_RST = 0x01, }; /* ECMR */ enum FELIC_MODE_BIT { -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, ECMR_RZPF = 0x00100000, #endif @@ -423,10 +426,10 @@ enum FELIC_MODE_BIT { }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ ECMR_TXF | ECMR_MCT) -#elif CONFIG_CPU_SH7724 || CONFIG_CPU_SH7757 +#elif defined(SH_ETH_TYPE_ETHER) #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) #else #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) @@ -434,14 +437,14 @@ enum FELIC_MODE_BIT { /* ECSR */ enum ECSR_STATUS_BIT { -#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) +#if defined(SH_ETH_TYPE_ETHER) ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, #endif ECSR_LCHNG = 0x04, ECSR_MPD = 0x02, ECSR_ICD = 0x01, }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) #else # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ @@ -450,10 +453,10 @@ enum ECSR_STATUS_BIT { /* ECSIPR */ enum ECSIPR_STATUS_MASK_BIT { -#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) +#if defined(SH_ETH_TYPE_ETHER) ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, -#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#elif defined(SH_ETY_TYPE_GETHER) ECSIPR_PSRTOIP = 0x10, ECSIPR_PHYIP = 0x08, #endif @@ -462,7 +465,7 @@ enum ECSIPR_STATUS_MASK_BIT { ECSIPR_ICDIP = 0x01, }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) #else # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ @@ -493,7 +496,7 @@ enum RPADIR_BIT { RPADIR_PADR = 0x0003f, }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) # define RPADIR_INIT (0x00) #else # define RPADIR_INIT (RPADIR_PADS1) -- 1.7.1

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[U-Boot] [PATCH 1/4] net: sh_eth: clean up for the SH7757's code
by Shimoda, Yoshihiro 24 Jul '12

24 Jul '12

The SH7757's ETHER can work using the SH7724's setting. So, the patch modifies it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- drivers/net/sh_eth.c | 9 +-------- drivers/net/sh_eth.h | 14 ++------------ 2 files changed, 3 insertions(+), 20 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index bb57e4d..1825059 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -376,12 +376,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); /* Configure e-mac registers */ -#if defined(CONFIG_CPU_SH7757) - outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | - ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port)); -#else outl(0, ECSIPR(port)); -#endif /* Set Mac address */ val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | @@ -395,14 +390,12 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) #if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) outl(0, PIPR(port)); #endif -#if !defined(CONFIG_CPU_SH7724) +#if !defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757) outl(APR_AP, APR(port)); outl(MPR_MP, MPR(port)); #endif #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) outl(TPAUSER_TPAUSE, TPAUSER(port)); -#elif defined(CONFIG_CPU_SH7757) - outl(TPAUSER_UNLIMITED, TPAUSER(port)); #endif #if defined(CONFIG_CPU_SH7734) diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 50f4b69..5276be3 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -319,7 +319,7 @@ enum EESR_BIT { EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, -#if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757) +#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) EESR_CND = 0x00000800, #endif EESR_DLC = 0x00000400, @@ -426,9 +426,7 @@ enum FELIC_MODE_BIT { #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ ECMR_TXF | ECMR_MCT) -#elif CONFIG_CPU_SH7757 -#define ECMR_CHG_DM (ECMR_ZPF) -#elif CONFIG_CPU_SH7724 +#elif CONFIG_CPU_SH7724 || CONFIG_CPU_SH7757 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) #else #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) @@ -473,20 +471,12 @@ enum ECSIPR_STATUS_MASK_BIT { /* APR */ enum APR_BIT { -#ifdef CONFIG_CPU_SH7757 - APR_AP = 0x00000001, -#else APR_AP = 0x00000004, -#endif }; /* MPR */ enum MPR_BIT { -#ifdef CONFIG_CPU_SH7757 - MPR_MP = 0x00000001, -#else MPR_MP = 0x00000006, -#endif }; /* TRSCER */ -- 1.7.1

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