July 2012 - U-Boot

[U-Boot] [PATCH] powerpc/sgmii: To support PHY link state auto detect in SGMII mode
by Jia Hongtao 09 Aug '12

09 Aug '12

PHYs on SGMII riser card are used in SGMII mode with different external IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type under ethernet node should be updated. Otherwise the PHY interrupt can not be handled therefor PHY link state change can not be auto detected. For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed but it's still be kept to guarantee the sgmii mode could work with old device tree. Signed-off-by: Li Yang <leoli(a)freescale.com> Signed-off-by: Jia Hongtao <B38951(a)freescale.com> --- board/freescale/common/sgmii_riser.c | 57 +++++++++++++++++++++++++++++----- 1 files changed, 49 insertions(+), 8 deletions(-) diff --git a/board/freescale/common/sgmii_riser.c b/board/freescale/common/sgmii_riser.c index 4f40a1d..5c3c593 100644 --- a/board/freescale/common/sgmii_riser.c +++ b/board/freescale/common/sgmii_riser.c @@ -17,6 +17,7 @@ #include <net.h> #include <libfdt.h> #include <tsec.h> +#include <fdt_support.h> void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num) { @@ -31,6 +32,7 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt) { struct eth_device *dev; int node; + int mdio_node; int i = -1; int etsec_num = 0; @@ -40,16 +42,38 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt) while ((dev = eth_get_dev_by_index(++i)) != NULL) { struct tsec_private *priv; + int phy_node; int enet_node; + uint32_t ph; + char sgmii_phy[16]; char enet[16]; const u32 *phyh; - int phynode; const char *model; const char *path; if (!strstr(dev->name, "eTSEC")) continue; + priv = dev->priv; + if (!(priv->flags & TSEC_SGMII)) { + etsec_num++; + continue; + } + + mdio_node = fdt_node_offset_by_compatible(fdt, -1, + "fsl,gianfar-mdio"); + if (mdio_node < 0) + return; + + sprintf(sgmii_phy, "sgmii-phy@%d", etsec_num); + phy_node = fdt_subnode_offset(fdt, mdio_node, sgmii_phy); + if (phy_node > 0) { + fdt_increase_size(fdt, 32); + ph = fdt_create_phandle(fdt, phy_node); + if (!ph) + continue; + } + sprintf(enet, "ethernet%d", etsec_num++); path = fdt_getprop(fdt, node, enet, NULL); if (!path) { @@ -74,15 +98,32 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt) if (!strstr(model, "TSEC")) continue; - phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL); - if (!phyh) - continue; + if (phy_node < 0) { + /* + * This part is only for old device tree without + * sgmii_phy nodes. It's kept just for compatible + * reason. Soon to be deprecated if all device tree + * get updated. + */ + phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL); + if (!phyh) + continue; - phynode = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyh)); + phy_node = fdt_node_offset_by_phandle(fdt, + fdt32_to_cpu(*phyh)); - priv = dev->priv; + priv = dev->priv; - if (priv->flags & TSEC_SGMII) - fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr); + if (priv->flags & TSEC_SGMII) + fdt_setprop_cell(fdt, phy_node, "reg", + priv->phyaddr); + } else { + fdt_setprop(fdt, enet_node, "phy-handle", &ph, + sizeof(ph)); + fdt_setprop_string(fdt, enet_node, + "phy-connection-type", + phy_string_for_interface( + PHY_INTERFACE_MODE_SGMII)); + } } } -- 1.7.5.1

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[U-Boot] [PATCH] powerpc/85xx: improve definition of BR_PHYS_ADDR macro
by Timur Tabi 09 Aug '12

09 Aug '12

The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro definition, so callers had to supply their own parenthesis. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- arch/powerpc/include/asm/fsl_lbc.h | 6 +++--- include/configs/MPC8536DS.h | 9 ++++----- include/configs/MPC8548CDS.h | 3 +-- include/configs/MPC8572DS.h | 9 ++++----- include/configs/P1022DS.h | 2 +- include/configs/P2020DS.h | 9 +++++---- include/configs/corenet_ds.h | 2 +- include/configs/p1_p2_rdb_pc.h | 4 ++-- 8 files changed, 21 insertions(+), 23 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 2a23d84..d1def75 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -82,10 +82,10 @@ void lbc_sdram_init(void); /* Convert an address into the right format for the BR registers */ #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC) -#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ - ((x & 0x300000000ULL) >> 19))) +#define BR_PHYS_ADDR(x) \ + ((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19))) #else -#define BR_PHYS_ADDR(x) (x & 0xffff8000) +#define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000) #endif /* OR - Option Registers diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index c26cb63..4a6b64f 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -217,8 +217,7 @@ #endif #define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ - | BR_PS_16 | BR_V) + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM \ @@ -380,14 +379,14 @@ #endif #define CONFIG_SYS_BR4_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR5_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -395,7 +394,7 @@ #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_BR6_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ + (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1a6ba69..82bbb3e 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -189,8 +189,7 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_SYS_BR0_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \ - | BR_PS_16 | BR_V) + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) #define CONFIG_SYS_BR1_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index d7910e1..eeb9a8d 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -205,8 +205,7 @@ #define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ - | BR_PS_16 | BR_V) + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) @@ -376,20 +375,20 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #endif -#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 70d751d..ae7c90e 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -118,7 +118,7 @@ #endif #define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index f0eb029..5a25b56 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -239,7 +239,8 @@ #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) @@ -342,20 +343,20 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 8ed37a5..976dfe9 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -211,7 +211,7 @@ #endif #define CONFIG_SYS_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ | BR_PS_16 | BR_V) #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9f2951d..f6677c8 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -357,7 +357,7 @@ #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 @@ -401,7 +401,7 @@ #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS)) \ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ -- 1.7.3.4

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[U-Boot] [PATCH] powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
by Timur Tabi 09 Aug '12

09 Aug '12

In order for indirect mode on the PIXIS to work properly, both chip selects need to be set to GPCM mode, otherwise writes to the chip select base addresses will not actually post to the local bus -- they'll go to the NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM mode before switching to indirect mode. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- board/freescale/p1022ds/diu.c | 82 +++++++++++++++++++++++++++++++++++++---- 1 files changed, 74 insertions(+), 8 deletions(-) diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c index d5428ea..898f4c7 100644 --- a/board/freescale/p1022ds/diu.c +++ b/board/freescale/p1022ds/diu.c @@ -63,6 +63,8 @@ static u8 px_brdcfg0; static u32 pmuxcr; static void *lbc_lcs0_ba; static void *lbc_lcs1_ba; +static u32 old_br0, old_or0, old_br1, old_or1; +static u32 new_br0, new_or0, new_br1, new_or1; void diu_set_pixel_clock(unsigned int pixclock) { @@ -88,10 +90,63 @@ int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) const char *name; u32 pixel_format; u8 temp; + phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */ - /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */ - lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000); - lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000); + /* + * Indirect mode requires both BR0 and BR1 to be set to "GPCM", + * otherwise writes to these addresses won't actually appear on the + * local bus, and so the PIXIS won't see them. + * + * In FCM mode, writes go to the NAND controller, which does not pass + * them to the localbus directly. So we force BR0 and BR1 into GPCM + * mode, since we don't care about what's behind the localbus any + * more. However, we save those registers first, so that we can + * restore them when necessary. + */ + new_br0 = old_br0 = get_lbc_br(0); + new_br1 = old_br1 = get_lbc_br(1); + new_or0 = old_or0 = get_lbc_or(0); + new_or1 = old_or1 = get_lbc_or(1); + + /* + * Use the existing BRx/ORx values if it's already GPCM. Otherwise, + * force the values to simple 32KB GPCM windows with the most + * conservative timing. + */ + if ((old_br0 & BR_MSEL) != BR_MS_GPCM) { + new_br0 = (get_lbc_br(0) & BR_BA) | BR_V; + new_or0 = OR_AM_32KB | 0xFF7; + set_lbc_br(0, new_br0); + set_lbc_or(0, new_or0); + } + if ((old_br1 & BR_MSEL) != BR_MS_GPCM) { + new_br1 = (get_lbc_br(1) & BR_BA) | BR_V; + new_or1 = OR_AM_32KB | 0xFF7; + set_lbc_br(1, new_br1); + set_lbc_or(1, new_or1); + } + + /* + * Determine the physical addresses for Chip Selects 0 and 1. The + * BR0/BR1 registers contain the truncated physical addresses for the + * chip selects, mapped via the localbus LAW. Since the BRx registers + * only contain the lower 32 bits of the address, we have to determine + * the upper 4 bits some other way. The proper way is to scan the LAW + * table looking for a matching localbus address. Instead, we cheat. + * We know that the upper bits are 0 for 32-bit addressing, or 0xF for + * 36-bit addressing. + */ +#ifdef CONFIG_PHYS_64BIT + phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA); + phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA); +#else + phys0 = old_br0 & old_or0 & BR_BA; + phys1 = old_br1 & old_or1 & BR_BA; +#endif + + /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */ + lbc_lcs0_ba = map_physmem(phys0, 1, 0); + lbc_lcs1_ba = map_physmem(phys1, 1, 0); pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | @@ -134,6 +189,7 @@ int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); px_brdcfg0 = in_8(lbc_lcs1_ba); out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); + in_8(lbc_lcs1_ba); /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); @@ -168,12 +224,10 @@ static int set_mux_to_lbc(void) * In DIU mode, the PIXIS can only be accessed indirectly * since we can't read/write the LBC directly. */ - /* Set the board mux to LBC. This will disable the display. */ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); - px_brdcfg0 = in_8(lbc_lcs1_ba); - out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK - | PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC); + out_8(lbc_lcs1_ba, px_brdcfg0); + in_8(lbc_lcs1_ba); /* Disable indirect PIXIS mode */ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr)); @@ -184,6 +238,12 @@ static int set_mux_to_lbc(void) PMUXCR_ELBCDIU_NOR16); in_be32(&gur->pmuxcr); + /* Restore the BR0 and BR1 settings */ + set_lbc_br(0, old_br0); + set_lbc_or(0, old_or0); + set_lbc_br(1, old_br1); + set_lbc_or(1, old_or1); + return 1; } @@ -199,12 +259,18 @@ static void set_mux_to_diu(void) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + /* Set BR0 and BR1 to GPCM mode */ + set_lbc_br(0, new_br0); + set_lbc_or(0, new_or0); + set_lbc_br(1, new_br1); + set_lbc_or(1, new_or1); + /* Enable indirect PIXIS mode */ setbits_8(&pixis->csr, PX_CTL_ALTACC); /* Set the board mux to DIU. This will enable the display. */ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); - out_8(lbc_lcs1_ba, px_brdcfg0); + out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); in_8(lbc_lcs1_ba); /* Set the chip mux to DIU mode. */ -- 1.7.3.4

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[U-Boot] [PATCH 1/2] powerpc/p1022ds: add support for SPI and SD boot
by Timur Tabi 09 Aug '12

09 Aug '12

From: Matthew McClintock <msm(a)freescale.com> Add TLB mappings, board target options, and configuration items need for SPI/SD boot. Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit address flash, therefore, when SDHC/ESPI booting and access to eLBC, the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to 00b for them. Configure the PX_BRDCFG0[0~1] to 10b which is connected to SPI devices as SPI_CS(0:3)_B. Signed-off-by: Matthew McClintock <msm(a)freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang(a)freescale.com> Signed-off-by: Jiang Yutang <b14898(a)freescale.com> --- board/freescale/p1022ds/p1022ds.c | 4 +++ board/freescale/p1022ds/tlb.c | 14 ++++++++++ boards.cfg | 4 +++ include/configs/P1022DS.h | 51 ++++++++++++++++++++++++++++++++++-- 4 files changed, 70 insertions(+), 3 deletions(-) diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index aca30f3..37531b4 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -39,6 +39,10 @@ int board_early_init_f(void) /* Set pmuxcr to allow both i2c1 and i2c2 */ setbits_be32(&gur->pmuxcr, 0x1000); +#ifdef CONFIG_SYS_RAMBOOT + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); +#endif /* Read back the register to synchronize the write. */ in_be32(&gur->pmuxcr); diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index e620112..71e71f7 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -71,6 +71,20 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1), + +#ifdef CONFIG_SYS_RAMBOOT + /* *I*G - eSDHC/eSPI/NAND boot */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), + + /* map the second 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_1G, 1), +#endif +# }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 7194e08..42e5ae0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -699,6 +699,10 @@ P1021RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freesca P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale +P1022DS_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:SPIFLASH +P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SPIFLASH +P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD +P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SDCARD P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 89e8663..ea1d19f 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -18,6 +18,22 @@ #define CONFIG_PHYS_64BIT #endif +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ @@ -397,11 +413,40 @@ /* * Environment */ +#ifdef CONFIG_SYS_RAMBOOT +#ifdef CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_NAND_U_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_LOADS_ECHO #define CONFIG_SYS_LOADS_BAUD_CHANGE -- 1.7.3.4

4 7

[U-Boot] [PATCH 1/2] powerpc/mpc85xx: Ignore E bit for BSC9130/1
by York Sun 09 Aug '12

09 Aug '12

Commit 48f6a5c34 removed E bit. BSC9130/1 were left out due to patch apply timing. Remove them now. Signed-off-by: York Sun <yorksun(a)freescale.com> --- arch/powerpc/include/asm/processor.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 489dd61..7bd3789 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1104,9 +1104,7 @@ #define SVR_8641D 0x809001 #define SVR_9130 0x860001 -#define SVR_9130_E 0x860801 #define SVR_9131 0x860000 -#define SVR_9131_E 0x860800 #define SVR_Unknown 0xFFFFFF -- 1.7.0.4

2 2

[U-Boot] Regarding BDI2000 connection problem with MPC8280 based board
by Thirumalesha N 08 Aug '12

08 Aug '12

Dear sir, I'm trying BDI 2000 to connect MPC8280 Board buts its showing time out and i'm new to BDI 2000. Please suggest me on this regards. Regards Thiru N

2 3

[U-Boot] [PATCH] at91: Add support for taskit AT91SAM9G20 boards.
by Markus Hubig 08 Aug '12

08 Aug '12

This adds support for the AT91SAM9G20 boards by taskit GmbH. Both boards, Stamp9G20 and PortuxG20, are integrated in one file. PortuxG20 is basically a SBC built around the Stamp9G20. Signed-off-by: Markus Hubig <mhubig(a)imko.de> Cc: Andreas Bießmann <andreas.devel(a)googlemail.com> --- board/taskit/stamp9g20/Makefile | 52 ++++++++ board/taskit/stamp9g20/stamp9g20.c | 199 +++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/stamp9g20.h | 225 ++++++++++++++++++++++++++++++++++++ 4 files changed, 478 insertions(+), 0 deletions(-) create mode 100644 board/taskit/stamp9g20/Makefile create mode 100644 board/taskit/stamp9g20/stamp9g20.c create mode 100644 include/configs/stamp9g20.h diff --git a/board/taskit/stamp9g20/Makefile b/board/taskit/stamp9g20/Makefile new file mode 100644 index 0000000..e99bfaa --- /dev/null +++ b/board/taskit/stamp9g20/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian(a)popies.net> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2012 +# Markus Hubig <mhubig(a)imko.de> +# IMKO GmbH <www.imko.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += stamp9g20.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c new file mode 100644 index 0000000..b87de51 --- /dev/null +++ b/board/taskit/stamp9g20/stamp9g20.c @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian(a)popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * Achim Ehrlich <aehrlich(a)taskit.de> + * taskit GmbH <www.taskit.de> + * + * (C) Copyright 2012- + * Markus Hubig <mhubig(a)imko.de> + * IMKO GmbH <www.imko.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> + +#ifdef CONFIG_MACB +# include <net.h> +# include <netdev.h> +#endif /* CONFIG_MACB */ + +DECLARE_GLOBAL_DATA_PTR; + +static void stamp9G20_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} + +#ifdef CONFIG_MACB +static void stamp9G20_macb_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; + + /* Enable MACB Chip, this is the enable PIN on Stamp Adaptor*/ + at91_set_gpio_output(AT91_PIN_PA26, 0); + + /* Enable EMAC clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PA17) => PHY normal mode (not Test mode) + * ERX0 (PA14) => PHY ADDR0 + * ERX1 (PA15) => PHY ADDR1 + * ERX2 (PA25) => PHY ADDR2 + * ERX3 (PA26) => PHY ADDR3 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA18) | + pin_to_mask(AT91_PIN_PA28), + &pioa->pudr); + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA18) | + pin_to_mask(AT91_PIN_PA28), + &pioa->puer); + + /* Initialize EMAC=MACB hardware */ + at91_macb_hw_init(); +} +#endif /* CONFIG_MACB */ + +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), &pmc->pcer); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_PORTUXG20 + gd->bd->bi_arch_number = MACH_TYPE_PORTUXG20; +#else + gd->bd->bi_arch_number = MACH_TYPE_STAMP9G20; +#endif + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + at91_set_gpio_output(AT91_PIN_PC9, 1); + at91_set_gpio_output(AT91_PIN_PC5, 1); + + at91_seriald_hw_init(); + stamp9G20_nand_hw_init(); +#ifdef CONFIG_MACB + stamp9G20_macb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_MACB +void reset_phy(void) +{ + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); + return rc; +} +#endif /* CONFIG_MACB */ diff --git a/boards.cfg b/boards.cfg index 2d36d83..9c5ba09 100644 --- a/boards.cfg +++ b/boards.cfg @@ -120,6 +120,8 @@ cpu9G20_nand_128M arm arm926ejs cpu9260 eukrea pm9261 arm arm926ejs pm9261 ronetix at91 pm9261:AT91SAM9261 pm9263 arm arm926ejs pm9263 ronetix at91 pm9263:AT91SAM9263 pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45 +portuxg20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20,CONFIG_PORTUXG20 +stamp9g20 arm arm926ejs stamp9g20 taskit at91 stamp9g20:AT91SAM9G20 cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx da830evm arm arm926ejs da8xxevm davinci davinci da850_am18xxevm arm arm926ejs da8xxevm davinci davinci da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h new file mode 100644 index 0000000..7783a2f --- /dev/null +++ b/include/configs/stamp9g20.h @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian(a)popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2010 + * Achim Ehrlich <aehrlich(a)taskit.de> + * taskit GmbH <www.taskit.de> + * + * (C) Copyright 2012 + * Markus Hubig <mhubig(a)imko.de> + * IMKO GmbH <www.imko.de> + * + * Configuation settings for the stamp9g20 CPU module. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include <asm/hardware.h> + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot + * program. Since the linker has to swallow that define, we must use a pure + * hex number here! + */ +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ +#define CONFIG_SYS_HZ 1000 /* 1ms resolution */ + +/* Misc CPU related settings */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#undef CONFIG_USE_IRQ /* we don't need IRQ stuff */ +#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */ +#define CONFIG_INITRD_TAG /* pass initrd param to kernel */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_BOARD_EARLY_INIT_f /* call board_early_init_f() */ +#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */ + +/* + * SDRAM: 1 bank, 64 MB, base address 0x20000000 + * Already initialized before u-boot gets started. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE (64 * (1024 << 10)) + +/* + * Perform a SDRAM Memtest from the start of SDRAM + * till the beginning of the U-Boot position in RAM. + */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above that + * address while providing maximum stack area below. + */ +#define CONFIG_STACKSIZE (32 * 1024) /* 32k regular stack size */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) + +/* NAND flash settings */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO /* enable the GPIO features */ +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600} +#define CONFIG_USART3 /* USART 3 is used as DBGU */ + +/* Ethernet configuration */ +#define CONFIG_MACB /* initialize the ethernet port */ + +#ifdef CONFIG_MACB +# define CONFIG_RMII /* use reduced MII inteface */ +# define CONFIG_RESET_PHY_R /* call reset_phy() after reloc. */ +# define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ +#endif /* CONFIG_MACB */ + +/* USB configuration */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 + +/* BOOTP options */ +#ifdef CONFIG_MACB +# define CONFIG_BOOTP_BOOTFILESIZE +# define CONFIG_BOOTP_BOOTPATH +# define CONFIG_BOOTP_GATEWAY +# define CONFIG_BOOTP_HOSTNAME +#endif /* CONFIG_MACB */ + +/* General Boot Parameter */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +/* + * RAM Memory address where to put the + * Linux Kernel bevor starting. + */ +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +/* + * The NAND Flash partitions: + * ========================================== + * 0x0000000-0x001ffff -> 128k, bootstrap + * 0x0020000-0x005ffff -> 256k, u-boot + * 0x0060000-0x007ffff -> 128k, env1 + * 0x0080000-0x009ffff -> 128k, env2 (backup) + * 0x0100000-0x03fffff -> 2M, kernel + * 0x0400000-0x8000000 -> 124M, RootFS + */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (128 + 256 << 10) +#define CONFIG_ENV_OFFSET_REDUND (128 + 256 + 128 << 10) +#define CONFIG_ENV_SIZE (128 << 10) + +/* + * Predefined environment variables. + * Usefull to define some easy to use boot commands. + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + \ + "basicargs=console=ttyS0,115200 mem=64M\0" \ + \ + "mtdparts=mtdparts=atmel_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro," \ + "128k(env2)ro,2M(linux),-(root)rw\0" \ + \ + "sdboot=setenv bootargs ${basicargs} ${mtdparts} " \ + "root=/dev/mmcblk0p1 rootdelay=1; " \ + "nand read 0x22000000 0xA0000 0x200000; " \ + "bootm 22000000\0" \ + \ + "flashboot=setenv bootargs ${basicargs} ${mtdparts} " \ + "root=/dev/mtdblock5 rootfstype=jffs2; " \ + "nand read 0x22000000 0xA0000 0x200000; " \ + "bootm 22000000\0" \ + \ + "nfsboot=setenv bootargs ${basicargs} ${mtdparts} " \ + "root=/dev/nfs ip=dhcp " \ + "nfsroot=${serverip}:/srv/nfs/rootfs; dhcp; " \ + "bootm\0" + +/* Command line & features configuration */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT + +#ifdef CONFIG_MACB +# define CONFIG_CMD_PING +# define CONFIG_CMD_DHCP +#endif /* CONFIG_MACB */ + +#ifdef CONFIG_USE_IRQ +# error CONFIG_USE_IRQ not supported +#endif + +#endif -- 1.7.7

2 18

[U-Boot] [PATCH v2] i.MX28: bug fixes in PMU configuration code
by Stathis Voukelatos 07 Aug '12

07 Aug '12

Fixed some typos in the i.MX28 PMU code that sets up the VDDD and VDDIO power rails. In addition the VDDD and VDDIO brownout offset values should be divided by a step size before being programmed to the corresponding registers. Signed-off-by: Stathis Voukelatos <stathis.voukelatos(a)linn.co.uk> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Marek Vasut <marek.vasut(a)gmail.com> --- Changes for v2: - White space cleanup arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git arch/arm/cpu/arm926ejs/mx28/spl_power_init.c arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 4b09b0c..cc71af8 100644 --- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -716,7 +716,7 @@ int mx28_get_vddio_power_source_off(void) tmp = readl(&power_regs->hw_power_vddioctrl); if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { return 1; } } @@ -724,7 +724,7 @@ int mx28_get_vddio_power_source_off(void) if (!(readl(&power_regs->hw_power_5vctrl) & POWER_5VCTRL_ENABLE_DCDC)) { if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { return 1; } } @@ -772,7 +772,7 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) uint32_t cur_target, diff, bo_int = 0; uint32_t powered_by_linreg = 0; - new_brownout = new_target - new_brownout; + new_brownout = (new_target - new_brownout + 25) / 50; cur_target = readl(&power_regs->hw_power_vddioctrl); cur_target &= POWER_VDDIOCTRL_TRG_MASK; @@ -858,8 +858,8 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) } clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDDCTRL_BO_OFFSET_MASK, - new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); + POWER_VDDIOCTRL_BO_OFFSET_MASK, + new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET); } void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) @@ -869,7 +869,7 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) uint32_t cur_target, diff, bo_int = 0; uint32_t powered_by_linreg = 0; - new_brownout = new_target - new_brownout; + new_brownout = (new_target - new_brownout + 12) / 25; cur_target = readl(&power_regs->hw_power_vdddctrl); cur_target &= POWER_VDDDCTRL_TRG_MASK; -- 1.7.2.5 Stathis Voukelatos Senior Software Engineer Linn Products Ltd. Glasgow Road Eaglesham, Glasgow G76 0EQ, UK Tel: +44 (0)141 3035191 Email: stathis.voukelatos(a)linn.co.uk

4 5

[U-Boot] pull request for u-boot-tegra/master
by Tom Warren 07 Aug '12

07 Aug '12

Albert, Please pull u-boot-tegra/master into ARM master. Thanks! The following changes since commit f8f09dd40423b7f9ea0f0b810a8f5da9cd580a17: Benoît Thébaudeau (1): ARM1136: Fix cache range checks are available in the git repository at: git://git.denx.de/u-boot-tegra master Allen Martin (15): tegra20: rename tegra2 -> tegra20 tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-common tegra20: rename CONFIG_MACH_TEGRA_GENERIC tegra20: tec: add tegra20-common-post.h tegra20: make board mkdir commands unconditional mkconfig: add support for SPL CPU ARM: Fix arm720t SPL build tegra20: remove timer_init from SPL build ARM: add tegra20 support to arm720t tegra20: add u-boot-*-tegra.bin targets tegra20: move SDRAM param save to later in boot tegra20: enable SPL for tegra20 boards arm: enable libgcc build for SPL spl: fix SPL build of private libgcc tegra20: Remove armv4t build flags MAINTAINERS | 18 ++-- Makefile | 26 ++++ arch/arm/cpu/arm720t/cpu.c | 2 + arch/arm/cpu/arm720t/interrupts.c | 5 + arch/arm/cpu/arm720t/start.S | 19 +++- .../cpu/{armv7/tegra2 => arm720t/tegra20}/Makefile | 28 +--- .../arch-tegra2 => cpu/arm720t/tegra20}/board.h | 11 +- .../{armv7/tegra2 => arm720t/tegra20}/config.mk | 12 -- .../{armv7/tegra2/ap20.c => arm720t/tegra20/cpu.c} | 148 ++------------------ .../ap20.h => cpu/arm720t/tegra20/cpu.h} | 15 +-- arch/arm/cpu/arm720t/tegra20/spl.c | 132 +++++++++++++++++ arch/arm/cpu/armv7/start.S | 2 - arch/arm/cpu/armv7/{tegra2 => tegra20}/Makefile | 15 +-- .../cpu/armv7/{tegra2 => tegra20}/cmd_enterrcm.c | 4 +- arch/arm/cpu/armv7/{tegra2 => tegra20}/config.mk | 12 -- arch/arm/cpu/armv7/{tegra2 => tegra20}/usb.c | 2 +- .../cpu/{armv7/tegra2 => tegra20-common}/Makefile | 29 ++--- arch/arm/cpu/tegra20-common/ap20.c | 131 +++++++++++++++++ .../cpu/{armv7/tegra2 => tegra20-common}/board.c | 39 ++---- .../cpu/{armv7/tegra2 => tegra20-common}/clock.c | 10 +- .../cpu/{armv7/tegra2 => tegra20-common}/crypto.c | 0 .../cpu/{armv7/tegra2 => tegra20-common}/crypto.h | 0 .../arm/cpu/{armv7/tegra2 => tegra20-common}/emc.c | 2 +- .../cpu/{armv7/tegra2 => tegra20-common}/funcmux.c | 2 +- .../tegra2 => tegra20-common}/lowlevel_init.S | 0 .../cpu/{armv7/tegra2 => tegra20-common}/pinmux.c | 4 +- .../arm/cpu/{armv7/tegra2 => tegra20-common}/pmu.c | 2 +- .../{armv7/tegra2 => tegra20-common}/sys_info.c | 2 +- .../cpu/{armv7/tegra2 => tegra20-common}/timer.c | 2 +- .../{armv7/tegra2 => tegra20-common}/warmboot.c | 18 ++-- .../tegra2 => tegra20-common}/warmboot_avp.c | 4 +- .../tegra2 => tegra20-common}/warmboot_avp.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/ap20.h | 4 +- .../asm/{arch-tegra2 => arch-tegra20}/apb_misc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/board.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/clk_rst.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/clock.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/emc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/flow.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/funcmux.h | 2 +- .../asm/{arch-tegra2 => arch-tegra20}/fuse.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/gp_padctrl.h | 2 +- .../asm/{arch-tegra2 => arch-tegra20}/gpio.h | 2 +- arch/arm/include/asm/arch-tegra20/hardware.h | 29 ++++ .../asm/{arch-tegra2 => arch-tegra20}/mmc.h | 8 +- .../asm/{arch-tegra2 => arch-tegra20}/pinmux.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/pmc.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/pmu.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/scu.h | 0 .../{arch-tegra2 => arch-tegra20}/sdram_param.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/sys_proto.h | 4 +- .../tegra2.h => arch-tegra20/tegra20.h} | 18 ++-- .../asm/{arch-tegra2 => arch-tegra20}/tegra_i2c.h | 2 +- .../asm/{arch-tegra2 => arch-tegra20}/tegra_spi.h | 4 +- .../asm/{arch-tegra2 => arch-tegra20}/timer.h | 6 +- .../uart-spi-switch.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/uart.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/usb.h | 0 .../asm/{arch-tegra2 => arch-tegra20}/warmboot.h | 0 arch/arm/lib/Makefile | 2 +- board/avionic-design/common/tamonten.c | 4 +- .../dts/{tegra2-medcom.dts => tegra20-medcom.dts} | 0 .../dts/{tegra2-plutux.dts => tegra20-plutux.dts} | 0 .../dts/{tegra2-tec.dts => tegra20-tec.dts} | 0 board/avionic-design/medcom/Makefile | 2 - board/avionic-design/plutux/Makefile | 2 - board/avionic-design/tec/Makefile | 2 - .../dts/{tegra2-paz00.dts => tegra20-paz00.dts} | 0 board/compal/paz00/Makefile | 2 - board/compal/paz00/paz00.c | 6 +- ...{tegra2-trimslice.dts => tegra20-trimslice.dts} | 0 board/compulab/trimslice/Makefile | 2 - board/compulab/trimslice/trimslice.c | 6 +- board/nvidia/common/board.c | 17 ++- board/nvidia/common/emc.c | 2 +- board/nvidia/common/uart-spi-switch.c | 2 +- .../{tegra2-harmony.dts => tegra20-harmony.dts} | 2 +- .../{tegra2-seaboard.dts => tegra20-seaboard.dts} | 0 .../{tegra2-ventana.dts => tegra20-ventana.dts} | 2 +- .../{tegra2-whistler.dts => tegra20-whistler.dts} | 2 +- board/nvidia/harmony/harmony.c | 6 +- board/nvidia/seaboard/seaboard.c | 6 +- board/nvidia/whistler/whistler.c | 6 +- boards.cfg | 23 ++-- doc/README.SPL | 12 ++ drivers/gpio/tegra_gpio.c | 12 +- drivers/i2c/tegra_i2c.c | 12 +- drivers/input/Makefile | 2 +- drivers/mmc/tegra_mmc.c | 32 ++-- drivers/mmc/tegra_mmc.h | 12 +- drivers/spi/tegra_spi.c | 10 +- include/configs/harmony.h | 14 +- include/configs/medcom.h | 12 +- include/configs/paz00.h | 12 +- include/configs/plutux.h | 12 +- include/configs/seaboard.h | 20 ++-- include/configs/tec.h | 12 +- ...{tegra2-common-post.h => tegra20-common-post.h} | 73 +++++++++- .../configs/{tegra2-common.h => tegra20-common.h} | 44 ++++-- include/configs/trimslice.h | 14 +- include/configs/ventana.h | 12 +- include/configs/whistler.h | 14 +- include/fdtdec.h | 12 +- include/serial.h | 2 +- mkconfig | 24 ++- spl/Makefile | 10 ++ 106 files changed, 742 insertions(+), 510 deletions(-) copy arch/arm/cpu/{armv7/tegra2 => arm720t/tegra20}/Makefile (56%) copy arch/arm/{include/asm/arch-tegra2 => cpu/arm720t/tegra20}/board.h (81%) copy arch/arm/cpu/{armv7/tegra2 => arm720t/tegra20}/config.mk (73%) rename arch/arm/cpu/{armv7/tegra2/ap20.c => arm720t/tegra20/cpu.c} (63%) copy arch/arm/{include/asm/arch-tegra2/ap20.h => cpu/arm720t/tegra20/cpu.h} (93%) create mode 100644 arch/arm/cpu/arm720t/tegra20/spl.c copy arch/arm/cpu/armv7/{tegra2 => tegra20}/Makefile (69%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/cmd_enterrcm.c (94%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/config.mk (74%) rename arch/arm/cpu/armv7/{tegra2 => tegra20}/usb.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/Makefile (66%) create mode 100644 arch/arm/cpu/tegra20-common/ap20.c rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/board.c (79%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/clock.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/crypto.c (100%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/crypto.h (100%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/emc.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/funcmux.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/lowlevel_init.S (100%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/pinmux.c (99%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/pmu.c (98%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/sys_info.c (98%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/timer.c (98%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/warmboot.c (95%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/warmboot_avp.c (98%) rename arch/arm/cpu/{armv7/tegra2 => tegra20-common}/warmboot_avp.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/ap20.h (98%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/apb_misc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/board.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/clk_rst.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/clock.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/emc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/flow.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/funcmux.h (97%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/fuse.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/gp_padctrl.h (98%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/gpio.h (99%) create mode 100644 arch/arm/include/asm/arch-tegra20/hardware.h rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/mmc.h (84%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/pinmux.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/pmc.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/pmu.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/scu.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/sdram_param.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/sys_proto.h (93%) rename arch/arm/include/asm/{arch-tegra2/tegra2.h => arch-tegra20/tegra20.h} (87%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/tegra_i2c.h (99%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/tegra_spi.h (96%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/timer.h (92%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/uart-spi-switch.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/uart.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/usb.h (100%) rename arch/arm/include/asm/{arch-tegra2 => arch-tegra20}/warmboot.h (100%) rename board/avionic-design/dts/{tegra2-medcom.dts => tegra20-medcom.dts} (100%) rename board/avionic-design/dts/{tegra2-plutux.dts => tegra20-plutux.dts} (100%) rename board/avionic-design/dts/{tegra2-tec.dts => tegra20-tec.dts} (100%) rename board/compal/dts/{tegra2-paz00.dts => tegra20-paz00.dts} (100%) rename board/compulab/dts/{tegra2-trimslice.dts => tegra20-trimslice.dts} (100%) rename board/nvidia/dts/{tegra2-harmony.dts => tegra20-harmony.dts} (92%) rename board/nvidia/dts/{tegra2-seaboard.dts => tegra20-seaboard.dts} (100%) rename board/nvidia/dts/{tegra2-ventana.dts => tegra20-ventana.dts} (92%) rename board/nvidia/dts/{tegra2-whistler.dts => tegra20-whistler.dts} (94%) rename include/configs/{tegra2-common-post.h => tegra20-common-post.h} (74%) rename include/configs/{tegra2-common.h => tegra20-common.h} (84%)

4 11

[U-Boot] [PATCH 1/4] MX28: Fix up the MMC driver DMA mode
by Marek Vasut 07 Aug '12

07 Aug '12

The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1. Also, it was using SSP0 DMA channel for all SSP devices. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <festevam(a)freescale.com> Cc: Andy Fleming <afleming(a)freescale.com> --- drivers/mmc/mxsmmc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) NOTE: This series is for -next! diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 4187a94..a637db3 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -79,6 +79,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) uint32_t *data_ptr; #else uint32_t cache_data_count; + int dmach; #endif debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); @@ -201,6 +202,8 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) timeout = MXSMMC_MAX_TIMEOUT; #ifdef CONFIG_MXS_MMC_DMA + writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); + if (data_count % ARCH_DMA_MINALIGN) cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN); else @@ -222,8 +225,9 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) (data_count << MXS_DMA_DESC_BYTES_OFFSET); - mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc); - if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) { + dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id; + mxs_dma_desc_append(dmach, priv->desc); + if (mxs_dma_go(dmach)) { printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev); return COMM_ERR; } @@ -234,6 +238,8 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) (uint32_t)(priv->desc->cmd.address + cache_data_count)); } #else + writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); + if (data->flags & MMC_DATA_READ) { data_ptr = (uint32_t *)data->dest; while (data_count && --timeout) { -- 1.7.10

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