June 2012 - U-Boot

[U-Boot] [PATCH] omap: am33xx: enable gpio support
by Steve Sakoman 21 Jun '12

21 Jun '12

This patch uses the code in omap-common to support gpio modules 1-3 on am33xx based boards. It adds base address and register definitions, enables clocks to the modules, and enables building the common gpio code for CONFIG_AM33XX as well as CONFIG_OMAP Signed-off-by: Steve Sakoman <steve(a)sakoman.com> --- arch/arm/cpu/armv7/am33xx/board.c | 10 ++++++++++ arch/arm/cpu/armv7/am33xx/clock.c | 15 +++++++++++++++ arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/include/asm/arch-am33xx/cpu.h | 19 +++++++++++++++++++ arch/arm/include/asm/arch-am33xx/gpio.h | 29 +++++++++++++++++++++++++++++ 5 files changed, 74 insertions(+), 1 deletions(-) create mode 100644 arch/arm/include/asm/arch-am33xx/gpio.h diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 6b7a494..47ed63c 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -22,6 +22,7 @@ #include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> +#include <asm/arch/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/common_def.h> #include <asm/io.h> @@ -33,6 +34,15 @@ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; +static const struct gpio_bank gpio_bank_am33xx[4] = { + { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; + /* UART Defines */ #ifdef CONFIG_SPL_BUILD #define UART_RESET (0x1 << 1) diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 57bec98..c1fb75c 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -123,6 +123,21 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmper->i2c1clkctrl); while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN) ; + + /* gpio1 module */ + writel(PRCM_MOD_EN, &cmper->gpio1clkctrl); + while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN) + ; + + /* gpio2 module */ + writel(PRCM_MOD_EN, &cmper->gpio2clkctrl); + while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN) + ; + + /* gpio3 module */ + writel(PRCM_MOD_EN, &cmper->gpio3clkctrl); + while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN) + ; } static void mpu_pll_config(void) diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 2a6625f..1394c3f 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -29,7 +29,7 @@ SOBJS := reset.o COBJS := timer.o COBJS += utils.o -ifdef CONFIG_OMAP +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP),) COBJS += gpio.o endif diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index be903fb..6ef82dc 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -234,6 +234,25 @@ struct ctrl_stat { unsigned int statusreg; /* ofset 0x40 */ }; +/* AM33XX GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x002c +#define OMAP_GPIO_IRQSTATUS2 0x0030 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + void init_timer(void); #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h new file mode 100644 index 0000000..1a211e9 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -0,0 +1,29 @@ +/* + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _GPIO_AM33xx_H +#define _GPIO_AM33xx_H + +#include <asm/omap_gpio.h> + +#define AM33XX_GPIO0_BASE 0x44E07000 +#define AM33XX_GPIO1_BASE 0x4804C000 +#define AM33XX_GPIO2_BASE 0x481AC000 +#define AM33XX_GPIO3_BASE 0x481AE000 + +#endif /* _GPIO_AM33xx_H */ -- 1.7.1

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[U-Boot] [PATCH 0/3] omap: fix bugs in automatic emif setup code
by Steve Sakoman 21 Jun '12

21 Jun '12

While bringing up a new OMAP4 based board I encountered a number of issues when attempting to use the automatic emif setup code. This patch series fixes a compile error and two runtime issues. Tested on the new custom OMAP4 board and Pandaboard Steve Sakoman (3): omap: fix compile error in emif-common.c omap: emif: deal with rams that return duplicate mr data on all byte lanes omap: emif: fix bug in manufacturer code test arch/arm/cpu/armv7/omap-common/emif-common.c | 9 +++++++-- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 6 +++--- 2 files changed, 10 insertions(+), 5 deletions(-)

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[U-Boot] [PATCH] ARM: OMAP4+: Move external phy initialisations to arch specific place.
by R Sricharan 21 Jun '12

21 Jun '12

The external phy is present in the case OMAP5 soc is currently configured in emif-common.c. This results in having dummy structures for those Socs which do not have a external phy. So by having a weak function in emif-common and overriding it in OMAP5, avoids the use of dummy structures. Signed-off-by: R Sricharan <r.sricharan(a)ti.com> --- arch/arm/cpu/armv7/omap-common/emif-common.c | 32 +++++--------------------- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 3 -- arch/arm/cpu/armv7/omap5/sdram.c | 31 +++++++++++++++++++++++++ arch/arm/include/asm/emif.h | 2 + 4 files changed, 39 insertions(+), 29 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index db509c9..278162d 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -31,6 +31,7 @@ #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> #include <asm/utils.h> +#include <linux/compiler.h> inline u32 emif_num(u32 base) { @@ -114,9 +115,6 @@ static void do_lpddr2_init(u32 base, u32 cs) static void lpddr2_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 *ext_phy_ctrl_base = 0; - u32 *emif_ext_phy_ctrl_base = 0; - u32 i = 0; /* Not NVM */ clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); @@ -134,29 +132,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) writel(regs->sdram_config_init, &emif->emif_sdram_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); - emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); - - if (omap_revision() >= OMAP5430_ES1_0) { - /* Configure external phy control timing registers */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { - writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); - } - - /* - * external phy 6-24 registers do not change with - * ddr frequency - */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - } - } + do_ext_phy_settings(base, regs); do_lpddr2_init(base, CS0); if (regs->sdram_config & EMIF_REG_EBANK_MASK) @@ -168,6 +144,10 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) /* Enable refresh now */ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + } + +__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ } void emif_update_timings(u32 base, const struct emif_regs *regs) diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index b538960..8761bc2 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -90,9 +90,6 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .emif_ddr_phy_ctlr_1 = 0x049ff418 }; -/* Dummy registers for OMAP44xx */ -const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; - const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index b2b5753..c1cf6f1 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -156,6 +156,37 @@ void emif_get_device_details(u32 emif_nr, #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ +void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 i = 0; + + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + writel(ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + } +} + #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS static const struct lpddr2_ac_timings timings_jedec_532_mhz = { .max_freq = 532000000, diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index f1e3ad2..e6ef6ea 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1093,6 +1093,8 @@ void emif_get_device_timings(u32 emif_nr, const struct lpddr2_device_timings **cs1_device_timings); #endif +void do_ext_phy_settings(u32 base, const struct emif_regs *regs); + #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS extern u32 *const T_num; extern u32 *const T_den; -- 1.7.1

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[U-Boot] [PATCH] omap: am33xx: accomodate input clocks other than 24 Mhz
by Steve Sakoman 21 Jun '12

21 Jun '12

The PLL setup values currently assume a 24 Mhz input clock. This patch uses V_OSCK from the board config file to support boards with different input clock rates. Signed-off-by: Steve Sakoman <steve(a)sakoman.com> --- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index abc5b6b..d748dd2 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -19,16 +19,16 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ -#define OSC 24 +#define OSC (V_OSCK/1000000) /* MAIN PLL Fdll = 550 MHZ, */ #define MPUPLL_M 550 -#define MPUPLL_N 23 +#define MPUPLL_N (OSC-1) #define MPUPLL_M2 1 /* Core PLL Fdll = 1 GHZ, */ #define COREPLL_M 1000 -#define COREPLL_N 23 +#define COREPLL_N (OSC-1) #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ @@ -40,13 +40,13 @@ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below */ #define PERPLL_M 960 -#define PERPLL_N 23 +#define PERPLL_N (OSC-1) #define PERPLL_M2 5 /* DDR Freq is 266 MHZ for now */ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ #define DDRPLL_M 266 -#define DDRPLL_N 23 +#define DDRPLL_N (OSC-1) #define DDRPLL_M2 1 extern void pll_init(void); -- 1.7.1

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[U-Boot] [PATCH 0/3] OMAP: Detect reset type and handle sdram init after warm rese
by Lokesh Vutla 21 Jun '12

21 Jun '12

Certain modules are not affected by means of a warm reset and need not be configured again. Adding an API to detect a warm reset. Emif is one such module that need not be configured after warm reset. All the registers are retained.So, skipping DDR init after warm reset. Freq_update is done to make sure timing registers are configured for appropriate frequency. This is tested on omap4430 sdp. Boot tested on omap5430uevm and omap5432sevm. Patch 3 is taking care of Errata:i727 Lokesh Vutla (3): ARM: OMAP3+: Detect reset type OMAP4+: Handle sdram init after warm reset OMAP4+: Force DDR in self-refresh after warm reset arch/arm/cpu/armv7/omap-common/emif-common.c | 31 ++++++++++++++++++++--- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 4 +++ arch/arm/cpu/armv7/omap-common/reset.c | 5 ++++ arch/arm/include/asm/arch-am33xx/cpu.h | 2 + arch/arm/include/asm/arch-omap3/cpu.h | 2 + arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + arch/arm/include/asm/arch-omap4/cpu.h | 2 + arch/arm/include/asm/arch-omap4/sys_proto.h | 2 + arch/arm/include/asm/arch-omap5/cpu.h | 2 + arch/arm/include/asm/arch-omap5/sys_proto.h | 2 + 10 files changed, 49 insertions(+), 4 deletions(-) -- 1.7.5.4

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[U-Boot] [PATCH] hawkboard/omapl-138: Add support for generating ais image for hawkboard
by Sughosh Ganu 21 Jun '12

21 Jun '12

Parameters used for configuring certain SoC peripherals are parsed from the cfg file and appended as part of the ais image's header. The u-boot-spl.ais generated is flashed separately to the nand, so do not delete the file after generation of u-boot.ais. Signed-off-by: Sughosh Ganu <urwithsughosh(a)gmail.com> --- .gitignore | 3 +++ Makefile | 5 +++-- board/davinci/da8xxevm/hawkboard-ais-nand.cfg | 4 ++++ include/configs/hawkboard.h | 1 + 4 files changed, 11 insertions(+), 2 deletions(-) create mode 100644 board/davinci/da8xxevm/hawkboard-ais-nand.cfg diff --git a/.gitignore b/.gitignore index 0f32fd8..d8a1893 100644 --- a/.gitignore +++ b/.gitignore @@ -75,3 +75,6 @@ cscope.* /onenand_ipl/onenand-ipl* /onenand_ipl/board/*/onenand* /onenand_ipl/board/*/*.S + +# spl ais files +/spl/*.ais diff --git a/Makefile b/Makefile index 0197239..8ac0530 100644 --- a/Makefile +++ b/Makefile @@ -441,7 +441,8 @@ $(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin rm $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(obj)tools/mkimage -s -n /dev/null -T aisimage \ + $(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \ + -T aisimage \ -e $(CONFIG_SPL_TEXT_BASE) \ -d $(obj)spl/u-boot-spl.bin \ $(obj)spl/u-boot-spl.ais @@ -450,7 +451,6 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \ $(obj)u-boot.ais - rm $(obj)spl/u-boot-spl{,-pad}.ais $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \ @@ -783,6 +783,7 @@ clobber: tidy @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f @rm -f $(obj)dts/*.tmp + @rm -f $(obj)spl/u-boot-spl{,-pad}.ais mrproper \ distclean: clobber unconfig diff --git a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg new file mode 100644 index 0000000..76282de --- /dev/null +++ b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg @@ -0,0 +1,4 @@ +# PLL0CFG0 PLL0CFG1 +PLL0 0x00180001 0x00000205 +# PLL1CFG0 PLL1CFG1 DRPYC1R SDCR SDTIMR1 SDTIMR2 SDRCR CLK2XSRC +DDR2 0x15010001 0x00000002 0x00000043 0x00134632 0x26492a09 0x7d13c722 0x00000249 0x00000000 diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index 6d2d4fb..5fa1273 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -43,6 +43,7 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_AIS_CONFIG_FILE "board/$(BOARDDIR)/hawkboard-ais-nand.cfg" #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_EMAC | \ -- 1.7.5.4

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[U-Boot] [PATCH v4 1/1] tegra: usb: Fix device enumeration problem of USB1
by Jim Lin 21 Jun '12

21 Jun '12

A known hardware issue of USB1 port where bit 1 (connect status change) of PORTSC register will be set after issuing Port Reset (like "usb reset" in u-boot command line). This will be treated as an error and stops later device enumeration. Therefore we clear that bit after Port Reset in order to proceed later device enumeration. Signed-off-by: Jim Lin <jilin(a)nvidia.com> --- To reproduce this issue, you can modify board .dts file to set as the following to build u-boot binary. " usb0 = "/usb@c5000000"; usb1 = "/usb@c5008000"; " Install device on USB1 port (address at 0xc5000000). And run "usb reset" in u-boot console to enumerate device. Before adding this patch, we could see problem every time. After adding, tried 10 times of "usb reset", "usb tree", "usb stop" , without seeing issue. Changes in v4: - Add comment to describe replacing weak function ehci_powerup_fixup of ehci-hcd.c - Remove using variable my_reg Changes in v3: - Move patch for USB1 controller into ehci_powerup_fixup of ehci-tegra.c - Update copyright year to 2012 Changes in v2: - Change config name - Add a callback function at the end of ehci_submit_root() function drivers/usb/host/ehci-tegra.c | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index a7e105b..6646d3a 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009 NVIDIA Corporation + * Copyright (c) 2009-2012 NVIDIA Corporation * * See file CREDITS for list of people who contributed to this * project. @@ -29,6 +29,22 @@ #include <asm/errno.h> #include <asm/arch/usb.h> +/* + * A known hardware issue where Connect Status Change bit of PORTSC register + * of USB1 controller will be set after Port Reset. + * We have to clear it in order for later device enumeration to proceed. + * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup + * in "ehci-hcd.c". + */ +void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) +{ + mdelay(50); + if (((u32) status_reg & 0xFFFFC000) != TEGRA_USB1_BASE) + return; + /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ + if (ehci_readl(status_reg) & EHCI_PS_CSC) + *reg |= EHCI_PS_CSC; +} /* * Create the appropriate control structures to manage -- 1.7.3 nvpublic

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[U-Boot] [PATCH v2] omap4: Use a smaller M,N couple for IVA DPLL
by Sebastien Jan 21 Jun '12

21 Jun '12

This reduced M,N couple corresponds to the advised value from TI HW team. Tested on 4460 Pandaboard, it also provides peripheral clocks closer to the advised values. Signed-off-by: Sebastien Jan <s-jan(a)ti.com> --- arch/arm/cpu/armv7/omap4/clocks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index c568951..1d92e66 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -146,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ - {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with sys_clk as source */ -- 1.7.9.5

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[U-Boot] [PATCH 0/4] OMAP4/5: Remove non-essential clocks, dplls, pads configurations.
by R Sricharan 21 Jun '12

21 Jun '12

On OMAP4/5 platforms, certain kernel drivers are dependent upon the bootloaders for clocks, dpll, pad configurations. But this should not be the case. Removing this from the u-boot is a way to get things fixed in the kernel. Have boot tested the kernel on OMAP4 SDP, PANDA, OMAP5 EVM boards. There are a lot of warnings during boot because some dplls are no more locked by default. This could also break other drivers which were dependent upon the bootloaders for their configurations. R Sricharan (4): ARM: OMAP4/5: Move gpmc clocks to essential group. ARM: OMAP4/5: Move USB clocks to essential group. ARM: OMAP4/5: Move USB pads to essential list. ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls. arch/arm/cpu/armv7/omap4/clocks.c | 12 +++++------- arch/arm/cpu/armv7/omap5/clocks.c | 8 ++++---- board/ti/omap5_evm/mux_data.h | 18 +++++++++--------- board/ti/sdp4430/sdp4430_mux_data.h | 25 ++++++++++++------------- include/configs/omap4_common.h | 5 ----- include/configs/omap5_evm.h | 2 -- 6 files changed, 30 insertions(+), 40 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH 0/6] Support for CPSW switch
by Ilya Yanok 21 Jun '12

21 Jun '12

These patches add CPSW switch driver and enable support for it on TI AM335x based boards. We need to detect the board type to configure pins correctly so these patches also include small fix to OMAP I2C driver. CC: Tom Rini <trini(a)ti.com> Signed-off-by: Ilya Yanok <ilya.yanok(a)cogentembedded.com> Cyril Chemparathy (1): cpsw: add driver for cpsw ethernet device Ilya Yanok (5): omap24xx_i2c: add 2-byte address support am33xx: CPSW init and definitions am33xx: pin mux defintions for CPSW switch am335x_evm: read the on-board EEPROM am335x_evm: CPSW support arch/arm/cpu/armv7/am33xx/clock.c | 8 +- arch/arm/include/asm/arch-am33xx/common_def.h | 2 + arch/arm/include/asm/arch-am33xx/cpu.h | 12 + arch/arm/include/asm/arch-am33xx/hardware.h | 5 + board/ti/am335x/evm.c | 158 +++- board/ti/am335x/mux.c | 47 ++ drivers/i2c/omap24xx_i2c.c | 58 +- drivers/net/Makefile | 1 + drivers/net/cpsw.c | 994 +++++++++++++++++++++++++ include/configs/am335x_evm.h | 20 +- include/cpsw.h | 51 ++ 11 files changed, 1320 insertions(+), 36 deletions(-) create mode 100644 drivers/net/cpsw.c create mode 100644 include/cpsw.h -- 1.7.9.5

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