June 2012 - U-Boot

[U-Boot] [PATCH] PXA: Enable CONFIG_PREBOOT on zipitz2
by Marek Vasut 07 Jul '12

07 Jul '12

Signed-off-by: Marek Vasut <marex(a)denx.de> --- include/configs/zipitz2.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 26204af..e14f59a 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -32,6 +32,7 @@ #undef CONFIG_BOARD_LATE_INIT #undef CONFIG_USE_IRQ #undef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_PREBOOT /* * Environment settings -- 1.7.9

2 2

[U-Boot] [PATCH] add new board vl_ma2sc
by Jens Scharsig 07 Jul '12

07 Jul '12

* add support for board VL+MA2SC * adds vl_ma2sc_config for standard NOR boot configuration * adds vl_ma2sc_ram_config for RAM load configuration Signed-off-by: Jens Scharsig <esw(a)bus-elektronik.de> --- MAINTAINERS | 1 + board/BuS/vl_ma2sc/Makefile | 54 ++++ board/BuS/vl_ma2sc/vl_ma2sc.c | 596 +++++++++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/vl_ma2sc.h | 466 ++++++++++++++++++++++++++++++++ 5 files changed, 1119 insertions(+), 0 deletions(-) create mode 100644 board/BuS/vl_ma2sc/Makefile create mode 100644 board/BuS/vl_ma2sc/vl_ma2sc.c create mode 100644 include/configs/vl_ma2sc.h diff --git a/MAINTAINERS b/MAINTAINERS index a5b728e..12047fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -819,6 +819,7 @@ Steve Sakoman <sakoman(a)gmail.com> Jens Scharsig <esw(a)bus-elektronik.de> eb_cpux9k2 ARM920T (AT91RM9200 SoC) + vl_ma2sc ARM926EJS (AT91SAM9263 SoC) Heiko Schocher <hs(a)denx.de> diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile new file mode 100644 index 0000000..3f36a4d --- /dev/null +++ b/board/BuS/vl_ma2sc/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2009-2012 +# Jens Scharsig <esw(a)bus-elekronik.de> +# BuS Elektronik GmbH & Co. KG +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS += vl_ma2sc.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c new file mode 100644 index 0000000..dfaf2cb --- /dev/null +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -0,0 +1,596 @@ +/* + * (C) Copyright 2009-2012 + * Jens Scharsig <esw(a)bus-elekronik.de> + * BuS Elektronik GmbH & Co. KG + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/sizes.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clk.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_common.h> +#include <lcd.h> +#include <i2c.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void vl_ma2sc_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */ + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); + + /* Configure SMC CS3 for NAND/SmartMedia */ +#if 1 + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); +#else +#warning SAMSUNG Timmings +#define NTM 1 + writel(AT91_SMC_SETUP_NWE(NTM * 2) | AT91_SMC_SETUP_NCS_WR(NTM * 1) | + AT91_SMC_SETUP_NRD(NTM * 2) | AT91_SMC_SETUP_NCS_RD(NTM * 1), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(NTM * 3) | AT91_SMC_PULSE_NCS_WR(NTM * 5) | + AT91_SMC_PULSE_NRD(NTM * 5) | AT91_SMC_PULSE_NCS_RD(NTM * 7), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(NTM * 7) | AT91_SMC_CYCLE_NRD(NTM * 10), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); +#endif + writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + /* Configure RDY/BSY */ +#ifdef CONFIG_SYS_NAND_READY_PIN + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + /* Enable NandFlash */ + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void vl_ma2sc_macb_hw_init(void) +{ + unsigned long erstl; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + + writel((1 << 25), &pio->pioc.pudr); + writel((1 << 25) | (1 << 26), &pio->pioe.pudr); + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + + /* Re-enable pull-up */ + writel((1 << 25), &pio->pioc.puer); + writel((1 << 25) | (1 << 26), &pio->pioe.puer); + + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 320, + vl_row: 240, + vl_clk: 6500000, + vl_sync: ATMEL_LCDC_INVDVAL_INVERTED | + ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVVD_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: (ATMEL_LCDC_PIXELSIZE_8 >> 5), + vl_tft: 1, + vl_hsync_len: 5, /* Horiz Sync Pulse Width */ + vl_left_margin: 68, /* horiz back porch */ + vl_right_margin: 20, /* horiz front porch */ + vl_vsync_len: 2, /* vert Sync Pulse Width */ + vl_upper_margin: 18, /* vert back porch */ + vl_lower_margin: 4, /* vert front porch */ + mmio: ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ +} + +void lcd_disable(void) +{ +} + +static void vl_ma2sc_lcd_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ + at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ + + at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */ + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ + + at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */ + + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */ + at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */ + at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */ + at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */ + at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */ + at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */ + + at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */ + + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + gd->fb_base = ATMEL_BASE_SRAM0; +} + +#endif /* Config LCD */ + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + at91_seriald_hw_init(); + + return 0; +} +#endif + +int board_init(void) +{ + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + pin = 0x1F000001; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); + writel((1 << 25), &pio->pioa.codr); + + pin = 0x1F000100; + writel(pin, &pio->piob.idr); + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.codr); + writel((1 << 24), &pio->piob.sodr); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + + pin = 0x0000000F; /* HWversion als Input */ + writel(pin, &pio->piod.idr); + writel(pin, &pio->piod.puer); + writel(pin, &pio->piod.per); + writel(pin, &pio->piod.odr); + writel(pin, &pio->piod.owdr); + + /* Enable Ctrlc */ + console_init_f(); + + gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC; + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup); + writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle); + writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse); + writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup); + +#ifdef CONFIG_CMD_NAND + vl_ma2sc_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + vl_ma2sc_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + vl_ma2sc_lcd_hw_init(); +#endif + return 0; +} + +#ifdef CONFIG_MISC_INIT_R + +int misc_init_r(void) +{ + uchar buffer[8]; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + buffer[0] = 0x04; + buffer[1] = 0x00; + if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0) + puts("error reseting rtc clock\n\0"); + + /* HWversion lesen */ + + pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44; + printf("Board: revision %c\n", pin); + buffer[0] = pin; + buffer[1] = 0; + setenv("revision", (char *) buffer); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01); +#endif + return rc; +} + +#ifdef CONFIG_SOFT_I2C + +void i2c_init_board(void) +{ + u32 pin; + + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u8 sda = (1<<4); + u8 scl = (1<<5); + + writel(1 << ATMEL_ID_PIOB, &pmc->pcer); + pin = sda | scl; + writel(pin, &pio->piob.idr); /* Disable Interupt */ + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.sodr); +} + +#endif + +void watchdog_reset(void) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin = 0x1; /* PA0 */ + + if ((readl(&pio->pioa.odsr) & pin) > 0) + writel(pin, &pio->pioa.codr); + else + writel(pin, &pio->pioa.sodr); +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + +/*---------------------------------------------------------------------------*/ + +int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + int col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */ + + pins = 0x1F000000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.oer); + writel(pins, &pio->pioa.sodr); + + pinz = 0x1F000000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.sodr); + + for (row = 0; row < 5; row++) { + for (col = 0; col < 5; col++) { + writel((0x01000000 << col), &pio->piob.sodr); + writel((0x01000000 << row), &pio->pioa.codr); + printf("LED Test %d x %d\n", row, col); + udelay(1000000); + writel(pinz, &pio->piob.codr); + writel(pins, &pio->pioa.sodr); + } + } + + return rcode; +} + +void poweroff(void) +{ + watchdog_reset(); + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */ + udelay(100); + while (1) + watchdog_reset(); +} + +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + poweroff(); + return rcode; +} + +int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + u32 freq; + u32 durate; + int rcode = 1; + + freq = 1000; + durate = 2; + switch (argc) { + case 3: + durate = simple_strtoul(argv[2], NULL, 10); + case 2: + freq = simple_strtoul(argv[1], NULL, 10); + case 1: + break; + default: + cmd_usage(cmdtp); + rcode = 1; + break; + } + durate = durate * freq; + freq = 500000 / freq; + for (i = 0; i < durate; i++) { + at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/ + udelay(freq); + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + udelay(freq); + } + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + return rcode; +} + +int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + u32 col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + writel((1 << ATMEL_ID_PIOA), &pmc->pcer); + + pins = 0x001F0000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.odr); + + pinz = 0x000F0000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.codr); + + while (1) { + col = 0; + for (row = 0; row < 4; row++) { + writel((0x00010000 << row), &pio->piob.sodr); + udelay(10000); + col <<= 4; + col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ; + writel(pinz, &pio->piob.codr); + } + printf("Matix: "); + for (row = 0; row < 16; row++) { + printf("%1.1d", col & 1); + col >>= 1; + } + printf(" SP %d\r ", + 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20))); + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) { + /* SHUTDOWN */ + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) + row++; + udelay(100); + } + udelay(100000); + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) { + row++; + udelay(1000); + } + } + poweroff(); + while (1) + ; + } + } + return rcode; +} + +/*****************************************************************************/ + +U_BOOT_CMD( + ledtest, 1, 0, do_ledtest, + "test ledmatrix", + "\n" + ); + +U_BOOT_CMD( + keytest, 1, 0, do_keytest, + "test keymatix and special keys, poweroff on pressing ON key", + "\n" + ); + +U_BOOT_CMD( + poweroff, 1, 0, do_poweroff, + "power off", + "\n" + ); + +U_BOOT_CMD( + beep, 3, 0, do_beep, + "[freq [duration]]", + "freq frequence of beep\nduration duration of beep\n" + ); + +/*****************************************************************************/ diff --git a/boards.cfg b/boards.cfg index 576b392..2f7211f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -94,6 +94,8 @@ at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 +vl_ma2sc arm arm926ejs vl_ma2sc BuS at91 +vl_ma2sc_ram arm arm926ejs vl_ma2sc BuS at91 vl_ma2sc:RAMLOAD sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h new file mode 100644 index 0000000..d9c2a2d --- /dev/null +++ b/include/configs/vl_ma2sc.h @@ -0,0 +1,466 @@ +/* + * (C) Copyright 2009-2012 + * Jens Scharsig <esw(a)bus-elekronik.de> + * BuS Elektronik GmbH & Co. KG + * + * Configuation settings for the VL_MA2SC board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*--------------------------------------------------------------------------*/ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ +#define CONFIG_AT91FAMILY +#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_MISC_INIT_R + +#include <asm/hardware.h> + +#define MACH_TYPE_VL_MA2SC 2412 +#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC + +#define CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_RAMLOAD +#define CONFIG_SYS_TEXT_BASE 0x21000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#endif +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_IDENT_STRING " on MiS Activ 2" +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AT91_GPIO + +#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD) +#define CONFIG_SYS_USE_NORFLASH +#define CONFIG_SYS_USE_BOOT_NORFLASH +#endif + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#ifndef CONFIG_SYS_USE_BOOT_NORFLASH +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * Hardware drivers + */ + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_WATCHDOG + +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* LCD */ +#define CONFIG_LCD +#define CONFIG_ATMEL_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SYS_BLACK_ON_WHITE +#define LCD_BPP LCD_COLOR8 +#define CONFIG_ATMEL_LCD_BGR555 + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_BMP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_MD5SUM +#define CONFIG_CMD_SHA1SUM +/* +#define CONFIG_CMD_SPI +*/ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_SYS_LONGHELP +#define CONFIG_MD5 +#define CONFIG_SHA1 + +/*---------------------------------------------------------------------------- + * Hardware confuguration + *---------------------------------------------------------------------------*/ + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#define CONFIG_AT91C_PQFP_UHPBUG + +/* I2C-Bus */ + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ + +#ifndef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C + +/* Software I2C driver configuration */ + +#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) + +#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */ +#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */ + +#define I2C_INIT i2c_init_board(); +#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr); +#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder); +#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + writel(AT91_PIN_SDA, &pio->piob.sodr); \ + else \ + writel(AT91_PIN_SDA, &pio->piob.codr); \ + } while (0); +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + writel(AT91_PIN_SCL, &pio->piob.sodr); \ + else \ + writel(AT91_PIN_SCL, &pio->piob.codr); \ + } while (0); +#endif + +/* I2C-RTC */ + +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_DS1338 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#endif + +/* EEPROM */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 + +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ + AT91_MATRIX_CSA_EBI_CS1A) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_MR_URSTEN | \ + AT91_RSTC_MR_ERSTL(15)) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xFFF) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xFFF)) + +/* clocks */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define MHZ180 +#if defined(MHZ199) +/* 199,8994 MHZ */ +#define MASTER_PLL_MUL 911 +#define MASTER_PLL_DIV 56 +#define MASTER_PLL_OUT 2 +#elif defined(MHZ180) +/* 180 MHZ */ +#define MASTER_PLL_MUL 1875 +#define MASTER_PLL_DIV 128 +#define MASTER_PLL_OUT 2 +#elif defined(MHZTEST) +/* Test MHZ */ +#define CONFIG_DISPLAY_CPUINFO +#define MASTER_PLL_MUL 8 +#define MASTER_PLL_DIV 1 +#define MASTER_PLL_OUT 2 +#else +/* 176.9472 MHZ */ +#define MASTER_PLL_MUL 72 +#define MASTER_PLL_DIV 5 +#define MASTER_PLL_OUT 2 +#endif + +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) + +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLAR_29 | \ + AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ + AT91_PMC_PLLXR_PLLCOUNT(63) | \ + AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ + AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */ + +#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CONFIG_SYS_SDRC_TR_VAL1 700 +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (8 << 28)) /* Exit Self Refresh to Active Delay */ + +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* NOR flash */ + +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_ETHADDR 00:4D:41:02:52:43 /* MA2SC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x21e00000 + +/* Address and size of Primary Environment Sector */ +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SIZE 0x20000 +#else +#define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \ + 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifndef CONFIG_RAMLOAD +#define CONFIG_BOOTCOMMAND "run nfsboot" +#endif +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_MIN 15 + +#define CONFIG_NFSBOOTCOMMAND \ + "dhcp $(copy_addr) $(kernelname);" \ + "run bootargsdefaults;" \ + "set bootargs $(bootargs) boot=nfs " \ + ";echo $(bootargs)" \ + ";bootm" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ubootaddr=10000000\0" \ + "splashimage=10080000\0" \ + "kerneladdr=100A0000\0" \ + "kernelsize=00800000\0" \ + "minifsaddr=108A0000\0" \ + "minifssize=00060000\0" \ + "rootfsaddr=10900000\0" \ + "copy_addr=20200000\0" \ + "rootfssize=01700000\0" \ + "kernelname=uImage_vl_ma2sc\0" \ + "bootargsdefaults=set bootargs " \ + "console=ttyS0,115200 " \ + "video=atmel_lcdfb " \ + "mem=62M " \ + "panic=10 " \ + "boardrevison=\\\"${revision}\\\" " \ + "uboot=\\\"${ver}\\\" " \ + "\0" \ + "update_all=run update_kernel;run update_root;" \ + "run update_splash; run update_uboot\0" \ + "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ + "dhcp $(copy_addr) $(kernelname);" \ + "erase $(kerneladdr) +$(kernelsize);" \ + "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ + "protect on $(kerneladdr) +$(kernelsize)" \ + "\0" \ + "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ + "dhcp $(copy_addr) vl_ma2sc.root;" \ + "erase $(rootfsaddr) +$(rootfssize);" \ + "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ + "\0" \ + "update_splash=protect off $(splashimage) +20000;" \ + "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \ + "erase $(splashimage) +20000;" \ + "cp.b $(fileaddr) 10080000 $(filesize);" \ + "protect on $(splashimage) +20000\0" \ + "update_uboot=protect off 10000000 1005FFFF;" \ + "dhcp $(copy_addr) u-boot_vl_ma2sc;" \ + "erase 10000000 1005FFFF;" \ + "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ + "protect on 10000000 1005FFFF;reset\0" \ + "emergency=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(kerneladdr)\0" \ + "netemergency=run bootargsdefaults;" \ + "dhcp $(copy_addr) $(kernelname);" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(copy_addr)\0" \ + "norboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=local quiet " \ + ";bootm $(kerneladdr)\0" \ + "nandboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=nand " \ + ";bootm $(kerneladdr)\0" \ + "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \ + "clearenv=protect off 10060000 1007FFFF;" \ + "erase 10060000 1007FFFF;reset\0" \ + " " + +/*--------------------------------------------------------------------------*/ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif + +/* EOF */ -- 1.7.3.4

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[U-Boot] [PATCH v4 0/6] Enable Thumb build for ARM platforms
by Aneesh V 07 Jul '12

07 Jul '12

Thumb is an alternate instruction set available in many ARM processors. Below is a detailed description from ARM specs: "The Thumb instruction set is a re-encoded subset of the ARM instruction set. Thumb instructions execute in their own processor state, with the architecture defining the mechanisms required to transition between ARM and Thumb states. The key difference is that Thumb instructions are half the size of ARM instructions(16 bits compared with 32 bits). Greater code density can usually be achieved by using the Thumb instruction set in preference to the ARM instruction set, at a cost of some reduction in performance" "In ARMv6T2, Thumb-2 technology is introduced. This technology makes it possible to extend the original Thumb instruction set with many 32-bit instructions. The range of 32-bit Thumb instructions included in ARMv6T2 permits Thumb code to achieve performance similar to ARM code, with code density better than that of earlier Thumb code. From ARMv6T2, the ARM and Thumb instruction sets provide almost identical functionality" This series adds Thumb support in U-Boot and enables it for OMAP4. It also fixes issues faced while booting OMAP4 with Thumb-2 images of U-Boot and SPL. Thumb mode is becoming increasingly relevant for U-Boot with the advent of SPL. It's very important to keep SPL size smaller considering the internal RAM size constraints on many platforms. On OMAP4 the size reduction enables us to use SPL on secure devices that have smaller internal RAM available for non-secure world. To enable support for new platforms you just need to add CONFIG_SYS_THUMB_BUILD in your config file. Tool-chains tried: 1. Sourcery G++ Lite 2010q1-202 arm-none-linux-gnueabi-gcc (Sourcery G++ Lite 2010q1-202) 4.4.1 GNU ld (Sourcery G++ Lite 2010q1-202) - binutils 2.19.51.20090709 2. Linaro 4.6-2012.01 arm-linux-gnueabi-gcc (crosstool-NG linaro-1.13.1-2012.01-20120125 - Linaro GCC 2012.01) 4.6.3 20120105 (prerelease) GNU ld (crosstool-NG linaro-1.13.1-2012.01-20120125 - Linaro GCC 2012.01) 2.22 Code-size reduction: Image ARM build Thumb build % Reduction u-boot.bin 190408 144676 24.01% u-boot-spl.bin 33200 25096 24.40% Performance(timestamp just before the main loop): ARM build Thumb build % Reduction 898510us 878247us -2.25% Performance actually improved marginally for the Thumb build, maybe because of the reduced image sizes. Aneesh V (6): arm: adapt asm/linkage.h from Linux armv7: add appropriate headers for assembly functions ARM: enable Thumb build armv7: Use -march=armv7-a and thereby enable Thumb-2 omap4+: Avoid using __attribute__ ((__packed__)) OMAP4: enable Thumb build README | 8 +++++ arch/arm/config.mk | 22 +++++++++---- arch/arm/cpu/armv7/config.mk | 7 +++- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 5 ++- arch/arm/cpu/armv7/mx6/lowlevel_init.S | 5 ++- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 14 ++++---- arch/arm/cpu/armv7/omap-common/reset.S | 5 ++- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 41 ++++++++++++----------- arch/arm/cpu/armv7/s5pc1xx/cache.S | 10 +++-- arch/arm/cpu/armv7/s5pc1xx/reset.S | 5 ++- arch/arm/cpu/armv7/start.S | 13 ++++--- arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 5 ++- arch/arm/cpu/armv7/u8500/lowlevel.S | 9 +++-- arch/arm/include/asm/arch-omap4/mux_omap4.h | 2 +- arch/arm/include/asm/arch-omap5/mux_omap5.h | 2 +- arch/arm/include/asm/linkage.h | 7 ++++ include/configs/omap4_common.h | 2 + include/linux/linkage.h | 7 +++- 18 files changed, 106 insertions(+), 63 deletions(-) create mode 100644 arch/arm/include/asm/linkage.h

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[U-Boot] [PATCH 0/9] CACHE: Finishing touches
by Marek Vasut 07 Jul '12

07 Jul '12

Add a few finishing touches for the cache support. Then ultimately enable cache support on m28. BIG FAT NOTE: This is for -next. This may break something. Compile testing IS STILL IN PROGRESS! Marek Vasut (9): COMMON: Add __stringify() function CACHE: Add cache_aligned() macro CACHE: ext2load: Test if start address is aligned CACHE: fatload: Test if start address is aligned CACHE: mmc read/write: Test if start address is aligned CACHE: nand read/write: Test if start address is aligned CACHE: net: Test if start address is aligned CACHE: net: asix: Fix asix driver to work with data cache on M28EVK: Enable instruction and data cache common/cmd_ext2.c | 3 +++ common/cmd_fat.c | 4 ++++ common/cmd_mmc.c | 2 ++ common/cmd_nand.c | 9 +++++++++ common/cmd_net.c | 4 ++++ drivers/usb/eth/asix.c | 29 ++++++++++++++++------------- include/common.h | 25 +++++++++++++++++++++++++ include/configs/m28evk.h | 2 -- 8 files changed, 63 insertions(+), 15 deletions(-) Cc: Wolfgang Denk <wd(a)denx.de> -- 1.7.10

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[U-Boot] [PATCH] fs/ext2/ext2fs.c: fix warning
by Andreas Bießmann 06 Jul '12

06 Jul '12

This patch fixes following warning: ---8<--- ext2fs.c: In function 'ext2fs_read_file': ext2fs.c:458:19: warning: 'blocknxt' may be used uninitialized in this function [-Wuninitialized] --->8--- The warning was introduced in 436da3cd233e7166b5ce9293dbd28092cf37bcc9. Signed-off-by: Andreas Bießmann <andreas.devel(a)googlemail.com> cc: Jason Cooper <u-boot(a)lakedaemon.net> cc: Eric Nelson <eric.nelson(a)boundarydevices.com> cc: Thierry Reding <thierry.reding(a)avionic-design.de> --- fs/ext2/ext2fs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c index f1fce48..40b6e6f 100644 --- a/fs/ext2/ext2fs.c +++ b/fs/ext2/ext2fs.c @@ -440,7 +440,7 @@ int ext2fs_read_file /* grab middle blocks in one go */ if (i != pos / blocksize && i != blockcnt - 1 && blockcnt > 3) { int oldblk = blknr; - int blocknxt; + int blocknxt = blknr; while (i < blockcnt - 1) { blocknxt = ext2fs_read_block(node, i + 1); if (blocknxt == (oldblk + 1)) { -- 1.7.10

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[U-Boot] Please pull u-boot-staging.git/sr@denx.de
by Stefan Roese 05 Jul '12

05 Jul '12

Hi Albert! I have collected all of the remaining ARM/SPEAr patches in my staging repository. There are some dependencies between the patches, so I also added the NOR, NAND and ethernet patches in this pull request. The patches have the Acked-by from the corresponding custodians (Joe for networking, Scott for NAND, myself for NOR). Since most of the patches are ARM/SPEAr platform related, I'm pushing the patchset through your ARM repository. Please pull and push to Wolfgang. Thanks, Stefan The following changes since commit 4398d55991eb3c2484a2a8e991d701e5d7a64874: net: sh-eth: Add support Gigabit of SH7734 (2012-05-23 17:53:09 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-staging.git sr(a)denx.de for you to fetch changes up to e94b7cb06a246532aba7af9e0f2040d4facba5db: MTD: SPEAr SMI: Add write support for length < 4 bytes (2012-06-05 08:42:50 +0200) ---------------------------------------------------------------- Amit Virdi (10): st_smi: Return error in case TFF is not set st_smi: Change SMI timeout values st_smi: Enhance the error handling st_smi: Change timeout loop implementation SPEAr: Fix ARM relocation support SPEAr: Eliminate dependency on Xloader table SPEAr: Initialize SNOR in early_board_init_f SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access cleanup/SPEAr: Remove unnecessary parenthesis cleanup/SPEAr: Define configuration flags more elegantly Armando Visconti (4): st_smi: Removed no needed dependency on ST_M25Pxx_ID st_smi: Change the flash probing method st_smi: Fix bug in flash_print_info() st_smi: Fixed page size for Winbond W25Q128FV flash Shiraz Hashim (5): st_smi: Move status register read before modifying ctrl register SPEAr: Enable autoneg for ethernet SPEAr: Enable dcache for fast file transfer SPEAr: explicitly select clk src for UART SPEAr: Correct SoC ID offset in misc configuration space Simon Glass (1): arm: Don't use printf() in SPL builds Stefan Roese (10): net: Multiple updates/enhancements to designware.c GPIO: Add SPEAr GPIO driver SPL: common/Makefile: Add image.c to SPL build SPL: lib/Makefile: Add crc32.c to SPL build SPL: ARM: spear: Remove some objects from SPL build Makefile: Add u-boot.spr build target (SPEAr) SPL: ARM: spear: Add SPL support for SPEAr600 platform rtc/m41t62: Add support for M41T82 with HT (Halt Update) i2c: designware_i2c.c: Add support for the "i2c probe" command MTD: SPEAr SMI: Add write support for length < 4 bytes Vipin KUMAR (14): mtd/NAND: Add FSMC driver support SPEAr: Configure FSMC driver for NAND interface mtd/NAND: Remove obsolete SPEAr specific NAND drivers st_smi: Add support for SPEAr SMI driver st_smi: Read status until timeout happens SPEAr: Place ethaddr write and read within CONFIG_CMD_NET SPEAr: Configure network support for spear SoCs SPEAr: Add macb driver support for spear310 and spear320 SPEAr: Add basic arch related support for SPEAr SoCs SPEAr: Add configuration options for spear3xx and spear6xx boards SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK) SPEAr: Change the default environment variables SPEAr: Enable usb device high speed support SPEAr: Enable udc and usb-console support only for usbtty configuration Vipin Kumar (6): st_smi: Fix smi read status SPEAr: Add interface information in initialization SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb Makefile | 17 + arch/arm/cpu/arm926ejs/spear/Makefile | 25 +- arch/arm/cpu/arm926ejs/spear/cpu.c | 87 ++++ arch/arm/cpu/arm926ejs/spear/spear600.c | 236 ++++++++++ arch/arm/cpu/arm926ejs/spear/spl.c | 282 ++++++++++++ arch/arm/cpu/arm926ejs/spear/spl_boot.c | 197 ++++++++ .../spear/spr600_mt47h128m8_3_266_cl5_async.c | 130 ++++++ .../spear/spr600_mt47h32m16_333_cl5_psync.c | 135 ++++++ .../spear/spr600_mt47h32m16_37e_166_cl4_sync.c | 130 ++++++ .../spear/spr600_mt47h64m16_3_333_cl5_psync.c | 144 ++++++ arch/arm/cpu/arm926ejs/spear/start.S | 122 +++++ arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 87 ++++ arch/arm/include/asm/arch-spear/clk.h | 27 ++ arch/arm/include/asm/arch-spear/gpio.h | 40 ++ arch/arm/include/asm/arch-spear/hardware.h | 63 ++- arch/arm/include/asm/arch-spear/spr_defs.h | 23 + arch/arm/include/asm/arch-spear/spr_gpt.h | 4 +- arch/arm/include/asm/arch-spear/spr_misc.h | 147 +++++- arch/arm/include/asm/arch-spear/spr_nand.h | 57 --- arch/arm/include/asm/arch-spear/spr_ssp.h | 45 ++ arch/arm/include/asm/arch-spear/spr_syscntl.h | 14 + .../arm/include/asm/arch-spear/spr_xloader_table.h | 67 --- arch/arm/lib/eabi_compat.c | 3 +- board/spear/common/Makefile | 2 + board/spear/common/spr_misc.c | 102 ++-- board/spear/spear300/config.mk | 39 -- board/spear/spear300/spear300.c | 27 +- board/spear/spear310/config.mk | 44 -- board/spear/spear310/spear310.c | 44 +- board/spear/spear320/config.mk | 44 -- board/spear/spear320/spear320.c | 43 +- board/spear/spear600/Makefile | 2 + board/spear/spear600/config.mk | 39 -- board/spear/spear600/spear600.c | 30 +- boards.cfg | 24 +- common/Makefile | 2 +- config.mk | 4 + doc/README.spear | 54 ++- drivers/gpio/Makefile | 1 + drivers/gpio/spear_gpio.c | 102 ++++ drivers/i2c/designware_i2c.c | 16 +- drivers/mtd/Makefile | 2 +- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/fsmc_nand.c | 486 ++++++++++++++++++++ drivers/mtd/nand/spr_nand.c | 124 ----- drivers/mtd/{spr_smi.c => st_smi.c} | 255 ++++++---- drivers/net/designware.c | 126 +++-- drivers/net/designware.h | 2 + drivers/rtc/m41t62.c | 10 +- include/configs/spear-common.h | 94 ++-- include/configs/{spear3xx.h => spear3xx_evb.h} | 62 ++- include/configs/{spear6xx.h => spear6xx_evb.h} | 20 +- include/linux/mtd/fsmc_nand.h | 101 ++++ .../spr_smi.h => include/linux/mtd/st_smi.h | 10 +- include/netdev.h | 2 +- lib/Makefile | 2 +- 56 files changed, 3229 insertions(+), 769 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/spear/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spear600.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spl.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spl_boot.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c create mode 100644 arch/arm/cpu/arm926ejs/spear/start.S create mode 100644 arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-spear/clk.h create mode 100644 arch/arm/include/asm/arch-spear/gpio.h delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h create mode 100644 arch/arm/include/asm/arch-spear/spr_ssp.h delete mode 100644 arch/arm/include/asm/arch-spear/spr_xloader_table.h delete mode 100644 board/spear/spear300/config.mk delete mode 100644 board/spear/spear310/config.mk delete mode 100644 board/spear/spear320/config.mk delete mode 100644 board/spear/spear600/config.mk create mode 100644 drivers/gpio/spear_gpio.c create mode 100644 drivers/mtd/nand/fsmc_nand.c delete mode 100644 drivers/mtd/nand/spr_nand.c rename drivers/mtd/{spr_smi.c => st_smi.c} (62%) rename include/configs/{spear3xx.h => spear3xx_evb.h} (72%) rename include/configs/{spear6xx.h => spear6xx_evb.h} (74%) create mode 100644 include/linux/mtd/fsmc_nand.h rename arch/arm/include/asm/arch-spear/spr_smi.h => include/linux/mtd/st_smi.h (95%)

2 4

[U-Boot] [PATCH v2 00/14] updates for Keymile Marvell boards
by Holger Brunck 05 Jul '12

05 Jul '12

Updated after some comments on the Mailing list. >From the previous version was removed and send as standalone patch: [PATCH 03/20] arm/kirkwood: protect the ENV_SPI see: http://lists.denx.de/pipermail/u-boot/2012-June/126140.html And this four were squshed to one: [PATCH 01/20] arm/km: enable spi claim bus [PATCH 02/20] arm/km: use correct kw_gpio function for NAND/SPI switching [PATCH 18/20] arm/km: implement weak function board_spi_clam_bus/release [PATCH 19/20] arm/km: remove spi toggle command see: http://lists.denx.de/pipermail/u-boot/2012-June/126139.html Additionaly [PATCH 17/20] arm/km: fix testpin detection for kmcoge5un was squashed to kmcoge5un board support, which makes logically sense. cc: Holger Brunck <holger.brunck(a)keymile.com> cc: Valentin Longchamp <valentin.longchamp(a)keymile.com> cc: Prafulla Wadaskar <prafulla(a)marvell.com> Holger Brunck (6): arm/km: add kmnusa board support arm/km: add kmcoge5un board support arm/km: convert mgcoge3un target to km_kirkwood arm/km: remove portl2.h and use km_kirkwood instead arm/km: cleanup km_kirkwood boards arm/km: remove calls to kw_gpio_* in board_early_init_f Thomas Herzmann (1): arm/km: add implementation for read_dip_switch Valentin Longchamp (7): arm/km: correct init of 88e6352 switch in the reset_phy function arm/km: enable BOCO2 FPGA download support arm/km: redefine piggy 4 reg names to avoid conflicts arm/km: add support for external switch configuration arm/km: enable external switch configuration for kmnusa arm/km: skip FPGA config when already configured arm/km: support the 2 PCIe fpga resets MAINTAINERS | 2 + board/keymile/common/common.h | 5 + board/keymile/km_arm/Makefile | 8 + board/keymile/km_arm/fpga_config.c | 256 ++++++++++++++++++++++ board/keymile/km_arm/km_arm.c | 127 ++++++++--- board/keymile/km_arm/kwbimage_128M16_1.cfg | 296 ++++++++++++++++++++++++++ board/keymile/km_arm/kwbimage_256M8_1.cfg | 296 ++++++++++++++++++++++++++ board/keymile/km_arm/managed_switch.c | 316 ++++++++++++++++++++++++++++ board/keymile/km_arm/managed_switch.h | 106 ++++++++++ boards.cfg | 10 +- include/configs/km/km_arm.h | 48 ++++- include/configs/km_kirkwood.h | 154 +++++++++++++-- include/configs/mgcoge3un.h | 87 -------- include/configs/portl2.h | 85 -------- 14 files changed, 1565 insertions(+), 231 deletions(-) create mode 100644 board/keymile/km_arm/fpga_config.c create mode 100644 board/keymile/km_arm/kwbimage_128M16_1.cfg create mode 100644 board/keymile/km_arm/kwbimage_256M8_1.cfg create mode 100644 board/keymile/km_arm/managed_switch.c create mode 100644 board/keymile/km_arm/managed_switch.h delete mode 100644 include/configs/mgcoge3un.h delete mode 100644 include/configs/portl2.h

5 39

[U-Boot] [PATCH 1/2] KW: Move the memory register definitions into kirkwood.h
by Marek Vasut 05 Jul '12

05 Jul '12

Also add the CPUCS register definition. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Prafulla Wadaskar <prafulla(a)marvell.com> Cc: Wolfgang Denk <wd(a)denx.de> --- arch/arm/cpu/arm926ejs/kirkwood/dram.c | 2 -- arch/arm/include/asm/arch-kirkwood/kirkwood.h | 9 +++++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c index 181b3e7..ccb6b03 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c @@ -30,8 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08)) -#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08)) /* * kw_sdram_bar - reads SDRAM Base Address Register */ diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h index 47771d5..33ae827 100644 --- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h +++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h @@ -77,6 +77,15 @@ #define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE #define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE +/* Kirkwood memory registers */ +#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + ((x) * 0x08)) +#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + ((x) * 0x08)) + +#define KW_REG_CPUCS_WIN_ENABLE (1 << 0) +#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1) +#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) +#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) + #if defined (CONFIG_KW88F6281) #include <asm/arch/kw88f6281.h> #elif defined (CONFIG_KW88F6192) -- 1.7.10

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[U-Boot] [PATCH] smdk6400: Move smdk6400 board from Makefile to boards.cfg
by Zhong Hongbo 05 Jul '12

05 Jul '12

From: seedshope <bocui107(a)gmail.com> Signed-off-by: Zhong Hongbo <bocui107(a)gmail.com> --- Makefile | 20 -------------------- board/samsung/smdk6400/config.mk | 4 +--- boards.cfg | 2 ++ include/configs/smdk6400.h | 2 +- 4 files changed, 4 insertions(+), 24 deletions(-) diff --git a/Makefile b/Makefile index 0197239..e3af33f 100644 --- a/Makefile +++ b/Makefile @@ -695,26 +695,6 @@ SX1_config: unconfig fi; @$(MKCONFIG) -n $@ SX1 arm arm925t sx1 -######################################################################### -## ARM1176 Systems -######################################################################### -smdk6400_noUSB_config \ -smdk6400_config : unconfig - @mkdir -p $(obj)include $(obj)board/samsung/smdk6400 - @mkdir -p $(obj)nand_spl/board/samsung/smdk6400 - @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h - @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk - @if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then \ - echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\ - else \ - echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\ - fi - @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx - @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk - -######################################################################### -######################################################################### - clean: @rm -f $(obj)examples/standalone/82559_eeprom \ $(obj)examples/standalone/atmel_df_pow2 \ diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk index 6f04c2f..93a1a0d 100644 --- a/board/samsung/smdk6400/config.mk +++ b/board/samsung/smdk6400/config.mk @@ -21,10 +21,8 @@ # # download area is 0x5000c000 -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - ifndef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = $(RAM_TEXT) +CONFIG_SYS_TEXT_BASE = $(CONFIG_RAM_TEXT) else CONFIG_SYS_TEXT_BASE = 0 endif diff --git a/boards.cfg b/boards.cfg index 53f6dc3..42b0883 100644 --- a/boards.cfg +++ b/boards.cfg @@ -47,6 +47,8 @@ flea3 arm arm1136 - CarMedi mx35pdk arm arm1136 - freescale mx35 apollon arm arm1136 apollon - omap24xx omap2420h4 arm arm1136 - ti omap24xx +smdk6400 arm arm1176 smdk6400 samsung s3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0xc7e00000 +smdk6400_nousb arm arm1176 smdk6400 samsung s3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0x57e00000 tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 04caeef..47326d6 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -54,7 +54,7 @@ /* input clock of PLL: SMDK6400 has 12MHz input clock */ #define CONFIG_SYS_CLK_FREQ 12000000 -#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) +#if !defined(CONFIG_NAND_U_BOOT) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) #define CONFIG_ENABLE_MMU #endif -- 1.7.5.4

1 1

[U-Boot] [PATCH] arm: rmobile: kzm9g: Modify sdram area
by Tetsuyuki Kobayashi 05 Jul '12

05 Jul '12

This patch depends on Nobuhiro Iwamatsu's arm: rmobile: Add supoprt for KMC KZM-A9-GT board Reserve first 16MB for RT-CPU (as same as kernel config). Without this patch, kernel can't get ATAGS info from u-boot properly. Signed-off-by: Tetsuyuki Kobayashi <koba(a)kmckk.co.jp> --- include/configs/kzm_a9_gt.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/kzm_a9_gt.h b/include/configs/kzm_a9_gt.h index 48b7afa..4749ca7 100644 --- a/include/configs/kzm_a9_gt.h +++ b/include/configs/kzm_a9_gt.h @@ -93,8 +93,9 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_SDRAM_BASE KZM_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE +#define CONFIG_SDRAM_OFFSET_FOR_RT (1 * 16 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) +#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) -- 1.7.9.5

2 1