March 2012 - U-Boot

[U-Boot] [PATCH] pci: move pciauto_config_init() to pci.h
by Linus Walleij 04 Mar '12

04 Mar '12

Fixing build regressions for the Integrator I get find that a few boards try to work around the missing declaration of pciauto_config_init() by declaring it in the local scope. This does not make sense when the sibling functions are in <pci.h> so move the function to the header, ridding the build error in the Integrator and getting rid of the local declarations here and there. Reported-by: Wolfgang Denk <wd(a)denx.de> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- board/esd/cpci750/pci.c | 1 - board/prodrive/p3mx/pci.c | 1 - drivers/pci/fsl_pci_init.c | 1 - drivers/pci/pci.c | 1 - include/pci.h | 1 + 5 files changed, 1 insertions(+), 4 deletions(-) diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index a2c1c50..24ab13f 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -29,7 +29,6 @@ #include <pci.h> #ifdef CONFIG_PCI_PNP -void pciauto_config_init(struct pci_controller *hose); int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar); #endif diff --git a/board/prodrive/p3mx/pci.c b/board/prodrive/p3mx/pci.c index e36b676..712c21c 100644 --- a/board/prodrive/p3mx/pci.c +++ b/board/prodrive/p3mx/pci.c @@ -29,7 +29,6 @@ #include <pci.h> #ifdef CONFIG_PCI_PNP -void pciauto_config_init(struct pci_controller *hose); int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar); #endif diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index bff1314..d04a08c 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -51,7 +51,6 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus); void pciauto_postscan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus); -void pciauto_config_init(struct pci_controller *hose); #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS 0 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index bee2b52..007b850 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -518,7 +518,6 @@ void pci_cfgfunc_do_nothing(struct pci_controller *hose, * to get the correct result when scanning bridges */ extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); -extern void pciauto_config_init(struct pci_controller *hose); #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW) const char * pci_class_str(u8 class) diff --git a/include/pci.h b/include/pci.h index 1284c42..7d98ad4 100644 --- a/include/pci.h +++ b/include/pci.h @@ -527,6 +527,7 @@ extern void pciauto_setup_device(struct pci_controller *hose, struct pci_region *mem, struct pci_region *prefetch, struct pci_region *io); +extern void pciauto_config_init(struct pci_controller *hose); int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); -- 1.7.7.6

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[U-Boot] [PATCH] integrator: remove fragile delay loop from PCI code
by Linus Walleij 04 Mar '12

04 Mar '12

The reference implementation of the PCI initialization code almost everywhere contain this fragile loop of "a few usecs", and its use of volatile variables to delay a number of bus cycles is indeed uncertain. Reading the manual "Integrator/AP Users Guide", page 5-15 it is clearly stated: "Wait until 230ms after the end of the reset period before accessing V360EPC internal registers. The V360EPC supports the use of a serial configuration PROM and the software must wait for the device to detect the absence of this PROM before accessing any registers. The required delay is a function of the PCI Clock, but at the lower frequency (25MHz) is 230ms". So let's simply wait 230ms per the spec. This solves the compilation error that looked like this: pci.c: In function ‘pci_init_board’: pci.c:286:18: warning: variable ‘j’ set but not used Reported-by: Wolfgang Denk <wd(a)denx.de> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- board/armltd/integrator/pci.c | 7 ++----- 1 files changed, 2 insertions(+), 5 deletions(-) diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c index f040450..8ff88fe 100644 --- a/board/armltd/integrator/pci.c +++ b/board/armltd/integrator/pci.c @@ -283,17 +283,14 @@ struct pci_controller integrator_hose = { void pci_init_board(void) { - volatile int i, j; struct pci_controller *hose = &integrator_hose; u16 val; /* setting this register will take the V3 out of reset */ __raw_writel(SC_PCI_PCIEN, SC_PCI); - /* wait a few usecs to settle the device and the PCI bus */ - - for (i = 0; i < 100; i++) - j = i + 1; + /* Wait for 230 ms (from spec) before accessing any V3 registers */ + mdelay(230); /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16)); -- 1.7.7.6

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[U-Boot] EHCI host not issuing PING token before Bulk Out transaction for CBW
by Thomas Abraham 04 Mar '12

04 Mar '12

Hi, When using EHCI host, there seems to be no PING token issued before the mass storage CBW is issued on the USB Bulk OUT EP. There are some USB disks which are not responding to CBW sent to them even after issuing mass storage 'reset' request and clearing any EP stall (when using the EHCI host). Is it required by some USB disks to send a PING token before issuing a CBW on the USB Bulk OUT EP? If it is required, should u-boot EHCI host driver be issuing a PING token before CBW are sent on bulk out EP? Thanks, Thomas.

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[U-Boot] fs/fat alignment
by Eric Nelson 04 Mar '12

04 Mar '12

Note that checkpatch fails on this patch with the following warning, but I'm not sure how to resolve it. Nothing else in the U-Boot code base seems to use __align() although it's defined in include/linux/compiler-gcc.h. #46: FILE: fs/fat/fat.c:432: +__attribute__ ((__aligned__ (ARCH_DMA_MINALIGN))) WARNING: __aligned(size) is preferred over __attribute__((aligned(size))) #46: FILE: fs/fat/fat.c:432: +__attribute__ ((__aligned__ (ARCH_DMA_MINALIGN))) total: 0 errors, 2 warnings, 47 lines checked

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[U-Boot] [PATCH] i.MX6: mx6q_sabrelite: add SATA bindings
by Eric Nelson 03 Mar '12

03 Mar '12

This patch requires Stefano's driver for MX5/MX6. http://lists.denx.de/pipermail/u-boot/2012-February/118530.html Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> --- arch/arm/include/asm/arch-mx6/imx-regs.h | 11 +++++ board/freescale/mx6qsabrelite/mx6qsabrelite.c | 54 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 ++++++ 3 files changed, 78 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3e5c4c2..2441434 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -165,6 +165,17 @@ #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +/* + * ANATOP register definitions + */ +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_ENABLE_MASK 0x00002000 +#define ANATOP_PLL_BYPASS_MASK 0x00010000 +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_PWDN_MASK 0x00001000 +#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800 +#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000 + #define CHIP_REV_1_0 0x10 #define IRAM_SIZE 0x00040000 #define IMX_IIM_BASE OCOTP_BASE_ADDR diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 2786482..e0ba6a4 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -273,10 +273,64 @@ int board_eth_init(bd_t *bis) return 0; } +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + u32 reg = 0; + s32 timeout = 100000; + + /* Enable sata clock */ + reg = readl(CCM_BASE_ADDR + 0x7c); /* CCGR5 */ + reg |= 0x30; + writel(reg, CCM_BASE_ADDR + 0x7c); + + /* Enable PLLs */ + reg = readl(ANATOP_BASE_ADDR + 0xe0); /* ENET PLL */ + reg &= ~ANATOP_PLL_PWDN_MASK; + writel(reg, ANATOP_BASE_ADDR + 0xe0); + reg |= ANATOP_PLL_ENABLE_MASK; + while (timeout--) { + if (readl(ANATOP_BASE_ADDR + 0xe0) & ANATOP_PLL_LOCK) + break; + } + if (timeout <= 0) + return -1; + reg &= ~ANATOP_PLL_BYPASS_MASK; + writel(reg, ANATOP_BASE_ADDR + 0xe0); + reg |= ANATOP_SATA_CLK_ENABLE_MASK; + writel(reg, ANATOP_BASE_ADDR + 0xe0); + + /* Enable sata phy */ + reg = readl(IOMUXC_BASE_ADDR + 0x34); /* GPR13 */ + + reg &= ~0x07ffffff; + /* + * rx_eq_val_0 = 5 [26:24] == 3.0 dB + * los_lvl = 0x12 [23:19] == SATA2m + * rx_dpll_mode_0 = 0x3 [18:16] + * speed = 1 [15] == 3Gpbs + * mpll_ss_en = 0x0 [14] + * tx_atten_0 = 0x4 [13:11] + * tx_boost_0 = 0x0 [10:7] + * tx_lvl = 0x11 [6:2] == 1.104 V + * tx_edgerate_0 == 0x0 [0:1] + * */ + reg |= 0x0593a046; + writel(reg, IOMUXC_BASE_ADDR + 0x34); + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + return 0; } diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index a5dae73..01c6887 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -69,6 +69,19 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_SATA +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -- 1.7.9

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[U-Boot] [PATCH] integrator: rewrite the AP PCI driver
by Linus Walleij 03 Mar '12

03 Mar '12

The PCI support for the Integrator AP has apparently never been finished and I strongly suspect that it has never worked, so let's fix it. This is a list of the more or less un-splittable changes done in this driver rewrite: - Replace the register definitions stashed into the config file (!) with a copy if the register file from the Linux kernels arch/arm/include/asm/hardware/pci_v3.h - Delete the unreadable gigantic macros that perform the config accesses and replace them with copyedited code from Linux arch/arm/mach-integrator/pci_v3.c - Rewrite the rest of the setup code to use the v3_[read|write][lwb]() accessors. - Enable PCI by default in the AP board configuration. - Fix checkpatch warnings and make code more conformant. Tested-by: Will Deacon <will.deacon(a)arm.com> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- board/armltd/integrator/pci.c | 582 ++++++++++++++++++++++---------------- board/armltd/integrator/pci_v3.h | 200 +++++++++++++ include/configs/integratorap.h | 148 +--------- 3 files changed, 538 insertions(+), 392 deletions(-) create mode 100644 board/armltd/integrator/pci_v3.h diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c index 6ee2a85..f040450 100644 --- a/board/armltd/integrator/pci.c +++ b/board/armltd/integrator/pci.c @@ -14,6 +14,10 @@ * ARM Ltd. * Philippe Robin, <philippe.robin(a)arm.com> * + * (C) Copyright 2011 + * Linaro + * Linus Walleij <linus.walleij(a)linaro.org> + * * See file CREDITS for list of people who contributed to this * project. * @@ -32,15 +36,53 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include <common.h> #include <pci.h> +#include <asm/io.h> +#include "integrator-sc.h" +#include "pci_v3.h" + +#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 +#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 + +/* + * These are in the physical addresses on the CPU side, i.e. + * where we read and write stuff - you don't want to try to + * move these around + */ +#define PHYS_PCI_MEM_BASE 0x40000000 +#define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */ +#define PHYS_PCI_CONFIG_BASE 0x61000000 +#define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */ +#define SZ_256M 0x10000000 + +/* + * These are in the PCI BUS address space + * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor + * we follow the example of the kernel, because that is the address + * range that devices actually use - what would they be doing at + * 0x40000000? + */ +#define PCI_BUS_NONMEM_START 0x00000000 +#define PCI_BUS_NONMEM_SIZE SZ_256M + +#define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE) +#define PCI_BUS_PREMEM_SIZE SZ_256M + +#if PCI_BUS_NONMEM_START & 0x000fffff +#error PCI_BUS_NONMEM_START must be megabyte aligned +#endif +#if PCI_BUS_PREMEM_START & 0x000fffff +#error PCI_BUS_PREMEM_START must be megabyte aligned +#endif /* * Initialize PCI Devices, report devices found. */ #ifndef CONFIG_PCI_PNP +#define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */ +#define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */ static struct pci_config_table pci_integrator_config_table[] = { { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, @@ -51,163 +93,187 @@ static struct pci_config_table pci_integrator_config_table[] = { #endif /* CONFIG_PCI_PNP */ /* V3 access routines */ -#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v)) -#define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o))) - -#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v)) -#define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o))) - -/* Compute address necessary to access PCI config space for the given */ -/* bus and device. */ -#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \ - unsigned int __address, __devicebit; \ - unsigned short __mapaddress; \ - unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \ - \ - if (__bus == 0) { \ - /* local bus segment so need a type 0 config cycle */ \ - /* build the PCI configuration "address" with one-hot in A31-A11 */ \ - __address = PCI_CONFIG_BASE; \ - __address |= ((__devfn & 0x07) << 8); \ - __address |= __offset & 0xFF; \ - __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \ - __devicebit = (1 << (__dev + 11)); \ - \ - if ((__devicebit & 0xFF000000) != 0) { \ - /* high order bits are handled by the MAP register */ \ - __mapaddress |= (__devicebit >> 16); \ - } else { \ - /* low order bits handled directly in the address */ \ - __address |= __devicebit; \ - } \ - } else { /* bus !=0 */ \ - /* not the local bus segment so need a type 1 config cycle */ \ - /* A31-A24 are don't care (so clear to 0) */ \ - __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \ - __address = PCI_CONFIG_BASE; \ - __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \ - __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \ - __address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \ - __address |= __offset & 0xFF; /* bits 7..0 = register number */ \ - } \ - _V3Write16 (V3_LB_MAP1, __mapaddress); \ - __address; \ -}) - -/* _V3OpenConfigWindow - open V3 configuration window */ -#define _V3OpenConfigWindow() { \ - /* Set up base0 to see all 512Mbytes of memory space (not */ \ - /* prefetchable), this frees up base1 for re-use by configuration*/ \ - /* memory */ \ - \ - _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ - 0x90 | V3_LB_BASE_M_ENABLE)); \ - /* Set up base1 to point into configuration space, note that MAP1 */ \ - /* register is set up by pciMakeConfigAddress(). */ \ - \ - _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \ - 0x40 | V3_LB_BASE_M_ENABLE)); \ +#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) +#define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o))) + +#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) +#define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o))) + +#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) +#define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o))) + +static unsigned long v3_open_config_window(pci_dev_t bdf, int offset) +{ + unsigned int address, mapaddress; + unsigned int busnr = PCI_BUS(bdf); + unsigned int devfn = PCI_FUNC(bdf); + + /* + * Trap out illegal values + */ + if (offset > 255) + BUG(); + if (busnr > 255) + BUG(); + if (devfn > 255) + BUG(); + + if (busnr == 0) { + /* + * Linux calls the thing U-Boot calls "DEV" "SLOT" + * instead, but it's the same 5 bits + */ + int slot = PCI_DEV(bdf); + + /* + * local bus segment so need a type 0 config cycle + * + * build the PCI configuration "address" with one-hot in + * A31-A11 + * + * mapaddress: + * 3:1 = config cycle (101) + * 0 = PCI A1 & A0 are 0 (0) + */ + address = PCI_FUNC(bdf) << 8; + mapaddress = V3_LB_MAP_TYPE_CONFIG; + + if (slot > 12) + /* + * high order bits are handled by the MAP register + */ + mapaddress |= 1 << (slot - 5); + else + /* + * low order bits handled directly in the address + */ + address |= 1 << (slot + 11); + } else { + /* + * not the local bus segment so need a type 1 config cycle + * + * address: + * 23:16 = bus number + * 15:11 = slot number (7:3 of devfn) + * 10:8 = func number (2:0 of devfn) + * + * mapaddress: + * 3:1 = config cycle (101) + * 0 = PCI A1 & A0 from host bus (1) + */ + mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; + address = (busnr << 16) | (devfn << 8); + } + + /* + * Set up base0 to see all 512Mbytes of memory space (not + * prefetchable), this frees up base1 for re-use by + * configuration memory + */ + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); + + /* + * Set up base1/map1 to point into configuration space. + */ + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | + V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP1, mapaddress); + + return PHYS_PCI_CONFIG_BASE + address + offset; } -/* _V3CloseConfigWindow - close V3 configuration window */ -#define _V3CloseConfigWindow() { \ - /* Reassign base1 for use by prefetchable PCI memory */ \ - _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \ - | 0x84 | V3_LB_BASE_M_ENABLE)); \ - _V3Write16 (V3_LB_MAP1, \ - (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \ - \ - /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \ - \ - _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ - 0x80 | V3_LB_BASE_M_ENABLE)); \ +static void v3_close_config_window(void) +{ + /* + * Reassign base1 for use by prefetchable PCI memory + */ + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | + V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | + V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | + V3_LB_MAP_TYPE_MEM_MULTIPLE); + + /* + * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) + */ + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); } -static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev, - int offset, unsigned char *val) +static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf, + int offset, unsigned char *val) { - _V3OpenConfigWindow (); - *val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset); - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + *val = __raw_readb(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_read__word (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned short *val) +static int pci_integrator_read__word(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned short *val) { - _V3OpenConfigWindow (); - *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset); - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + *val = __raw_readw(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_read_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned int *val) +static int pci_integrator_read_dword(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned int *val) { - _V3OpenConfigWindow (); - *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset); - *val |= (*(volatile unsigned int *) - PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev), - (offset + 2))) << 16; - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + *val = __raw_readl(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_write_byte (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned char val) +static int pci_integrator_write_byte(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned char val) { - _V3OpenConfigWindow (); - *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset) = val; - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + __raw_writeb((u8)val, addr); + __raw_readb(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_write_word (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned short val) +static int pci_integrator_write_word(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned short val) { - _V3OpenConfigWindow (); - *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset) = val; - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + __raw_writew((u8)val, addr); + __raw_readw(addr); + v3_close_config_window(); return 0; } -static int pci_integrator_write_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, - unsigned int val) +static int pci_integrator_write_dword(struct pci_controller *hose, + pci_dev_t bdf, int offset, + unsigned int val) { - _V3OpenConfigWindow (); - *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - offset) = (val & 0xFFFF); - *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), - PCI_FUNC (dev), - (offset + 2)) = ((val >> 16) & 0xFFFF); - _V3CloseConfigWindow (); + unsigned long addr; + addr = v3_open_config_window(bdf, offset); + __raw_writel((u8)val, addr); + __raw_readl(addr); + v3_close_config_window(); return 0; } -/****************************** - * PCI initialisation - ******************************/ struct pci_controller integrator_hose = { #ifndef CONFIG_PCI_PNP @@ -215,182 +281,198 @@ struct pci_controller integrator_hose = { #endif }; -void pci_init_board (void) +void pci_init_board(void) { volatile int i, j; struct pci_controller *hose = &integrator_hose; + u16 val; /* setting this register will take the V3 out of reset */ - - *(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1; + __raw_writel(SC_PCI_PCIEN, SC_PCI); /* wait a few usecs to settle the device and the PCI bus */ for (i = 0; i < 100; i++) j = i + 1; - /* Now write the Base I/O Address Word to V3_BASE + 0x6C */ - - *(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) = - (unsigned short) (V3_BASE >> 16); + /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ + v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16)); + /* Wait for the mailbox to settle */ do { - *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA; - *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) = - 0x55; - } while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA - || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + - 4) != 0x55); + v3_writeb(V3_MAIL_DATA, 0xAA); + v3_writeb(V3_MAIL_DATA + 4, 0x55); + } while (v3_readb(V3_MAIL_DATA) != 0xAA || + v3_readb(V3_MAIL_DATA + 4) != 0x55); /* Make sure that V3 register access is not locked, if it is, unlock it */ + if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) + v3_writew(V3_SYSTEM, 0xA05F); - if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) & - V3_SYSTEM_M_LOCK) - == V3_SYSTEM_M_LOCK) - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F; - - /* Ensure that the slave accesses from PCI are disabled while we */ - /* setup windows */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &= - ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); + /* + * Ensure that the slave accesses from PCI are disabled while we + * setup memory windows + */ + val = v3_readw(V3_PCI_CMD); + val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); + v3_writew(V3_PCI_CMD, val); /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ - - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &= - ~V3_SYSTEM_M_RST_OUT; + val = v3_readw(V3_SYSTEM); + val &= ~V3_SYSTEM_M_RST_OUT; + v3_writew(V3_SYSTEM, val); /* Make all accesses from PCI space retry until we're ready for them */ + val = v3_readw(V3_PCI_CFG); + val |= V3_PCI_CFG_M_RETRY_EN; + v3_writew(V3_PCI_CFG, val); - *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |= - V3_PCI_CFG_M_RETRY_EN; - - /* Set up any V3 PCI Configuration Registers that we absolutely have to */ - /* LB_CFG controls Local Bus protocol. */ - /* Enable LocalBus byte strobes for READ accesses too. */ - /* set bit 7 BE_IMODE and bit 6 BE_OMODE */ - - *(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0; - - /* PCI_CMD controls overall PCI operation. */ - /* Enable PCI bus master. */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04; + /* + * Set up any V3 PCI Configuration Registers that we absolutely have to. + * LB_CFG controls Local Bus protocol. + * Enable LocalBus byte strobes for READ accesses too. + * set bit 7 BE_IMODE and bit 6 BE_OMODE + */ + val = v3_readw(V3_LB_CFG); + val |= 0x0C0; + v3_writew(V3_LB_CFG, val); - /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */ + /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */ + val = v3_readw(V3_PCI_CMD); + val |= V3_COMMAND_M_MASTER_EN; + v3_writew(V3_PCI_CMD, val); - *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) = - (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE); + /* + * PCI_MAP0 controls where the PCI to CPU memory window is on + * Local Bus + */ + v3_writel(V3_PCI_MAP0, + (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB | + V3_PCI_MAP_M_REG_EN | + V3_PCI_MAP_M_ENABLE)); /* PCI_BASE0 is the PCI address of the start of the window */ - - *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) = - INTEGRATOR_BOOT_ROM_BASE; + v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE); /* PCI_MAP1 is LOCAL address of the start of the window */ - - *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) = - (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M | - V3_PCI_MAP_M_REG_EN | - V3_PCI_MAP_M_ENABLE); + v3_writel(V3_PCI_MAP1, + (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB | + V3_PCI_MAP_M_REG_EN | + V3_PCI_MAP_M_ENABLE)); /* PCI_BASE1 is the PCI address of the start of the window */ + v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE); - *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) = - INTEGRATOR_HDR0_SDRAM_BASE; - - /* Set up the windows from local bus memory into PCI configuration, */ - /* I/O and Memory. */ - /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */ - - *(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) = - ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE; - *(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0; + /* + * Set up memory the windows from local bus memory into PCI + * configuration, I/O and Memory regions. + * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. + */ + v3_writew(V3_LB_BASE2, + v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP2, 0); /* PCI Configuration, use LB_BASE1/LB_MAP1. */ - /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */ - /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */ - /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */ - - *(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) = - INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE); - - *(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) = - ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006; + /* + * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 + * Map first 256Mbytes as non-prefetchable via BASE0/MAP0 + */ + v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | + V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP0, + v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM); /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ + v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | + V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | + V3_LB_BASE_ENABLE); + v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | + V3_LB_MAP_TYPE_MEM_MULTIPLE); + + /* Dump PCI to local address space mappings */ + debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0)); + debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0)); + debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1)); + debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1)); + debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2)); + debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2)); + debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE)); - *(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) = - INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE); - - *(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) = - (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006; - - /* Allow accesses to PCI Configuration space */ - /* and set up A1, A0 for type 1 config cycles */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) = - ((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) & - ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) | - V3_PCI_CFG_M_AD_LOW0; - - /* now we can allow in PCI MEMORY accesses */ - - *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) = - (*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) | - V3_COMMAND_M_MEM_EN; + /* + * Allow accesses to PCI Configuration space and set up A1, A0 for + * type 1 config cycles + */ + val = v3_readw(V3_PCI_CFG); + val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1); + val |= V3_PCI_CFG_M_AD_LOW0; + v3_writew(V3_PCI_CFG, val); - /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */ - /* initialise and lock the V3 system register so that no one else */ - /* can play with it */ + /* now we can allow incoming PCI MEMORY accesses */ + val = v3_readw(V3_PCI_CMD); + val |= V3_COMMAND_M_MEM_EN; + v3_writew(V3_PCI_CMD, val); - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = - (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | - V3_SYSTEM_M_RST_OUT; + /* + * Set RST_OUT to take the PCI bus is out of reset, PCI devices can + * now initialise. + */ + val = v3_readw(V3_SYSTEM); + val |= V3_SYSTEM_M_RST_OUT; + v3_writew(V3_SYSTEM, val); - *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = - (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | - V3_SYSTEM_M_LOCK; + /* Lock the V3 system register so that no one else can play with it */ + val = v3_readw(V3_SYSTEM); + val |= V3_SYSTEM_M_LOCK; + v3_writew(V3_SYSTEM, val); /* - * Register the hose + * Configure and register the PCI hose */ hose->first_busno = 0; hose->last_busno = 0xff; - /* System memory space */ - pci_set_region (hose->regions + 0, - 0x00000000, 0x40000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + /* System memory space, window 0 256 MB non-prefetchable */ + pci_set_region(hose->regions + 0, + PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE, + SZ_256M, + PCI_REGION_MEM); - /* PCI Memory - config space */ - pci_set_region (hose->regions + 1, - 0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM); - - /* PCI V3 regs */ - pci_set_region (hose->regions + 2, - 0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM); + /* System memory space, window 1 256 MB prefetchable */ + pci_set_region(hose->regions + 1, + PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M, + SZ_256M, + PCI_REGION_MEM | + PCI_REGION_PREFETCH); /* PCI I/O space */ - pci_set_region (hose->regions + 3, - 0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO); + pci_set_region(hose->regions + 2, + 0x00000000, PHYS_PCI_IO_BASE, 0x01000000, + PCI_REGION_IO); + + /* PCI Memory - config space */ + pci_set_region(hose->regions + 3, + 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000, + PCI_REGION_MEM); + /* PCI V3 regs */ + pci_set_region(hose->regions + 4, + 0x00000000, PHYS_PCI_V3_BASE, 0x01000000, + PCI_REGION_MEM); - pci_set_ops (hose, - pci_integrator_read_byte, - pci_integrator_read__word, - pci_integrator_read_dword, - pci_integrator_write_byte, - pci_integrator_write_word, pci_integrator_write_dword); + hose->region_count = 5; - hose->region_count = 4; + pci_set_ops(hose, + pci_integrator_read_byte, + pci_integrator_read__word, + pci_integrator_read_dword, + pci_integrator_write_byte, + pci_integrator_write_word, + pci_integrator_write_dword); - pci_register_hose (hose); + pci_register_hose(hose); - pciauto_config_init (hose); - pciauto_config_device (hose, 0); + pciauto_config_init(hose); + pciauto_config_device(hose, 0); - hose->last_busno = pci_hose_scan (hose); + hose->last_busno = pci_hose_scan(hose); } diff --git a/board/armltd/integrator/pci_v3.h b/board/armltd/integrator/pci_v3.h new file mode 100644 index 0000000..39a0c41 --- /dev/null +++ b/board/armltd/integrator/pci_v3.h @@ -0,0 +1,200 @@ +/* + * arch/arm/include/asm/hardware/pci_v3.h + * + * Internal header file PCI V3 chip + * + * Copyright (C) ARM Limited + * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef ASM_ARM_HARDWARE_PCI_V3_H +#define ASM_ARM_HARDWARE_PCI_V3_H + +/* ------------------------------------------------------------------------------- + * V3 Local Bus to PCI Bridge definitions + * ------------------------------------------------------------------------------- + * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 + * All V3 register names are prefaced by V3_ to avoid clashing with any other + * PCI definitions. Their names match the user's manual. + * + * I'm assuming that I20 is disabled. + * + */ +#define V3_PCI_VENDOR 0x00000000 +#define V3_PCI_DEVICE 0x00000002 +#define V3_PCI_CMD 0x00000004 +#define V3_PCI_STAT 0x00000006 +#define V3_PCI_CC_REV 0x00000008 +#define V3_PCI_HDR_CFG 0x0000000C +#define V3_PCI_IO_BASE 0x00000010 +#define V3_PCI_BASE0 0x00000014 +#define V3_PCI_BASE1 0x00000018 +#define V3_PCI_SUB_VENDOR 0x0000002C +#define V3_PCI_SUB_ID 0x0000002E +#define V3_PCI_ROM 0x00000030 +#define V3_PCI_BPARAM 0x0000003C +#define V3_PCI_MAP0 0x00000040 +#define V3_PCI_MAP1 0x00000044 +#define V3_PCI_INT_STAT 0x00000048 +#define V3_PCI_INT_CFG 0x0000004C +#define V3_LB_BASE0 0x00000054 +#define V3_LB_BASE1 0x00000058 +#define V3_LB_MAP0 0x0000005E +#define V3_LB_MAP1 0x00000062 +#define V3_LB_BASE2 0x00000064 +#define V3_LB_MAP2 0x00000066 +#define V3_LB_SIZE 0x00000068 +#define V3_LB_IO_BASE 0x0000006E +#define V3_FIFO_CFG 0x00000070 +#define V3_FIFO_PRIORITY 0x00000072 +#define V3_FIFO_STAT 0x00000074 +#define V3_LB_ISTAT 0x00000076 +#define V3_LB_IMASK 0x00000077 +#define V3_SYSTEM 0x00000078 +#define V3_LB_CFG 0x0000007A +#define V3_PCI_CFG 0x0000007C +#define V3_DMA_PCI_ADR0 0x00000080 +#define V3_DMA_PCI_ADR1 0x00000090 +#define V3_DMA_LOCAL_ADR0 0x00000084 +#define V3_DMA_LOCAL_ADR1 0x00000094 +#define V3_DMA_LENGTH0 0x00000088 +#define V3_DMA_LENGTH1 0x00000098 +#define V3_DMA_CSR0 0x0000008B +#define V3_DMA_CSR1 0x0000009B +#define V3_DMA_CTLB_ADR0 0x0000008C +#define V3_DMA_CTLB_ADR1 0x0000009C +#define V3_DMA_DELAY 0x000000E0 +#define V3_MAIL_DATA 0x000000C0 +#define V3_PCI_MAIL_IEWR 0x000000D0 +#define V3_PCI_MAIL_IERD 0x000000D2 +#define V3_LB_MAIL_IEWR 0x000000D4 +#define V3_LB_MAIL_IERD 0x000000D6 +#define V3_MAIL_WR_STAT 0x000000D8 +#define V3_MAIL_RD_STAT 0x000000DA +#define V3_QBA_MAP 0x000000DC + +/* PCI COMMAND REGISTER bits + */ +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) + +/* SYSTEM REGISTER bits + */ +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) + +/* PCI_CFG bits + */ +#define V3_PCI_CFG_M_I2O_EN (1 << 15) +#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) +#define V3_PCI_CFG_M_IO_DIS (1 << 13) +#define V3_PCI_CFG_M_EN3V (1 << 12) +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) + +/* PCI_BASE register bits (PCI -> Local Bus) + */ +#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 +#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 +#define V3_PCI_BASE_M_PREFETCH (1 << 3) +#define V3_PCI_BASE_M_TYPE (3 << 1) +#define V3_PCI_BASE_M_IO (1 << 0) + +/* PCI MAP register bits (PCI -> Local bus) + */ +#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (3 << 10) +#define V3_PCI_MAP_M_SWAP (3 << 8) +#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) + +#define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4) +#define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4) + +/* + * LB_BASE0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_BASE_ADR_BASE 0xfff00000 +#define V3_LB_BASE_SWAP (3 << 8) +#define V3_LB_BASE_ADR_SIZE (15 << 4) +#define V3_LB_BASE_PREFETCH (1 << 3) +#define V3_LB_BASE_ENABLE (1 << 0) + +#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) +#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) +#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) +#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) +#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) +#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) +#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) +#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) +#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) +#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) +#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) +#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) + +#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) + +/* + * LB_MAP0,1 register bits (Local bus -> PCI) + */ +#define V3_LB_MAP_MAP_ADR 0xfff0 +#define V3_LB_MAP_TYPE (7 << 1) +#define V3_LB_MAP_AD_LOW_EN (1 << 0) + +#define V3_LB_MAP_TYPE_IACK (0 << 1) +#define V3_LB_MAP_TYPE_IO (1 << 1) +#define V3_LB_MAP_TYPE_MEM (3 << 1) +#define V3_LB_MAP_TYPE_CONFIG (5 << 1) +#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) + +/* PCI MAP register bits (PCI -> Local bus) */ +#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) + +/* + * LB_BASE2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_BASE2_ADR_BASE 0xff00 +#define V3_LB_BASE2_SWAP (3 << 6) +#define V3_LB_BASE2_ENABLE (1 << 0) + +#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) + +/* + * LB_MAP2 register bits (Local bus -> PCI IO) + */ +#define V3_LB_MAP2_MAP_ADR 0xff00 + +#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) + +#endif diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index d4cb3dd..6f8c3b1 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -83,17 +83,7 @@ /* * Command line configuration. */ - - -#define CONFIG_CMD_IMI -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMLS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS - +#include <config_cmd_default.h> #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty" @@ -158,142 +148,16 @@ * PCI definitions */ -#ifdef CONFIG_PCI /* pci support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define DEBUG +#define CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_PCI_PNP +#define CONFIG_NET_MULTI +#define CONFIG_TULIP #define CONFIG_EEPRO100 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 - -/* PCI Base area */ -#define INTEGRATOR_PCI_BASE 0x40000000 -#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF - -/* memory map as seen by the CPU on the local bus */ -#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ -#define CPU_PCI_IO_SIZE 0x10000 - -#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ -#define CPU_PCI_CNFG_SIZE 0x1000000 - -#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ -/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ -#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ -/* unused (128-16)M from B1000000-B7FFFFFF */ -#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ -/* unused ((128-16)M - 64K) from XXX */ - -#define PCI_V3_BASE 0x62000000 - -/* V3 PCI bridge controller */ -#define V3_BASE 0x62000000 /* V360EPC registers */ - -#define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS) -#define PCI_ENET0_MEMADDR (PCI_MEM_BASE) - - -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CF 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC - -/* SYSTEM register bits */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) - -/* PCI_CFG bits */ -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) - -/* PCI MAP register bits (PCI -> Local bus) */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) -#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) - -/* 9 => 512M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 - -/* A => 1024M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 - -/* LB_BASE register bits (Local bus -> PCI) */ -#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 -#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) -#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 -#define V3_LB_BASE_M_PREFETCH (1 << 3) -#define V3_LB_BASE_M_ENABLE (1 << 0) - -/* PCI COMMAND REGISTER bits */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) - -#define INTEGRATOR_SC_BASE 0x11000000 -#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 -#define INTEGRATOR_SC_PCIENABLE \ - (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) -#endif /* CONFIG_PCI */ /*----------------------------------------------------------------------- * There are various dependencies on the core module (CM) fitted * Users should refer to their CM user guide -- 1.7.7.6

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[U-Boot] Have there been any toughs of adding exFAT file system support?
by Andreas Bäck 03 Mar '12

03 Mar '12

More and more people are starting to use exFat on their usb sticks especially now when windows starts to be the majority of instalations

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[U-Boot] [PATCH 1/2] i.MX28: Do data transfers via DMA in MMC driver
by Marek Vasut 03 Mar '12

03 Mar '12

Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Andy Fleming <afleming(a)gmail.com> Cc: Fabio Estevam <festevam(a)gmail.com> --- drivers/mmc/mxsmmc.c | 52 ++++++++++++++++++++++--------------------------- 1 files changed, 23 insertions(+), 29 deletions(-) diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 5f87a1e..fcd39a1 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -41,6 +41,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/dma.h> struct mxsmmc_priv { int id; @@ -49,6 +50,7 @@ struct mxsmmc_priv { uint32_t *clkctrl_ssp; uint32_t buswidth; int (*mmc_is_wp)(int); + struct mxs_dma_desc *desc; }; #define MXSMMC_MAX_TIMEOUT 10000 @@ -65,7 +67,6 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) uint32_t reg; int timeout; uint32_t data_count; - uint32_t *data_ptr; uint32_t ctrl0; debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx); @@ -183,37 +184,22 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (!data) return 0; - /* Process the data */ data_count = data->blocksize * data->blocks; - timeout = MXSMMC_MAX_TIMEOUT; + if (data->flags & MMC_DATA_READ) { - data_ptr = (uint32_t *)data->dest; - while (data_count && --timeout) { - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & SSP_STATUS_FIFO_EMPTY)) { - *data_ptr++ = readl(&ssp_regs->hw_ssp_data); - data_count -= 4; - timeout = MXSMMC_MAX_TIMEOUT; - } else - udelay(1000); - } + priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE; + priv->desc->cmd.address = (dma_addr_t)data->dest; } else { - data_ptr = (uint32_t *)data->src; - timeout *= 100; - while (data_count && --timeout) { - reg = readl(&ssp_regs->hw_ssp_status); - if (!(reg & SSP_STATUS_FIFO_FULL)) { - writel(*data_ptr++, &ssp_regs->hw_ssp_data); - data_count -= 4; - timeout = MXSMMC_MAX_TIMEOUT; - } else - udelay(1000); - } + priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ; + priv->desc->cmd.address = (dma_addr_t)data->src; } - if (!timeout) { - printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n", - mmc->block_dev.dev, cmd->cmdidx, reg); + priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | + (data_count << MXS_DMA_DESC_BYTES_OFFSET); + + mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc); + if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) { + printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev); return COMM_ERR; } @@ -270,7 +256,8 @@ static int mxsmmc_init(struct mmc *mmc) /* 8 bits word length in MMC mode */ clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK, - SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); + SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | + SSP_CTRL1_DMA_ENABLE); /* Set initial bit clock 400 KHz */ mx28_set_ssp_busclock(priv->id, 400); @@ -300,6 +287,13 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) return -ENOMEM; } + priv->desc = mxs_dma_desc_alloc(); + if (!priv->desc) { + free(priv); + free(mmc); + return -ENOMEM; + } + priv->mmc_is_wp = wp; priv->id = id; switch (id) { @@ -345,7 +339,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) */ mmc->f_min = 400000; mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2; - mmc->b_max = 0; + mmc->b_max = 0x40; mmc_register(mmc); return 0; -- 1.7.9

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[U-Boot] [PATCH] Revert "nand: make 1-bit software ECC configurable"
by Scott Wood 03 Mar '12

03 Mar '12

This reverts commit 4fee6c2f295f932b8febdc7ce8731ba045695fa5. It breaks boards that currently rely on soft-ecc, as pointed out here: http://patchwork.ozlabs.org/patch/140872/ The reverted patch should be resubmitted with documentation, and with the CONFIG_MTD_ECC_SOFT selected from every board that needs it. We could start by looking at what NAND driver the board selects, and whether that driver ever asks for soft ECC. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- drivers/mtd/nand/Makefile | 2 +- drivers/mtd/nand/nand_base.c | 4 ---- include/linux/mtd/nand_ecc.h | 25 ------------------------- 3 files changed, 1 insertions(+), 30 deletions(-) diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 998fc73..1d1b628 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -39,7 +39,7 @@ COBJS-y += nand_bbt.o COBJS-y += nand_ids.o COBJS-y += nand_util.o endif -COBJS-$(CONFIG_MTD_ECC_SOFT) += nand_ecc.o +COBJS-y += nand_ecc.o COBJS-y += nand_base.o COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 12b960f..8ab8303 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -3028,10 +3028,6 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.mode = NAND_ECC_SOFT; case NAND_ECC_SOFT: - if (!mtd_nand_has_ecc_soft()) { - printk(KERN_WARNING "CONFIG_MTD_ECC_SOFT not enabled\n"); - return -EINVAL; - } chip->ecc.calculate = nand_calculate_ecc; chip->ecc.correct = nand_correct_data; chip->ecc.read_page = nand_read_page_swecc; diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h index 9715a53..090da50 100644 --- a/include/linux/mtd/nand_ecc.h +++ b/include/linux/mtd/nand_ecc.h @@ -15,10 +15,6 @@ struct mtd_info; -#if defined(CONFIG_MTD_ECC_SOFT) - -static inline int mtd_nand_has_ecc_soft(void) { return 1; } - /* * Calculate 3 byte ECC code for 256 byte block */ @@ -29,25 +25,4 @@ int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code */ int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); -#else - -static inline int mtd_nand_has_ecc_soft(void) { return 0; } - -static inline int -nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) -{ - return -1; -} - -static inline int -nand_correct_data(struct mtd_info *mtd, - u_char *dat, - u_char *read_ecc, - u_char *calc_ecc) -{ - return -1; -} - -#endif - #endif /* __MTD_NAND_ECC_H__ */ -- 1.7.7.rc3.4.g8d714

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[U-Boot] [PATCH] [PATCH] net/eth.c: Avoid Warning when ethxaddr is not set
by Gwenhael Goavec-Merou 03 Mar '12

03 Mar '12

The return value for eth_getenv_enetaddr_by_index produces a Warning when ethXaddr is not set (env_enetaddr is equal to 00:00:00:00:00:00). The validity of the mac address is tested later in this function to avoid to write an erroneous address. The test of the function's return is consequently useless and adds a warning. Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou(a)armadeus.com> --- net/eth.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/net/eth.c b/net/eth.c index b4b9b43..1e61aed 100644 --- a/net/eth.c +++ b/net/eth.c @@ -175,8 +175,7 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name, unsigned char env_enetaddr[6]; int ret = 0; - if (!eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr)) - return -1; + (void)eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr); if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { if (memcmp(dev->enetaddr, "\0\0\0\0\0\0", 6) && -- 1.7.3.4

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