March 2012 - U-Boot

[U-Boot] [PATCH v2] README.mx28: add
by Otavio Salvador 21 Mar '12

21 Mar '12

This is mainline a copy of README.m28 changing the references to the mx28 counterpart but it makes easy for people looking for information about mx28 based boards. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- doc/README.mx28 | 152 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 152 insertions(+), 0 deletions(-) create mode 100644 doc/README.mx28 diff --git a/doc/README.mx28 b/doc/README.mx28 new file mode 100644 index 0000000..a68ad72 --- /dev/null +++ b/doc/README.mx28 @@ -0,0 +1,152 @@ +Freescale MX28EVK +================= + +This document describes the Freescale MX28EVK U-Boot port. This document mostly +covers topics related to making the module/board bootable. + +Terminology +----------- + +The dollar symbol ($) introduces a snipped of shell code. This shall be typed +into the unix command prompt in U-Boot source code root directory. + +The (=>) introduces a snipped of code that should by typed into U-Boot command +prompt. + +Contents +-------- + +0) Files of the MX28EVK port +1) Prerequisites +2) Compiling U-Boot for MX28EVK +3) Installation of U-Boot for MX28EVK to SD card + +0) Files of the MX28EVK port +---------------------------- + +arch/arm/cpu/arm926ejs/mx28/ - The CPU support code for the Freescale i.MX28 +arch/arm/include/asm/arch-mx28/ - Header files for the Freescale i.MX28 +board/denx/mx28evk/ - MX28EVK board specific files +include/configs/mx28evk.h - MX28EVK configuration file + +1) Prerequisites +---------------- + +To make the MX28EVK board bootable, some tools are necessary. The first one is +the "elftosb" tool distributed by Freescale Semiconductor. The other tool is the +"mxsboot" tool found in U-Boot source tree. + +Firstly, obtain the elftosb archive from the following location: + + http://foss.doredevelopment.dk/mirrors/imx/elftosb-10.12.01.tar.gz + +We use a $VER variable here to denote the current version. At the time of +writing of this document, that is "10.12.01". To obtain the file from command +line, use: + + $ VER="10.12.01" + $ wget http://foss.doredevelopment.dk/mirrors/imx/elftosb-${VER}.tar.gz + +Extract the file: + + $ tar xzf elftosb-${VER}.tar.gz + +Compile the file. We need to manually tell the linker to use also libm: + + $ cd elftosb-${VER}/ + $ make LIBS="-lstdc++ -lm" elftosb + +Optionally, remove debugging symbols from elftosb: + + $ strip bld/linux/elftosb + +Finally, install the "elftosb" binary. The "install" target is missing, so just +copy the binary by hand: + + $ sudo cp bld/linux/elftosb /usr/local/bin/ + +Make sure the "elftosb" binary can be found in your $PATH, in this case this +means "/usr/local/bin/" has to be in your $PATH. + +2) Compiling U-Boot for MX28 +---------------------------- + +Compiling the U-Boot for MX28 is straightforward and done as compiling U-Boot +for any other ARM device. For cross-compiler setup, please refer to ELDK5.0 +documentation. First, clean up the source code: + + $ make mrproper + +Next, configure U-Boot for MX28EVK: + + $ make mx28evk_config + +Lastly, compile U-Boot and prepare a "BootStream". The "BootStream" is a special +type of file, which the i.MX28 CPU can boot. This is handled by the following +command: + + $ make u-boot.sb + +HINT: To speed-up the build process, you can add -j<N>, where N is number of + compiler instances that'll run in parallel. + +The code produces "u-boot.sb" file. This file needs to be augmented with a +proper header to allow successful boot from SD or NAND. Adding the header is +discussed in the following chapters. + +3) Installation of U-Boot for MX28EVK to SD card +------------------------------------------------ + +To boot an MX28 from SD, set the boot mode DIP switches as: + + * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42) + * JTAG PSWITCH RESET: To the left (reset enabled) + * Battery Source: Down + * Wall 5V: Up + * VDD 5V: To the left (off) + * Hold Button: Down (off) + +Full reference at i.MX28 manual chapter 12.2.1 (Table 12-2). + +An SD card that can be used to boot U-Boot on a i.MX28 CPU must contain a DOS +partition table, which in turn carries a partition of special type and which +contains a special header. The rest of partitions in the DOS partition table can +be used by the user. + +To prepare such partition, use your favourite partitioning tool. The partition +must have the following parameters: + + * Start sector .......... sector 2048 + * Partition size ........ at least 1024 kb + * Partition type ........ 0x53 (sometimes "OnTrack DM6 Aux3") + +For example in Linux fdisk, the sequence for a clear card follows. Be sure to +run fdisk with the option "-u=sectors" to set units to sectors: + + * o ..................... create a clear partition table + * n ..................... create new partition + * p ............. primary partition + * 1 ............. first partition + * 2048 .......... first sector is 2048 + * +1M ........... make the partition 1Mb big + * t 1 ................... change first partition ID + * 53 ............ change the ID to 0x53 (OnTrack DM6 Aux3) + * <create other partitions> + * w ..................... write partition table to disk + +The partition layout is ready, next the special partition must be filled with +proper contents. The contents is generated by running the following command (see +chapter 2)): + + $ ./tools/mxsboot sd u-boot.sb u-boot.sd + +The resulting file, "u-boot.sd", shall then be written to the partition. In this +case, we assume the first partition of the SD card is /dev/mmcblk0p1: + + $ dd if=u-boot.sd of=/dev/mmcblk0p1 + +Last step is to insert the card into MX28EVK and boot. + +NOTE: If the user needs to adjust the start sector, the "mxsboot" tool contains + a "-p" switch for that purpose. The "-p" switch takes the sector number as + an argument. -- 1.7.9.1

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[U-Boot] [BUG] cfi_flash can't work correctly on latest uboot
by Bob Liu 21 Mar '12

21 Mar '12

Hi, folks I think this patch make cfi_flash can't work correctly. http://git.denx.de/?p=u-boot.git;a=commitdiff;h=df4e813b72bf07d9026b00455f5… --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1426,6 +1426,11 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) #endif }; + /* + * Flash needs to be in status register read mode for + * flash_full_status_check() to work correctly + */ + flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); -------------------------------------- without this line, flash can't be recognized. So it's correct here. U-Boot 2011.09-svn2735 (ADI-2012R1-pre) (Nov 02 2011 - 15:05:23) CPU: ADSP bf526-0.0 (Detected Rev: 0.2) (parallel flash boot) Board: ADI BF526 EZ-Board board Support: http://blackfin.uclinux.org/ Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz RAM: 64 MiB Flash: Flash protect timeout at address 20004000 data 1520ff01 Flash protect error at address 20004000 Vpp Low Error. 4 MiB Flash protect timeout at address 20000000 data 1520ff01 Flash protect error at address 20000000 Flash protect timeout at address 20002000 data 1520ff01 Flash protect error at address 20002000 Block locked. Vpp Low Error. Flash protect timeout at address 20004000 data 1520ff01 Flash protect error at address 20004000 Vpp Low Error. Flash protect timeout at address 20006000 data 1520ff01 Flash protect error at address 20006000 Flash protect timeout at address 20008000 data 1520ff01 Flash protect error at address 20008000 Block locked. Vpp Low Error. Flash protect timeout at address 2000a000 data 1520ff01 Flash protect error at address 2000a000 Block locked. Vpp Low Error. Flash protect timeout at address 2000c000 data 1520ff01 Flash protect error at address 2000c000 Vpp Low Error. Flash protect timeout at address 2000e000 data 1520ff01 Flash protect error at address 2000e000 Block Erase Error. -------------------------------------- if ((retcode = flash_full_status_check (info, sector, info->erase_blk_tout, prot ? "protect" : "unprotect")) == 0) { @@ -1975,6 +1980,13 @@ ulong flash_get_size (phys_addr_t base, int banknum) case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: + /* + * Set flash to read-id mode. Otherwise + * reading protected status is not + * guaranteed. + */ + flash_write_cmd(info, sect_cnt, 0, + FLASH_CMD_READ_ID); ---------------------------------------------------------------------------- But with this two lines. flash ops are not correct. I used old uboot version to read out data from flash. Then tftpboot and run with latest uboot version, you can see that the read out data from flash is different. And without set flash to read-id mode here, it works fine. U-Boot 2010.06 (ADI-2010R1-RC2) (Oct 20 2010 - 04:37:34) CPU: ADSP bf526-0.0 (Detected Rev: 0.2) (parallel flash boot) Board: ADI BF526 EZ-Board board Support: http://blackfin.uclinux.org/ Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz RAM: 64 MiB Flash: 4 MiB In: serial Out: serial Err: serial KGDB: [on serial] ready Net: bfin_mac Hit any key to stop autoboot: 0 bfin> bfin> md 0x20100000 20100000: 56190527 0b223987 d60baf4e 2e871c00 '..V.9".N....... 20100010: 00100000 c42c1c00 a86adb94 01021005 ......,...j..... 20100020: 32356662 2e302d36 2e332d30 2d382e30 bf526-0.0-3.0.8- 20100030: 2d494441 31313032 702d3152 732d6572 ADI-2011R1-pre-s 20100040: 00088b1f 00000000 fdc40302 4514780b .............x.E 20100050: 570e38d6 3d33264f 24f48743 0649d303 .8.WO&3=C..$..I. 20100060: 93080932 834e9970 0931141a 648443a0 2...p.N...1..C.d 20100070: e0804212 12048762 56501a34 086bb2f1 .B..b...4.PV..k. 20100080: 66e0888a d9782808 d165049d 75049945 ...f.(x...e.E..u 20100090: 31415041 ba02cba2 aebbb2ae 8093d34b APA1........K... 201000a0: 682f1a8a 9cffceb8 105ceeea 7f7df77d ../h......\.}.}. 201000b0: 3c7cf3df 3aea984f 9d554ea7 4e753aaa ..|<O..:.NU..:uN 201000c0: b1a94e5d b13ae91e cc436dbe 749b42c2 ]N....:..mC..B.t 201000d0: fa449283 2aa2ec29 a82e0846 b7089ae5 ..D.)..*F....... 201000e0: cc1f9dc4 a9920651 113e5122 b1122213 ....Q..."Q>..".. 201000f0: 308f15a9 b6496a6a 12562598 49a8c8af ...0jjI..%V....I bfin> tftpboot 0x1000 u-boot.bin Using bfin_mac device TFTP from server 10.100.4.174; our IP address is 10.100.4.50 Filename 'u-boot.bin'. Load address: 0x1000 Loading: ############### done Bytes transferred = 213828 (34344 hex) bfin> go 0x1000 ## Starting application at 0x00001000 ... U-Boot 2011.09-svn2735 (ADI-2012R1-pre) (Nov 02 2011 - 15:15:05) CPU: ADSP bf526-0.0 (Detected Rev: 0.2) (parallel flash boot) Board: ADI BF526 EZ-Board board Support: http://blackfin.uclinux.org/ Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz RAM: 64 MiB Flash: 4 MiB In: serial Out: serial Err: serial KGDB: [on serial] ready Net: bfin_mac Hit any key to stop autoboot: 0 bfin> md 0x20100000 20100000: 88150020 ffff0001 bfcfffff ffffffff ............... 20100010: ffffffff ffffffff ffffffff ffffffff ................ 20100020: 00520051 00030059 00390000 00000000 Q.R.Y.....9..... 20100030: 00000000 00170000 00850020 00040095 ........ ....... 20100040: 000a0000 00030000 00020000 00160000 ................ 20100050: 00000001 00000000 00070002 00200000 .............. . 20100060: 003e0000 00000000 ffff0001 ffffffff ..>............. 20100070: 0050ffff 00490052 00330031 000300e6 ..P.R.I.1.3..... 20100080: 00000000 00030001 00180000 00010090 ................ 20100090: 00000080 00040003 00040003 00020001 ................ 201000a0: 00070003 00010002 00110000 00000000 ................ 201000b0: 00070002 00200000 00640000 00010000 ...... ...d..... 201000c0: 00060003 00000000 00640001 00010000 ..........d..... 201000d0: 00070003 00110000 00000000 00070001 ................ 201000e0: 00000000 00640001 00010000 ffff0003 ......d......... 201000f0: ffffffff ffffffff ffffffff ffffffff ................ bfin> flinfo Bank # 1: CFI conformant flash (16 x 16) Size: 4 MB in 71 Sectors Intel Standard command set, Manufacturer ID: 0x20, Device ID: 0x8815 Erase timeout: 4096 ms, write timeout: 1 ms Sector Start Addresses: 20000000 RO 20002000 RO 20004000 RO 20006000 RO 20008000 RO 2000A000 RO 2000C000 RO 2000E000 RO 20010000 RO 20020000 RO 20030000 RO 20040000 RO 20050000 RO 20060000 RO 20070000 RO 20080000 RO 20090000 RO 200A0000 RO 200B0000 RO 200C0000 RO 200D0000 RO 200E0000 RO 200F0000 RO 20100000 RO 20110000 RO 20120000 RO 20130000 RO 20140000 RO 20150000 RO 20160000 RO 20170000 RO 20180000 RO 20190000 RO 201A0000 RO 201B0000 RO 201C0000 RO 201D0000 RO 201E0000 RO 201F0000 RO 20200000 RO 20210000 RO 20220000 RO 20230000 RO 20240000 RO 20250000 RO 20260000 RO 20270000 RO 20280000 RO 20290000 RO 202A0000 RO 202B0000 RO 202C0000 RO 202D0000 RO 202E0000 RO 202F0000 RO 20300000 RO 20310000 RO 20320000 RO 20330000 RO 20340000 RO 20350000 RO 20360000 RO 20370000 RO 20380000 RO 20390000 RO 203A0000 RO 203B0000 RO 203C0000 RO 203D0000 RO 203E0000 RO 203F0000 RO bfin> ---------------------------------------------------------------------------- info->protect[sect_cnt] = flash_isset (info, sect_cnt, FLASH_OFFSET_PROTECT, -- Regards, --Bob

2 1

[U-Boot] How to specify the TEXT_BASE
by jingchaotian6 21 Mar '12

21 Mar '12

Hi All, I am working on the porting of uboot at freescale MPC8360, now stuck on the address TEXT_BASE. in our board, the address of Nor Flash is 0xfc00_0000-0xffff_ffff, the high 1MB from 0xfff0_0000 is used for boot rom. could you instruct me how to specify the TEXT_BASE? is the same to the 0xfc00_0000 ? in addition, the region of SDRAM is 0x0000_0000 to 0x0fff_ffff. Besd regards, -Peter

1 0

[U-Boot] Bug in cfb_console driver
by Pali Rohár 21 Mar '12

21 Mar '12

Hello, commit 03d31fcf4c37d90a00e66f06b38742960139f090 break video framebuffer output on Nokia N900. After this commit is video output garbaged and not readable on display. Problem is in function video_invertchar() - when I commented it, video output is OK, but without cursor. Problem is only on real N900 device, not in qemu. -- Pali Rohár pali.rohar(a)gmail.com

2 7

[U-Boot] [PATCH v2] add new board nas62x0
by Luka Perkov 21 Mar '12

21 Mar '12

Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220 boards. Only difference between boards is number of SATA ports. By default we use only one SATA port. Signed-off-by: Luka Perkov <uboot(a)lukaperkov.net> Signed-off-by: Gerald Kerma <dreagle(a)doukki.net> --- Changes from version v1: * use tools/checkpatch.pl to locate patch errors and fix them * add two entries in boards.cfg, one for each board * fixed CONFIG_RESET_PHY_R * don't define values for macros that enable features only * remove static RAM configuration * fix comments * use only CONFIG_ENV_OFFSET and remove CONFIG_ENV_ADDR * clean coding style * add entry in MAINTAINERS file I will send README for booting from UART in separate patch, but before I do that can somebody please look at: http://www.solinno.co.uk/public/kwuartboot/ http://www.solinno.co.uk/public/kwuartboot/kwuartboot-0.1.tar.gz I have 100% success rate, even the author states he had only 75%. Does including this tool in uboot tools/ make sense? Anybody want to give it a try on another kirkwood board? MAINTAINERS | 4 + board/Marvell/ib62x0/Makefile | 51 +++++++++++ board/Marvell/ib62x0/ib62x0.c | 114 ++++++++++++++++++++++++ board/Marvell/ib62x0/ib62x0.h | 41 +++++++++ board/Marvell/ib62x0/kwbimage.cfg | 167 +++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/ib62x0.h | 176 +++++++++++++++++++++++++++++++++++++ 7 files changed, 555 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46f63a0..11d023e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -782,6 +782,10 @@ Linus Walleij <linus.walleij(a)linaro.org> integratorap various integratorcp various +Luka Perkov <uboot(a)lukaperkov.net> + + ib62x0 ARM926EJS + Dave Peverley <dpeverley(a)mpc-data.co.uk> omap730p2 ARM926EJS diff --git a/board/Marvell/ib62x0/Makefile b/board/Marvell/ib62x0/Makefile new file mode 100644 index 0000000..3d82f27 --- /dev/null +++ b/board/Marvell/ib62x0/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ib62x0.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/ib62x0/ib62x0.c b/board/Marvell/ib62x0/ib62x0.c new file mode 100644 index 0000000..2b7762a --- /dev/null +++ b/board/Marvell/ib62x0/ib62x0.c @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2011 Gérald Kerma <dreagle(a)doukki.net> + * + * Written-by: Gérald Kerma <dreagle(a)doukki.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "ib62x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_UART0_RTS, + MPP9_UART0_CTS, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, /* Power LED red */ + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, /* Power LED green */ + MPP26_GPIO, + MPP27_GPIO, /* USB transfer LED */ + MPP28_GPIO, /* Reset button */ + MPP29_TSMP9, /* USB Copy button */ + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NAS6210; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/Marvell/ib62x0/ib62x0.h b/board/Marvell/ib62x0/ib62x0.h new file mode 100644 index 0000000..b26a257 --- /dev/null +++ b/board/Marvell/ib62x0/ib62x0.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2011 Gérald Kerma <dreagle(a)doukki.net> + * + * Written-by: Gérald Kerma <dreagle(a)doukki.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __IB62x0_H +#define __IB62x0_H + +#define IB62x0_OE_LOW (~(0)) +#define IB62x0_OE_HIGH (~(0)) +#define IB62x0_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ +#define IB62x0_OE_VAL_HIGH (1 << 17) /* LED pin high */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __IB62x0_H */ diff --git a/board/Marvell/ib62x0/kwbimage.cfg b/board/Marvell/ib62x0/kwbimage.cfg new file mode 100644 index 0000000..ffa3c18 --- /dev/null +++ b/board/Marvell/ib62x0/kwbimage.cfg @@ -0,0 +1,167 @@ +# +# Copyright (C) 2011 Gérald Kerma <dreagle(a)doukki.net> +# +# Written-by: Gérald Kerma <dreagle(a)doukki.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # change from nand to uart if building UART image +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000CC # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 1, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 0, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 28cc345..a4e8852 100644 --- a/boards.cfg +++ b/boards.cfg @@ -147,6 +147,8 @@ netspace_max_v2 arm arm926ejs netspace_v2 LaCie netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2 dreamplug arm arm926ejs - Marvell kirkwood guruplug arm arm926ejs - Marvell kirkwood +ib_nas6210 arm arm926ejs ib62x0 Marvell kirkwood ib62x0:BOARD_IS_IB_NAS6210 +ib_nas6220 arm arm926ejs ib62x0 Marvell kirkwood ib62x0:BOARD_IS_IB_NAS6220 mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h new file mode 100644 index 0000000..5981b65 --- /dev/null +++ b/include/configs/ib62x0.h @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2011-2012 + * Gérald Kerma <dreagle(a)doukki.net> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_IB62x0_H +#define _CONFIG_IB62x0_H + +/* + * Version number information + */ +#ifdef CONFIG_BOARD_IS_IB_NAS6210 +# define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS6210" +#elif CONFIG_BOARD_IS_IB_NAS6220 +# define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS6220" +#else +# error Unknown RaidSonic ICY BOX board specified +#endif + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_MACH_NAS6210 /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Other required minimal configurations + */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT +#ifdef CONFIG_BOARD_IS_IB_NAS6210 +# define CONFIG_SYS_PROMPT "IB-NAS6210 # " +#elif CONFIG_BOARD_IS_IB_NAS6220 +# define CONFIG_SYS_PROMPT "IB-NAS6220 # " +#else +# error Unknown RaidSonic ICY BOX board specified +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount root; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x1100000 ${initrd}; " \ + "bootm 0x800000 0x1100000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0x80000@0x0(uboot)," \ + "0x20000@0x80000(uboot_env)," \ + "-@0xa0000(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/uImage\0" \ + "initrd=/boot/uInitrd\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:root rootfstype=ubifs\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_MVSATA_IDE_USE_PORT0 +# ifdef CONFIG_BOARD_IS_IB_NAS6210 +# undef CONFIG_SYS_IDE_MAXBUS +# define CONFIG_SYS_IDE_MAXBUS 1 +# undef CONFIG_SYS_IDE_MAXDEVICE +# define CONFIG_SYS_IDE_MAXDEVICE 1 +# elif CONFIG_BOARD_IS_IB_NAS6220 +# define CONFIG_MVSATA_IDE_USE_PORT1 +# endif +#define CONFIG_SYS_ATA_IDE0_OFFSET KW_SATA_PORT0_OFFSET +# ifdef CONFIG_BOARD_IS_IB_NAS6220 +# define CONFIG_SYS_ATA_IDE1_OFFSET KW_SATA_PORT1_OFFSET +# endif +#endif /* CONFIG_CMD_IDE */ + +/* + * RTC driver configuration + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + +#endif /* _CONFIG_IB62x0_H */

6 16

[U-Boot] [PATCH v4] add new board nas62x0
by Luka Perkov 21 Mar '12

21 Mar '12

Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220. Only difference between boards is number of SATA ports. Signed-off-by: Luka Perkov <uboot(a)lukaperkov.net> Signed-off-by: Gerald Kerma <dreagle(a)doukki.net> --- Changes from version v3: * don't use utf8 for Geralds name * don't mix upper/lower case in kwbimage.cfg * fix prompt Found problems that should be looked at (this is not related with adding support for this board): * IB62x0_OE_LOW and IB62x0_OE_HIGH issue * CONFIG_SKIP_LOWLEVEL_INIT issue In separate patch I'll resend fix for CONFIG_SKIP_LOWLEVEL_INIT. MAINTAINERS | 4 + board/Marvell/ib62x0/Makefile | 51 +++++++++++ board/Marvell/ib62x0/ib62x0.c | 114 ++++++++++++++++++++++++ board/Marvell/ib62x0/ib62x0.h | 41 +++++++++ board/Marvell/ib62x0/kwbimage.cfg | 167 +++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/ib62x0.h | 176 +++++++++++++++++++++++++++++++++++++ 7 files changed, 555 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46f63a0..11d023e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -782,6 +782,10 @@ Linus Walleij <linus.walleij(a)linaro.org> integratorap various integratorcp various +Luka Perkov <uboot(a)lukaperkov.net> + + ib62x0 ARM926EJS + Dave Peverley <dpeverley(a)mpc-data.co.uk> omap730p2 ARM926EJS diff --git a/board/Marvell/ib62x0/Makefile b/board/Marvell/ib62x0/Makefile new file mode 100644 index 0000000..3d82f27 --- /dev/null +++ b/board/Marvell/ib62x0/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ib62x0.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/ib62x0/ib62x0.c b/board/Marvell/ib62x0/ib62x0.c new file mode 100644 index 0000000..e6853e7 --- /dev/null +++ b/board/Marvell/ib62x0/ib62x0.c @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2011 Gerald Kerma <dreagle(a)doukki.net> + * + * Written-by: Gerald Kerma <dreagle(a)doukki.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "ib62x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_UART0_RTS, + MPP9_UART0_CTS, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, /* Power LED red */ + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, /* Power LED green */ + MPP26_GPIO, + MPP27_GPIO, /* USB transfer LED */ + MPP28_GPIO, /* Reset button */ + MPP29_TSMP9, /* USB Copy button */ + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NAS6210; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/Marvell/ib62x0/ib62x0.h b/board/Marvell/ib62x0/ib62x0.h new file mode 100644 index 0000000..0e1e7c4 --- /dev/null +++ b/board/Marvell/ib62x0/ib62x0.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2011 Gerald Kerma <dreagle(a)doukki.net> + * + * Written-by: Gerald Kerma <dreagle(a)doukki.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __IB62x0_H +#define __IB62x0_H + +#define IB62x0_OE_LOW (~(0)) +#define IB62x0_OE_HIGH (~(0)) +#define IB62x0_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ +#define IB62x0_OE_VAL_HIGH (1 << 17) /* LED pin high */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __IB62x0_H */ diff --git a/board/Marvell/ib62x0/kwbimage.cfg b/board/Marvell/ib62x0/kwbimage.cfg new file mode 100644 index 0000000..32f3dca --- /dev/null +++ b/board/Marvell/ib62x0/kwbimage.cfg @@ -0,0 +1,167 @@ +# +# Copyright (C) 2011 Gerald Kerma <dreagle(a)doukki.net> +# +# Written-by: Gerald Kerma <dreagle(a)doukki.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # change from nand to uart if building UART image +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xffd01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xffd01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 1, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 0, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00120012 # DDR ODT Control (Low) +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xffd0149c 0x0000e40f # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 28cc345..a4e8852 100644 --- a/boards.cfg +++ b/boards.cfg @@ -147,6 +147,8 @@ netspace_max_v2 arm arm926ejs netspace_v2 LaCie netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2 dreamplug arm arm926ejs - Marvell kirkwood guruplug arm arm926ejs - Marvell kirkwood +ib_nas6210 arm arm926ejs ib62x0 Marvell kirkwood ib62x0:BOARD_IS_IB_NAS6210 +ib_nas6220 arm arm926ejs ib62x0 Marvell kirkwood ib62x0:BOARD_IS_IB_NAS6220 mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h new file mode 100644 index 0000000..1c4778d --- /dev/null +++ b/include/configs/ib62x0.h @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma <dreagle(a)doukki.net> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_IB62x0_H +#define _CONFIG_IB62x0_H + +/* + * Version number information + */ +#if defined(CONFIG_BOARD_IS_IB_NAS6210) +# define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS6210" +#elif defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS6220" +#else +# error Unknown RaidSonic ICY BOX board specified +#endif + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_MACH_NAS6210 /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Other required minimal configurations + */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT +#if defined(CONFIG_BOARD_IS_IB_NAS6210) +# define CONFIG_SYS_PROMPT "IB-NAS6210 => " +#elif defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_SYS_PROMPT "IB-NAS6220 => " +#else +# error Unknown RaidSonic ICY BOX board specified +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount root; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x1100000 ${initrd}; " \ + "bootm 0x800000 0x1100000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0x80000@0x0(uboot)," \ + "0x20000@0x80000(uboot_env)," \ + "-@0xa0000(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/uImage\0" \ + "initrd=/boot/uInitrd\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:root rootfstype=ubifs\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_MVSATA_IDE_USE_PORT0 +# if defined(CONFIG_BOARD_IS_IB_NAS6210) +# undef CONFIG_SYS_IDE_MAXBUS +# define CONFIG_SYS_IDE_MAXBUS 1 +# undef CONFIG_SYS_IDE_MAXDEVICE +# define CONFIG_SYS_IDE_MAXDEVICE 1 +# elif defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_MVSATA_IDE_USE_PORT1 +# endif +#define CONFIG_SYS_ATA_IDE0_OFFSET KW_SATA_PORT0_OFFSET +# if defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_SYS_ATA_IDE1_OFFSET KW_SATA_PORT1_OFFSET +# endif +#endif /* CONFIG_CMD_IDE */ + +/* + * RTC driver configuration + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + +#endif /* _CONFIG_IB62x0_H */

3 3

[U-Boot] [PATCH 1/2] sh: Add header file for interface of SH MMC
by Nobuhiro Iwamatsu 21 Mar '12

21 Mar '12

This defines the mmcif_mmc_init which is an MMC function of SH. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/sh/include/asm/mmc.h | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) create mode 100644 arch/sh/include/asm/mmc.h diff --git a/arch/sh/include/asm/mmc.h b/arch/sh/include/asm/mmc.h new file mode 100644 index 0000000..2c2ff21 --- /dev/null +++ b/arch/sh/include/asm/mmc.h @@ -0,0 +1,18 @@ +/* + * Renesas SuperH MMCIF driver. + * + * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + */ +#ifndef _SH_MMC_H_ +#define _SH_MMC_H_ + +int mmcif_mmc_init(void); + +#endif /* _SH_MMC_H_ */ + -- 1.7.9.1

1 1

[U-Boot] [PATCH 1/2] sh: ecovec: Remove unused variable
by Nobuhiro Iwamatsu 21 Mar '12

21 Mar '12

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- board/renesas/ecovec/ecovec.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c index 275b0ba..3bd1a62 100644 --- a/board/renesas/ecovec/ecovec.c +++ b/board/renesas/ecovec/ecovec.c @@ -55,7 +55,6 @@ int board_late_init(void) { u8 mac[6]; char env_mac[17]; - int i; udelay(1000); -- 1.7.9.1

1 0

[U-Boot] [PATCH] sh: Add header file of MMC framework
by Nobuhiro Iwamatsu 21 Mar '12

21 Mar '12

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/sh/lib/board.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index d9c0c22..eb021e8 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -25,6 +25,7 @@ #include <version.h> #include <watchdog.h> #include <net.h> +#include <mmc.h> #include <environment.h> #ifdef CONFIG_BITBANGMII -- 1.7.9.1

1 0

[U-Boot] [PATCH 4/4] powerpc/85xx:Fix NAND code base to support debugger
by Prabhakar Kushwaha 21 Mar '12

21 Mar '12

Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address. As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to any fetchable valid data Signed-off-by: Radu Lazarescu <radu.lazarescu(a)freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master No change, Resending again Tested on - SoC having E500 Family processor (P1010RDB, BSC9131RDB) - SoC having E500MC Family processor (P4080DS, P3041DS) arch/powerpc/cpu/mpc85xx/start.S | 18 +++++++++++++----- 1 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index cef00ba..0d50f6f 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1431,17 +1431,25 @@ relocate_code: 7: sync /* Wait for all icbi to complete on bus */ isync - /* - * Re-point the IVPR at RAM - */ - mtspr IVPR,r10 - /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ addi r0,r10,in_ram - _start + _START_OFFSET + +#if defined(CONFIG_E500) && defined(CONFIG_NAND_SPL) +/* + * As IVPR is going to point RAM address, + * Make sure IVOR15 has valid opcode to support debugger + */ + mtspr IVOR15,r0 +#endif + /* + * Re-point the IVPR at RAM + */ + mtspr IVPR,r10 + mtlr r0 blr /* NEVER RETURNS! */ .globl in_ram -- 1.7.5.4

1 0