March 2012 - U-Boot

[U-Boot] [PATCH v2] add nand spl boot for qi_lb60 board
by Xiangfu Liu 06 Mar '12

06 Mar '12

Signed-off-by: Xiangfu Liu <xiangfu(a)openmobilefree.net> --- arch/mips/cpu/xburst/cpu.c | 4 + arch/mips/cpu/xburst/start_spl.S | 65 ++++++++++++++++++++ drivers/mtd/nand/jz4740_nand.c | 40 +++++++++++- include/configs/qi_lb60.h | 3 + nand_spl/board/qi/qi_lb60/Makefile | 112 ++++++++++++++++++++++++++++++++++ nand_spl/board/qi/qi_lb60/nand_spl.c | 37 +++++++++++ nand_spl/board/qi/qi_lb60/u-boot.lds | 63 +++++++++++++++++++ 7 files changed, 321 insertions(+), 3 deletions(-) create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 nand_spl/board/qi/qi_lb60/Makefile create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c index e976341..afd166c 100644 --- a/arch/mips/cpu/xburst/cpu.c +++ b/arch/mips/cpu/xburst/cpu.c @@ -42,6 +42,8 @@ : \ : "i" (op), "R" (*(unsigned char *)(addr))) +#ifndef CONFIG_NAND_SPL + void __attribute__((weak)) _machine_restart(void) { struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE; @@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) cache_op(Hit_Invalidate_D, addr); } +#endif + void flush_icache_all(void) { u32 addr, t = 0; diff --git a/arch/mips/cpu/xburst/start_spl.S b/arch/mips/cpu/xburst/start_spl.S new file mode 100644 index 0000000..f137ccd --- /dev/null +++ b/arch/mips/cpu/xburst/start_spl.S @@ -0,0 +1,65 @@ +/* + * Startup Code for MIPS32 XBURST CPU-core + * + * Copyright (c) 2010 Xiangfu Liu <xiangfu(a)sharism.cc> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 3 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/cacheops.h> + +#include <asm/jz4740.h> + + .set noreorder + + .globl _start + .text +_start: + .word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */ +reset: + /* + * STATUS register + * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1 + */ + li t0, 0x0040FC04 + mtc0 t0, CP0_STATUS + /* + * CAUSE register + * IV=1, use the specical interrupt vector (0x200) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + bal 1f + nop + .word _GLOBAL_OFFSET_TABLE_ +1: + move gp, ra + lw t1, 0(ra) + move gp, t1 + + la sp, 0x80004000 + la t9, nand_spl_boot + j t9 + nop diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c index 3ec34f3..7ef07a5 100644 --- a/drivers/mtd/nand/jz4740_nand.c +++ b/drivers/mtd/nand/jz4740_nand.c @@ -15,6 +15,10 @@ #include <asm/io.h> #include <asm/jz4740.h> +#ifdef CONFIG_NAND_SPL + #define printf(arg...) do {} while (0) +#endif + #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000) #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000) #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000) @@ -176,7 +180,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, for (k = 0; k < 9; k++) writeb(read_ecc[k], &emc->nfpar[k]); } - /* Set PRDY */ + writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr); /* Wait for completion */ @@ -184,7 +188,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, status = readl(&emc->nfints); } while (!(status & EMC_NFINTS_DECF)); - /* disable ecc */ + /* Disable ECC */ writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr); /* Check decoding */ @@ -192,7 +196,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, return 0; if (status & EMC_NFINTS_UNCOR) { - printf("uncorrectable ecc\n"); + printf("JZ4740 uncorrectable ECC\n"); return -1; } @@ -230,6 +234,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat, return errcnt; } +#ifdef CONFIG_NAND_SPL +void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + +#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \ + (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2) + for (i = 0; i < len; i += 2) + buf[i] = readw(this->IO_ADDR_R); +#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \ + (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2) + for (i = 0; i < len; i++) + buf[i] = readb(this->IO_ADDR_R); +#else + #error JZ4740_NANDBOOT_CFG not defined or wrong +#endif +} + +uint8_t nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return readb(this->IO_ADDR_R); +} +#endif + /* * Main initialization routine */ @@ -247,6 +277,10 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_W = JZ_NAND_DATA_ADDR; nand->cmd_ctrl = jz_nand_cmd_ctrl; nand->dev_ready = jz_nand_device_ready; +#ifdef CONFIG_NAND_SPL + nand->read_byte = nand_read_byte; + nand->read_buf = nand_read_buf; +#endif nand->ecc.hwctl = jz_nand_hwctl; nand->ecc.correct = jz_nand_rs_correct_data; nand->ecc.calculate = jz_nand_rs_calculate_ecc; diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h index f989595..c40e4cc 100644 --- a/include/configs/qi_lb60.h +++ b/include/configs/qi_lb60.h @@ -35,6 +35,9 @@ #define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" #define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" +#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST + /* * Command line configuration. */ diff --git a/nand_spl/board/qi/qi_lb60/Makefile b/nand_spl/board/qi/qi_lb60/Makefile new file mode 100644 index 0000000..0c4113d --- /dev/null +++ b/nand_spl/board/qi/qi_lb60/Makefile @@ -0,0 +1,112 @@ +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_NAND_SPL_TEXT_BASE) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL -O2 + +SOBJS = start.o +COBJS = cpu.o jz4740.o jz_serial.o jz4740_nand.o nand_spl.o nand_boot.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin +all: $(obj).depend $(ALL) + +# The JZ4740 CPU can load two areas of data from NAND flash to internal SRAM, +# one is the normal area up to 8KB starting from NAND flash address 0, the +# other is the backup area up to 8KB starting from NAND flash address 0x2000. + +# After reset, the boot program will first read the normal area data from NAND +# flash using hardware Reed-Solomon ECC. If no ECC error is detected or ECC +# error is correctable, the boot program then branches to internal SRAM at 4 +# bytes offset. ff it detects an uncorrectable ECC error, it will continue to +# read the backup area of data from NAND flash using hardware Reed-Solomon ECC. + +# those 'dd' commands is for create such two 8KB for JZ4740 CPU +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin + dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1 + cat $< $(nandobj)junk1 > $(nandobj)junk2 + dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3 + cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4 + dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5 + cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6 + dd bs=1024 count=256 if=$(nandobj)junk6 of=$@ + rm -f $(nandobj)junk* + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files +$(obj)start.S: + @rm -f $@ + ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $@ + +$(obj)cpu.c: + @rm -f $@ + ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $@ + +$(obj)jz4740.c: + @rm -f $@ + ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $@ + +$(obj)jz_serial.c: + @rm -f $@ + ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $@ + +$(obj)jz4740_nand.c: + @rm -f $@ + ln -s $(TOPDIR)/drivers/mtd/nand/jz4740_nand.c $@ + +$(obj)nand_boot.c: + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_spl.c: + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_spl.c $@ +endif + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/nand_spl/board/qi/qi_lb60/nand_spl.c b/nand_spl/board/qi/qi_lb60/nand_spl.c new file mode 100644 index 0000000..6a0358a --- /dev/null +++ b/nand_spl/board/qi/qi_lb60/nand_spl.c @@ -0,0 +1,37 @@ +/* + * Copyright 2012 Xiangfu Liu <xiangfu(a)sharism.cc> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> + +#include <nand.h> +#include <asm/io.h> +#include <asm/jz4740.h> + +void nand_spl_boot(void) +{ + __gpio_as_sdram_16bit_4720(); + __gpio_as_uart0(); + + pll_init(); + serial_init(); + sdram_init(); + + nand_boot(); +} diff --git a/nand_spl/board/qi/qi_lb60/u-boot.lds b/nand_spl/board/qi/qi_lb60/u-boot.lds new file mode 100644 index 0000000..7042388 --- /dev/null +++ b/nand_spl/board/qi/qi_lb60/u-boot.lds @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2005 + * Ingenic Semiconductor, <jlwei(a)ingenic.cn> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") + +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} -- 1.7.5.4

4 6

[U-Boot] [PATCH] Makefile: Remove mmc_spl related enteries
by Chander Kashyap 06 Mar '12

06 Mar '12

As mmc_spl now follows spl infrastructure, removed unwanted enteries in Makefile for mmc_spl related compilation. Signed-off-by: Chander Kashyap <chander.kashyap(a)linaro.org> --- Makefile | 8 -------- 1 files changed, 0 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 294c762..d349c1c 100644 --- a/Makefile +++ b/Makefile @@ -361,7 +361,6 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin -ALL-$(CONFIG_MMC_U_BOOT) += $(obj)mmc_spl/u-boot-mmc-spl.bin ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin @@ -481,11 +480,6 @@ onenand_ipl: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk $(obj)u-boot-onenand.bin: onenand_ipl $(obj)u-boot.bin cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin -mmc_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend - $(MAKE) -C mmc_spl/board/$(BOARDDIR) all - -$(obj)mmc_spl/u-boot-mmc-spl.bin: mmc_spl - $(obj)spl/u-boot-spl.bin: depend $(MAKE) -C spl all @@ -768,7 +762,6 @@ clean: @rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map} @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map} - @rm -f $(obj)mmc_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,u-boot-spl.bin,u-boot-mmc-spl.bin} @rm -f $(ONENAND_BIN) @rm -f $(obj)onenand_ipl/u-boot.lds @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map} @@ -797,7 +790,6 @@ clobber: clean @rm -fr $(obj)include/generated @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f - @[ ! -d $(obj)mmc_spl ] || find $(obj)mmc_spl -name "*" -type l -print | xargs rm -f @rm -f $(obj)dts/*.tmp mrproper \ -- 1.7.5.4

2 1

[U-Boot] [PATCH v5 0/9] Unified command execution in one place
by Simon Glass 06 Mar '12

06 Mar '12

At present two parsers have similar code to execute commands. Also cmd_usage() is called all over the place. This series adds a single function which processes commands called cmd_process(). This new function understands return codes, and in particular CMD_RET_USAGE to indicate a usage error. So rather than calling cmd_usage() themselves, the command handlers can just return this error. There appears to be a run_command2() which is used to run commands with the selected parser. This series changes this in two separate steps to just run_command(), and renames the old run_command() to builtin_run_command(). No one should call this outside main.c since if the hush parser is being used it is wrong to call it. The built-in parser code could move into a separate file perhaps in a future patch. The overall series reduces code size on ARM by about 1KB on my ~160KB U-Boot text region when the hush parser is used, and around 60 bytes when it isn't. As an aside the only user of parse_line() is fsl_ddr_interactive() which seems to have its own command line interface which operates before DRAM is set up. Do I have this right? Is there no way this could be done later from a normal U-Boot command? (I have run this through MAKEALL and it seems clean) Changes in v2: - Fix minor errors one of which created a warning - Squash i2c patch into the common/ patch Changes in v3: - Rebase to master Changes in v4: - Add a 'repeatable' parameter to cmd_process() - Make cmd_process() return only success (0) or failure (1) - Minor comment change for call to builtin_run_command() - Rationalise return codes to 0, 1 and usage Changes in v5: - Add function comment to run_command() - Adjust commit message to make it easier for Mike to grok - Move cmd_call() prototype inside existing #ifdef __ASSEMBLY__ - Tidy up function comment to bring in changes in a later patch - Use existing #ifdef __ASSEMBLY__ rather than create a new one Simon Glass (9): Remove CMD_PXE's static on run_command() Rename run_command() to builtin_run_command() Rename run_command2() to run_command() Stop using builtin_run_command() Don't include standard parser if hush is used Create a single cmd_call() function to handle command execution Remove interleave of non-U-Boot code in hush Add cmd_process() to process commands in one place Convert cmd_usage() calls in common to use a return value arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 7 +-- board/esd/common/cmd_loadpci.c | 2 +- board/esd/du440/du440.c | 2 +- common/cmd_bedbug.c | 6 +- common/cmd_bmp.c | 6 +- common/cmd_boot.c | 2 +- common/cmd_bootm.c | 10 +--- common/cmd_cache.c | 4 +- common/cmd_dataflash_mmc_mux.c | 2 +- common/cmd_date.c | 3 +- common/cmd_dcr.c | 8 +- common/cmd_df.c | 2 +- common/cmd_eeprom.c | 2 +- common/cmd_ext2.c | 4 +- common/cmd_fdc.c | 2 +- common/cmd_fdos.c | 2 +- common/cmd_fdt.c | 14 ++-- common/cmd_fitupd.c | 2 +- common/cmd_flash.c | 14 ++-- common/cmd_fpga.c | 4 +- common/cmd_gpio.c | 2 +- common/cmd_i2c.c | 32 +++++----- common/cmd_ide.c | 10 ++-- common/cmd_irq.c | 2 +- common/cmd_itest.c | 2 +- common/cmd_led.c | 6 +- common/cmd_load.c | 2 +- common/cmd_log.c | 4 +- common/cmd_md5sum.c | 2 +- common/cmd_mdio.c | 2 +- common/cmd_mem.c | 22 ++++---- common/cmd_mfsl.c | 10 ++-- common/cmd_mgdisk.c | 2 +- common/cmd_mii.c | 4 +- common/cmd_misc.c | 2 +- common/cmd_mmc.c | 14 ++-- common/cmd_mmc_spi.c | 3 +- common/cmd_mp.c | 8 +- common/cmd_mtdparts.c | 2 +- common/cmd_nand.c | 6 +- common/cmd_net.c | 6 +- common/cmd_nvedit.c | 22 ++++---- common/cmd_onenand.c | 12 ++-- common/cmd_otp.c | 2 +- common/cmd_pci.c | 2 +- common/cmd_portio.c | 4 +- common/cmd_pxe.c | 10 ++-- common/cmd_reiser.c | 4 +- common/cmd_sata.c | 8 +- common/cmd_scsi.c | 15 +++-- common/cmd_setexpr.c | 2 +- common/cmd_sf.c | 2 +- common/cmd_sha1sum.c | 2 +- common/cmd_source.c | 2 +- common/cmd_strings.c | 2 +- common/cmd_time.c | 4 +- common/cmd_ubi.c | 4 +- common/cmd_ubifs.c | 10 ++-- common/cmd_unzip.c | 2 +- common/cmd_usb.c | 6 +- common/command.c | 60 +++++++++++++++++++ common/hush.c | 69 ++++++----------------- common/main.c | 101 +++++++++++---------------------- include/command.h | 30 ++++++++++ include/common.h | 5 +- 65 files changed, 315 insertions(+), 306 deletions(-) -- 1.7.7.3

3 30

[U-Boot] Pull request: u-boot-x86/master
by Graeme Russ 06 Mar '12

06 Mar '12

Hi Wolfgang, The following changes since commit fca94c3fd5deef33442813475a5af1650f2d2830: integrator: remove fragile delay loop from PCI code (2012-03-04 21:15:31 +0100) are available in the git repository at: git://git.denx.de/u-boot-x86.git master Mike Frysinger (1): sc520: fix build warning about unused temp var arch/x86/cpu/sc520/sc520_timer.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Regards, Graeme

2 1

[U-Boot] [PATCH 1/2] PPC: Drop mv6436x_eth_initialize() from net/eth.c
by Marek Vasut 06 Mar '12

06 Mar '12

This function was defined as an extern in net/eth.c, drop that and use standard means of calling it. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Reinhard Arlt <reinhard.arlt(a)esd-electronics.com> --- board/Marvell/db64360/db64360.c | 6 +++++- board/Marvell/db64360/eth.h | 1 + board/esd/cpci750/cpci750.c | 5 +++++ board/esd/cpci750/eth.h | 1 + net/eth.c | 4 ---- 5 files changed, 12 insertions(+), 5 deletions(-) diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c index 5183466..6cae686 100644 --- a/board/Marvell/db64360/db64360.c +++ b/board/Marvell/db64360/db64360.c @@ -934,5 +934,9 @@ void board_prebootm_init () int board_eth_init(bd_t *bis) { - return pci_eth_init(bis); + int ret; + ret = pci_eth_init(bis); + if (!ret) + ret = mv6436x_eth_initialize(bis); + return ret; } diff --git a/board/Marvell/db64360/eth.h b/board/Marvell/db64360/eth.h index aab32d2..6fbfdfe 100644 --- a/board/Marvell/db64360/eth.h +++ b/board/Marvell/db64360/eth.h @@ -39,5 +39,6 @@ int db64360_eth0_transmit(unsigned int s, volatile char *p); void db64360_eth0_disable(void); bool network_start(bd_t *bis); +int mv6436x_eth_initialize(bd_t *); #endif /* __EVB64360_ETH_H__ */ diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 08311c9..98051fb 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -1101,3 +1101,8 @@ U_BOOT_CMD( pldver, 1, 1, do_pldver, "Show PLD version", "Show PLD version)"); + +int board_eth_init(bd_t *bis) +{ + return mv6436x_eth_initialize(bis); +} diff --git a/board/esd/cpci750/eth.h b/board/esd/cpci750/eth.h index aab32d2..6fbfdfe 100644 --- a/board/esd/cpci750/eth.h +++ b/board/esd/cpci750/eth.h @@ -39,5 +39,6 @@ int db64360_eth0_transmit(unsigned int s, volatile char *p); void db64360_eth0_disable(void); bool network_start(bd_t *bis); +int mv6436x_eth_initialize(bd_t *); #endif /* __EVB64360_ETH_H__ */ diff --git a/net/eth.c b/net/eth.c index b4b9b43..225b03f 100644 --- a/net/eth.c +++ b/net/eth.c @@ -81,7 +81,6 @@ static int __def_eth_init(bd_t *bis) int cpu_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init"))); int board_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init"))); -extern int mv6436x_eth_initialize(bd_t *); extern int mv6446x_eth_initialize(bd_t *); #ifdef CONFIG_API @@ -252,9 +251,6 @@ int eth_initialize(bd_t *bis) } else printf("Net Initialization Skipped\n"); -#if defined(CONFIG_DB64360) || defined(CONFIG_CPCI750) - mv6436x_eth_initialize(bis); -#endif #if defined(CONFIG_DB64460) || defined(CONFIG_P3Mx) mv6446x_eth_initialize(bis); #endif -- 1.7.9

2 3

[U-Boot] [PATCH] env: Add the ability to merge the saved env with the default.
by Doug Anderson 06 Mar '12

06 Mar '12

This is a useful mechanism any time you have a way to update the saved environment outside of u-boot. This can be a tool like fw_setenv or could be a tool like we use in Chrome OS that modifies the variables in a binary image before flashing (see factory_setup/update_firmware_vars.py in http://git.chromium.org/git/chromiumos/platform/factory-utils). Signed-off-by: Doug Anderson <dianders(a)chromium.org> --- common/env_common.c | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-) diff --git a/common/env_common.c b/common/env_common.c index 71811c4..5938732 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -34,6 +34,19 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * Create a saved enviroment with this env variable set to "1" to merge the + * saved environment on top of the default environment. The idea is that your + * saved environment would just contain variables that you'd like to override + * from the default so that as you update u-boot (w/ potential changes to the + * default) you get all the updates. + * + * This is really most useful when you have a tool like fw_setenv to manage + * your saved environment. Using 'saveenv' to save your environment will saved + * the _merged_ environment (AKA it won't unmerge things). + */ +#define MERGE_WITH_DEFAULT "merge_with_default" + /************************************************************************ * Default settings to be used when no valid environment is found */ @@ -208,7 +221,18 @@ int env_import(const char *buf, int check) } if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0)) { + char *merge_val; + gd->flags |= GD_FLG_ENV_READY; + merge_val = getenv(MERGE_WITH_DEFAULT); + + if (merge_val != NULL && merge_val[0] != '0') { + set_default_env(""); + himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', + H_NOCLEAR); + hdelete_r(MERGE_WITH_DEFAULT, &env_htab); + puts("Merged saved with default environment\n\n"); + } return 1; } -- 1.7.7.3

3 4

[U-Boot] [PATCH] usb: replace wait_ms() with mdelay()
by Mike Frysinger 06 Mar '12

06 Mar '12

Common code has a mdelay() func, so use that instead of the usb-specific wait_ms() func. This also fixes the build errors: ohci-hcd.c: In function 'submit_common_msg': /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1519:9: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1816:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1827:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1844:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1563:11: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1583:9: sorry, unimplemented: called from here make[1]: *** [ohci-hcd.o] Error 1 Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c | 28 ++++++++++++------------ arch/arm/cpu/pxa/usb.c | 2 +- arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c | 28 ++++++++++++------------ arch/powerpc/cpu/mpc5xxx/usb_ohci.c | 6 ++-- arch/powerpc/cpu/ppc4xx/usb_ohci.c | 6 ++-- arch/sparc/cpu/leon3/usb_uhci.c | 8 +++--- board/efikamx/efikamx-usb.c | 2 +- board/mcc200/auto_update.c | 4 +- board/mpl/common/usb_uhci.c | 8 +++--- board/renesas/sh7785lcr/selfcheck.c | 10 +------- common/usb.c | 16 ++----------- common/usb_hub.c | 10 ++++---- common/usb_storage.c | 16 +++++++------- drivers/usb/host/ehci-hcd.c | 4 +- drivers/usb/host/isp116x-hcd.c | 12 +++++----- drivers/usb/host/ohci-hcd.c | 28 ++++++++++++------------ drivers/usb/host/r8a66597-hcd.c | 14 ++++++------ include/usb.h | 1 - 18 files changed, 93 insertions(+), 110 deletions(-) diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c index 80bb61b27..cf0335c 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c @@ -1057,7 +1057,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif if (usb_pipeint(pipe)) { info("Root-Hub submit IRQ: NOT implemented"); @@ -1260,7 +1260,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, #ifdef DEBUG ohci_dump_roothub(&gohci, 1); #else - wait_ms(1); + mdelay(1); #endif len = min_t(int, len, leni); @@ -1275,7 +1275,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0 /*usb_pipein(pipe) */); #else - wait_ms(1); + mdelay(1); #endif return stat; @@ -1302,7 +1302,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif if (!maxsize) { err("submit_common_message: pipesize for pipe %lx is zero", @@ -1316,7 +1316,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, return -1; } - wait_ms(10); + mdelay(10); /* ohci_dump_status(&gohci); */ /* allow more time for a BULK device to react - some are slow */ @@ -1351,7 +1351,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, } if (--timeout) { - wait_ms(1); + mdelay(1); if (!urb_finished) dbg("\%"); @@ -1396,7 +1396,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif /* free TDs in urb_priv */ @@ -1423,7 +1423,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif if (!maxsize) { err("submit_control_message: pipesize for pipe %lx is zero", @@ -1463,7 +1463,7 @@ static int hc_reset(struct ohci *ohci) writel(OHCI_OCR, &ohci->regs->cmdstatus); info("USB HC TakeOver from SMM"); while (readl(&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms(10); + mdelay(10); if (--smm_timeout == 0) { err("USB HC TakeOver failed!"); return -1; @@ -1600,7 +1600,7 @@ static int hc_interrupt(void) #ifdef DEBUG ohci_dump(ohci, 1); #else - wait_ms(1); + mdelay(1); #endif /* FIXME: be optimistic, hope that bug won't repeat often. */ /* Make some non-interrupt context restart the controller. */ @@ -1611,7 +1611,7 @@ static int hc_interrupt(void) } if (ints & OHCI_INTR_WDH) { - wait_ms(1); + mdelay(1); writel(OHCI_INTR_WDH, &regs->intrdisable); stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci)); @@ -1627,7 +1627,7 @@ static int hc_interrupt(void) /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ if (ints & OHCI_INTR_SF) { unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; - wait_ms(1); + mdelay(1); writel(OHCI_INTR_SF, &regs->intrdisable); if (ohci->ed_rm_list[frame] != NULL) writel(OHCI_INTR_SF, &regs->intrenable); @@ -1718,7 +1718,7 @@ int usb_lowlevel_init(void) /* FIXME this is a second HC reset; why?? */ gohci.hc_control = OHCI_USB_RESET; writel(gohci.hc_control, &gohci.regs->control); - wait_ms(10); + mdelay(10); if (hc_start(&gohci) < 0) { err("can't start usb-%s", gohci.slot_name); @@ -1730,7 +1730,7 @@ int usb_lowlevel_init(void) #ifdef DEBUG ohci_dump(&gohci, 1); #else - wait_ms(1); + mdelay(1); #endif ohci_inited = 1; urb_finished = 1; diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c index 307fc6c..6c7e496 100644 --- a/arch/arm/cpu/pxa/usb.c +++ b/arch/arm/cpu/pxa/usb.c @@ -48,7 +48,7 @@ int usb_cpu_init(void) #endif writel(readl(UHCHR) | UHCHR_FHR, UHCHR); - wait_ms(11); + mdelay(11); writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c index 866dd6c..7647e11 100644 --- a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c @@ -1012,7 +1012,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, urb_priv.actual_length = 0; pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif if (usb_pipeint(pipe)) { info("Root-Hub submit IRQ: NOT implemented"); @@ -1189,7 +1189,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); #ifdef DEBUG ohci_dump_roothub (&gohci, 1); #else - wait_ms(1); + mdelay(1); #endif len = min_t(int, len, leni); @@ -1203,7 +1203,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); urb_priv.actual_length = transfer_len; pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); #else - wait_ms(1); + mdelay(1); #endif return stat; @@ -1230,7 +1230,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, urb_priv.actual_length = 0; pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif if (!maxsize) { err("submit_common_message: pipesize for pipe %lx is zero", @@ -1243,7 +1243,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, return -1; } - wait_ms(10); + mdelay(10); /* ohci_dump_status(&gohci); */ /* allow more time for a BULK device to react - some are slow */ @@ -1267,7 +1267,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, break; } if (--timeout) { - udelay(250); /* wait_ms(1); */ + udelay(250); /* mdelay(1); */ } else { err("CTL:TIMEOUT "); stat = USB_ST_CRC_ERR; @@ -1302,7 +1302,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, #ifdef DEBUG pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif /* free TDs in urb_priv */ @@ -1328,7 +1328,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, urb_priv.actual_length = 0; pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif if (!maxsize) { err("submit_control_message: pipesize for pipe %lx is zero", @@ -1367,7 +1367,7 @@ static int hc_reset (ohci_t *ohci) writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ info("USB HC TakeOver from SMM"); while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); + mdelay (10); if (--smm_timeout == 0) { err("USB HC TakeOver failed!"); return -1; @@ -1490,7 +1490,7 @@ hc_interrupt (void) #ifdef DEBUG ohci_dump (ohci, 1); #else - wait_ms(1); + mdelay(1); #endif /* FIXME: be optimistic, hope that bug won't repeat often. */ /* Make some non-interrupt context restart the controller. */ @@ -1501,7 +1501,7 @@ hc_interrupt (void) } if (ints & OHCI_INTR_WDH) { - wait_ms(1); + mdelay(1); writel (OHCI_INTR_WDH, &regs->intrdisable); stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); writel (OHCI_INTR_WDH, &regs->intrenable); @@ -1516,7 +1516,7 @@ hc_interrupt (void) /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ if (ints & OHCI_INTR_SF) { unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; - wait_ms(1); + mdelay(1); writel (OHCI_INTR_SF, &regs->intrdisable); if (ohci->ed_rm_list[frame] != NULL) writel (OHCI_INTR_SF, &regs->intrenable); @@ -1686,7 +1686,7 @@ int usb_lowlevel_init(void) /* FIXME this is a second HC reset; why?? */ writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); - wait_ms (10); + mdelay (10); if (hc_start (&gohci) < 0) goto errout; @@ -1694,7 +1694,7 @@ int usb_lowlevel_init(void) #ifdef DEBUG ohci_dump (&gohci, 1); #else - wait_ms(1); + mdelay(1); #endif ohci_inited = 1; return 0; diff --git a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c index d250c19..6d91525 100644 --- a/arch/powerpc/cpu/mpc5xxx/usb_ohci.c +++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c @@ -1269,7 +1269,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, } if (--timeout) { - wait_ms(1); + mdelay(1); if (!urb_finished) dbg("\%"); @@ -1372,7 +1372,7 @@ static int hc_reset (ohci_t *ohci) writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ info("USB HC TakeOver from SMM"); while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); + mdelay (10); if (--smm_timeout == 0) { err("USB HC TakeOver failed!"); return -1; @@ -1529,7 +1529,7 @@ hc_interrupt (void) /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ if (ints & OHCI_INTR_SF) { unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; - wait_ms(1); + mdelay(1); writel (OHCI_INTR_SF, &regs->intrdisable); if (ohci->ed_rm_list[frame] != NULL) writel (OHCI_INTR_SF, &regs->intrenable); diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c index 4fb7031..14c6a28 100644 --- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c +++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c @@ -1274,7 +1274,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, } if (--timeout) { - wait_ms(1); + mdelay(1); if (!urb_finished) dbg("\%"); @@ -1377,7 +1377,7 @@ static int hc_reset (ohci_t *ohci) writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ info("USB HC TakeOver from SMM"); while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms (10); + mdelay (10); if (--smm_timeout == 0) { err("USB HC TakeOver failed!"); return -1; @@ -1534,7 +1534,7 @@ hc_interrupt (void) /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ if (ints & OHCI_INTR_SF) { unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1; - wait_ms(1); + mdelay(1); writel (OHCI_INTR_SF, &regs->intrdisable); if (ohci->ed_rm_list[frame] != NULL) writel (OHCI_INTR_SF, &regs->intrenable); diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c index 358e52a..62cc25d 100644 --- a/arch/sparc/cpu/leon3/usb_uhci.c +++ b/arch/sparc/cpu/leon3/usb_uhci.c @@ -515,9 +515,9 @@ void reset_hc(void) out16r(usb_base_addr + USBCMD, USBCMD_GRESET | USBCMD_RS); /* Turn off all interrupts */ out16r(usb_base_addr + USBINTR, 0); - wait_ms(50); + mdelay(50); out16r(usb_base_addr + USBCMD, 0); - wait_ms(10); + mdelay(10); } void start_hc(void) @@ -1044,7 +1044,7 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, status = (status & 0xfff5) | USBPORTSC_PR; out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), status); - wait_ms(10); + mdelay(10); status = (status & 0xfff5) & ~USBPORTSC_PR; out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), status); @@ -1052,7 +1052,7 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, status = (status & 0xfff5) | USBPORTSC_PE; out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), status); - wait_ms(10); + mdelay(10); status = (status & 0xfff5) | 0xa; out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), status); diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c index ac2d2e9..618b39d 100644 --- a/board/efikamx/efikamx-usb.c +++ b/board/efikamx/efikamx-usb.c @@ -187,7 +187,7 @@ void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS); - wait_ms(50); + mdelay(50); /* terminate the reset */ *reg = ehci_readl(status_reg); diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c index 4152873..b9ff311 100644 --- a/board/mcc200/auto_update.c +++ b/board/mcc200/auto_update.c @@ -284,7 +284,7 @@ int au_do_update(int idx, long sz) */ debug ("flash_sect_erase(%lx, %lx);\n", start, end); flash_sect_erase(start, end); - wait_ms(100); + mdelay(100); #ifdef CONFIG_PROGRESSBAR show_progress(end - start, totsize); #endif @@ -352,7 +352,7 @@ int do_auto_update(void) * Read keypad status */ i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2); - wait_ms(500); + mdelay(500); i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2); /* diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index 89d2e0a..ddca587 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -435,9 +435,9 @@ void reset_hc(void) out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS); /* Turn off all interrupts */ out16r(usb_base_addr + USBINTR,0); - wait_ms(50); + mdelay(50); out16r( usb_base_addr + USBCMD,0); - wait_ms(10); + mdelay(10); } void start_hc(void) @@ -926,13 +926,13 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); status = (status & 0xfff5) | USBPORTSC_PR; out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - wait_ms(10); + mdelay(10); status = (status & 0xfff5) & ~USBPORTSC_PR; out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); udelay(10); status = (status & 0xfff5) | USBPORTSC_PE; out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - wait_ms(10); + mdelay(10); status = (status & 0xfff5) | 0xa; out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); len=0; diff --git a/board/renesas/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c index 6d92c83..2cd2ad0 100644 --- a/board/renesas/sh7785lcr/selfcheck.c +++ b/board/renesas/sh7785lcr/selfcheck.c @@ -33,12 +33,6 @@ #define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET) -static void wait_ms(unsigned long time) -{ - while (time--) - udelay(1000); -} - static void test_pld(void) { printf("PLD version = %04x\n", readb(PLD_VERSR)); @@ -53,10 +47,10 @@ static void test_led(void) { printf("turn on LEDs 3, 5, 7, 9\n"); writeb(0x55, PLD_LEDCR); - wait_ms(2000); + mdelay(2000); printf("turn on LEDs 4, 6, 8, 10\n"); writeb(0xaa, PLD_LEDCR); - wait_ms(2000); + mdelay(2000); writeb(0x00, PLD_LEDCR); } diff --git a/common/usb.c b/common/usb.c index 3c9ede4..1ec30bc 100644 --- a/common/usb.c +++ b/common/usb.c @@ -81,16 +81,6 @@ char usb_started; /* flag for the started/stopped USB status */ */ static void usb_scan_devices(void); -/*********************************************************************** - * wait_ms - */ - -inline void wait_ms(unsigned long ms) -{ - while (ms-- > 0) - udelay(1000); -} - /*************************************************************************** * Init USB Device */ @@ -209,7 +199,7 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, while (timeout--) { if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC)) break; - wait_ms(1); + mdelay(1); } if (dev->status) return -1; @@ -233,7 +223,7 @@ int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, while (timeout--) { if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC)) break; - wait_ms(1); + mdelay(1); } *actual_length = dev->act_len; if (dev->status == 0) @@ -897,7 +887,7 @@ int usb_new_device(struct usb_device *dev) return 1; } - wait_ms(10); /* Let the SET_ADDRESS settle */ + mdelay(10); /* Let the SET_ADDRESS settle */ tmp = sizeof(dev->descriptor); diff --git a/common/usb_hub.c b/common/usb_hub.c index 84d0d3f..e0edaad 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -120,7 +120,7 @@ static void usb_hub_power_on(struct usb_hub_device *hub) } /* Wait at least 100 msec for power to become stable */ - wait_ms(max(pgood_delay, (unsigned)100)); + mdelay(max(pgood_delay, (unsigned)100)); } void usb_hub_reset(void) @@ -160,7 +160,7 @@ int hub_port_reset(struct usb_device *dev, int port, for (tries = 0; tries < MAX_TRIES; tries++) { usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET); - wait_ms(200); + mdelay(200); if (usb_get_port_status(dev, port + 1, &portsts) < 0) { USB_HUB_PRINTF("get_port_status failed status %lX\n", @@ -187,7 +187,7 @@ int hub_port_reset(struct usb_device *dev, int port, if (portstatus & USB_PORT_STAT_ENABLE) break; - wait_ms(200); + mdelay(200); } if (tries == MAX_TRIES) { @@ -232,7 +232,7 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port) if (!(portstatus & USB_PORT_STAT_CONNECTION)) return; } - wait_ms(200); + mdelay(200); /* Reset the port */ if (hub_port_reset(dev, port, &portstatus) < 0) { @@ -240,7 +240,7 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port) return; } - wait_ms(200); + mdelay(200); /* Allocate a new device struct for it */ usb = usb_alloc_new_device(); diff --git a/common/usb_storage.c b/common/usb_storage.c index de84c8d..1208333 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -438,19 +438,19 @@ static int usb_stor_BBB_reset(struct us_data *us) } /* long wait for reset */ - wait_ms(150); + mdelay(150); USB_STOR_PRINTF("BBB_reset result %d: status %lX reset\n", result, us->pusb_dev->status); pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); result = usb_clear_halt(us->pusb_dev, pipe); /* long wait for reset */ - wait_ms(150); + mdelay(150); USB_STOR_PRINTF("BBB_reset result %d: status %lX clearing IN endpoint\n", result, us->pusb_dev->status); /* long wait for reset */ pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); result = usb_clear_halt(us->pusb_dev, pipe); - wait_ms(150); + mdelay(150); USB_STOR_PRINTF("BBB_reset result %d: status %lX" " clearing OUT endpoint\n", result, us->pusb_dev->status); @@ -478,7 +478,7 @@ static int usb_stor_CB_reset(struct us_data *us) USB_CNTL_TIMEOUT * 5); /* long wait for reset */ - wait_ms(1500); + mdelay(1500); USB_STOR_PRINTF("CB_reset result %d: status %lX" " clearing endpoint halt\n", result, us->pusb_dev->status); @@ -621,7 +621,7 @@ int usb_stor_CBI_get_status(ccb *srb, struct us_data *us) while (timeout--) { if ((volatile int *) us->ip_wanted == 0) break; - wait_ms(10); + mdelay(10); } if (us->ip_wanted) { printf(" Did not get interrupt on CBI\n"); @@ -692,7 +692,7 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) usb_stor_BBB_reset(us); return USB_STOR_TRANSPORT_FAILED; } - wait_ms(5); + mdelay(5); pipein = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out); /* DATA phase + error handling */ @@ -884,7 +884,7 @@ do_retry: srb->sense_buf[12], srb->sense_buf[13]); return USB_STOR_TRANSPORT_FAILED; } else { - wait_ms(100); + mdelay(100); goto do_retry; } break; @@ -960,7 +960,7 @@ static int usb_test_unit_ready(ccb *srb, struct us_data *ss) if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) return 0; usb_request_sense(srb, ss); - wait_ms(100); + mdelay(100); } while (retries--); return -1; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index d6fee81..ef5afc2 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -776,7 +776,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, goto unknown; } - wait_ms(1); + mdelay(1); len = min3(srclen, le16_to_cpu(req->length), length); if (srcptr != NULL && len > 0) memcpy(buffer, srcptr, len); @@ -857,7 +857,7 @@ int usb_lowlevel_init(void) ehci_writel(&hcor->or_configflag, cmd); /* unblock posted write */ cmd = ehci_readl(&hcor->or_usbcmd); - wait_ms(5); + mdelay(5); reg = HC_VERSION(ehci_readl(&hccr->cr_capbase)); printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c index abdcbb4..5ef34c3 100644 --- a/drivers/usb/host/isp116x-hcd.c +++ b/drivers/usb/host/isp116x-hcd.c @@ -578,7 +578,7 @@ static int isp116x_interrupt(struct isp116x *isp116x) /* When root hub or any of its ports is going to come out of suspend, it may take more than 10ms for status bits to stabilize. */ - wait_ms(20); + mdelay(20); } if (intstat & HCINT_SO) { @@ -679,7 +679,7 @@ retry_same: /* Pack data into FIFO ram */ pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len); #ifdef EXTRA_DELAY - wait_ms(EXTRA_DELAY); + mdelay(EXTRA_DELAY); #endif /* Start the data transfer */ @@ -983,11 +983,11 @@ static int isp116x_submit_rh_msg(struct usb_device *dev, unsigned long pipe, HCRHPORT1 + wIndex - 1); if (!(tmp & RH_PS_PRS)) break; - wait_ms(1); + mdelay(1); } isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1, RH_PS_PRS); - wait_ms(10); + mdelay(10); len = 0; break; @@ -1251,7 +1251,7 @@ static int isp116x_sw_reset(struct isp116x *isp116x) isp116x_write_reg32(isp116x, HCCMDSTAT, HCCMDSTAT_HCR); while (--retries) { /* It usually resets within 1 ms */ - wait_ms(1); + mdelay(1); if (!(isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR)) break; } @@ -1278,7 +1278,7 @@ static int isp116x_reset(struct isp116x *isp116x) clkrdy = isp116x_read_reg16(isp116x, HCuPINT) & HCuPINT_CLKRDY; if (clkrdy) break; - wait_ms(1); + mdelay(1); } if (!clkrdy) { ERR("clock not ready after %dms", timeout); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 1a428e9..d24f2f1 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1279,7 +1279,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif if (usb_pipeint(pipe)) { info("Root-Hub submit IRQ: NOT implemented"); @@ -1360,7 +1360,7 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, OK(0); case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_PPS); - wait_ms(100); + mdelay(100); OK(0); case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ if (RD_RH_PORTSTAT & RH_PS_CCS) @@ -1465,7 +1465,7 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, #ifdef DEBUG ohci_dump_roothub(&gohci, 1); #else - wait_ms(1); + mdelay(1); #endif len = min_t(int, len, leni); @@ -1478,7 +1478,7 @@ pkt_print(NULL, dev, pipe, buffer, transfer_len, pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); #else - wait_ms(1); + mdelay(1); #endif return stat; @@ -1516,7 +1516,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif if (!maxsize) { err("submit_common_message: pipesize for pipe %lx is zero", @@ -1530,7 +1530,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, } #if 0 - wait_ms(10); + mdelay(10); /* ohci_dump_status(&gohci); */ #endif @@ -1560,7 +1560,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, } if (--timeout) { - wait_ms(1); + mdelay(1); if (!urb->finished) dbg("*"); @@ -1580,7 +1580,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif /* free TDs in urb_priv */ @@ -1607,7 +1607,7 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); #else - wait_ms(1); + mdelay(1); #endif if (!maxsize) { err("submit_control_message: pipesize for pipe %lx is zero", @@ -1677,7 +1677,7 @@ static int hc_reset(ohci_t *ohci) ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus); info("USB HC TakeOver from SMM"); while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { - wait_ms(10); + mdelay(10); if (--smm_timeout == 0) { err("USB HC TakeOver failed!"); return -1; @@ -1813,7 +1813,7 @@ static int hc_interrupt(void) #ifdef DEBUG ohci_dump(ohci, 1); #else - wait_ms(1); + mdelay(1); #endif /* FIXME: be optimistic, hope that bug won't repeat often. */ /* Make some non-interrupt context restart the controller. */ @@ -1824,7 +1824,7 @@ static int hc_interrupt(void) } if (ints & OHCI_INTR_WDH) { - wait_ms(1); + mdelay(1); ohci_writel(OHCI_INTR_WDH, &regs->intrdisable); (void)ohci_readl(&regs->intrdisable); /* flush */ stat = dl_done_list(&gohci); @@ -1841,7 +1841,7 @@ static int hc_interrupt(void) /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ if (ints & OHCI_INTR_SF) { unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1; - wait_ms(1); + mdelay(1); ohci_writel(OHCI_INTR_SF, &regs->intrdisable); if (ohci->ed_rm_list[frame] != NULL) ohci_writel(OHCI_INTR_SF, &regs->intrenable); @@ -1973,7 +1973,7 @@ int usb_lowlevel_init(void) #ifdef DEBUG ohci_dump(&gohci, 1); #else - wait_ms(1); + mdelay(1); #endif ohci_inited = 1; return 0; diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index aa753d8..ab1b8d0 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -497,7 +497,7 @@ static void r8a66597_check_syssts(struct r8a66597 *r8a66597, int port) old_syssts = r8a66597_read(r8a66597, get_syssts_reg(port) & LNST); while (count > 0) { - wait_ms(R8A66597_RH_POLL_TIME); + mdelay(R8A66597_RH_POLL_TIME); syssts = r8a66597_read(r8a66597, get_syssts_reg(port) & LNST); if (syssts == old_syssts) { @@ -511,11 +511,11 @@ static void r8a66597_check_syssts(struct r8a66597 *r8a66597, int port) static void r8a66597_bus_reset(struct r8a66597 *r8a66597, int port) { - wait_ms(10); + mdelay(10); r8a66597_mdfy(r8a66597, USBRST, USBRST | UACT, get_dvstctr_reg(port)); - wait_ms(50); + mdelay(50); r8a66597_mdfy(r8a66597, UACT, USBRST | UACT, get_dvstctr_reg(port)); - wait_ms(50); + mdelay(50); } static int check_usb_device_connecting(struct r8a66597 *r8a66597) @@ -823,7 +823,7 @@ static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe, stat = USB_ST_STALLED; } - wait_ms(1); + mdelay(1); len = min_t(int, len, leni); @@ -918,7 +918,7 @@ int usb_lowlevel_init(void) r8a66597->reg = CONFIG_R8A66597_BASE_ADDR; disable_controller(r8a66597); - wait_ms(100); + mdelay(100); enable_controller(r8a66597); r8a66597_port_power(r8a66597, 0 , 1); @@ -926,7 +926,7 @@ int usb_lowlevel_init(void) /* check usb device */ check_usb_device_connecting(r8a66597); - wait_ms(50); + mdelay(50); return 0; } diff --git a/include/usb.h b/include/usb.h index 4534738..48e4bcd 100644 --- a/include/usb.h +++ b/include/usb.h @@ -199,7 +199,6 @@ int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval); int usb_disable_asynch(int disable); int usb_maxpacket(struct usb_device *dev, unsigned long pipe); -inline void wait_ms(unsigned long ms); int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer, int cfgno); int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, -- 1.7.8.4

4 8

[U-Boot] md,mw commands
by VISWANADHULA BALAJI 06 Mar '12

06 Mar '12

Hi, Iam using 256MB RAM on arm11 board.I just tried md,mw commands from uboot like the following mw C800000 0xbbbbbbbb 0x500 here C800000 is the 200MB of RAM MCS8142>> md C800000 0c800000: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c800010: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c800020: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c800030: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c800040: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c800050: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c800060: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c800070: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c800080: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c800090: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c8000a0: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c8000b0: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c8000c0: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c8000d0: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c8000e0: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ 0c8000f0: bbbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ................ mw 32000000 0xffffffff 0x500 here 32000000 is the 800MB of RAM MCS8142>> md 32000000 32000000: ffffffff ffffffff ffffffff ffffffff ................ 32000010: ffffffff ffffffff ffffffff ffffffff ................ 32000020: ffffffff ffffffff ffffffff ffffffff ................ 32000030: ffffffff ffffffff ffffffff ffffffff ................ 32000040: ffffffff ffffffff ffffffff ffffffff ................ 32000050: ffffffff ffffffff ffffffff ffffffff ................ 32000060: ffffffff ffffffff ffffffff ffffffff ................ 32000070: ffffffff ffffffff ffffffff ffffffff ................ How it is possible to see the data even after the 256MB of RAM.If i give the sizes like 256MB ,512MB mw command get hangs otherwise the data is writing to the RAM even the size exceeds the size of actual RAM. Please help me. Thanks V.Balaji

2 1

[U-Boot] [PATCH] powerpc/85xx:Add PSC9131 RDB Support
by Prabhakar Kushwaha 06 Mar '12

06 Mar '12

PSC9131RDB is a Freescale reference design board for PSC9131 SoC. PSC9131 SOC is an integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements PSC9131RDB Overview ----------------- -1Gbyte DDR3 (on board DDR) -128Mbyte 2K page size NAND Flash -256 Kbit M24256 I2C EEPROM -128 Mbit SPI Flash memory -USB-ULPI -eTSEC1: Connected to RGMII PHY -eTSEC2: Connected to RGMII PHY -DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal(a)freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Applied on git://git.denx.de/u-boot.git (branch master) board/freescale/psc9131rdb/Makefile | 54 +++ board/freescale/psc9131rdb/ddr.c | 186 +++++++++ board/freescale/psc9131rdb/law.c | 31 ++ board/freescale/psc9131rdb/psc9131rdb.c | 116 ++++++ board/freescale/psc9131rdb/tlb.c | 67 ++++ boards.cfg | 2 + doc/README.psc9131rdb | 137 +++++++ include/configs/PSC9131RDB.h | 484 +++++++++++++++++++++++ nand_spl/board/freescale/psc9131rdb/Makefile | 145 +++++++ nand_spl/board/freescale/psc9131rdb/nand_boot.c | 122 ++++++ 10 files changed, 1344 insertions(+), 0 deletions(-) create mode 100644 board/freescale/psc9131rdb/Makefile create mode 100644 board/freescale/psc9131rdb/ddr.c create mode 100644 board/freescale/psc9131rdb/law.c create mode 100644 board/freescale/psc9131rdb/psc9131rdb.c create mode 100644 board/freescale/psc9131rdb/tlb.c create mode 100644 doc/README.psc9131rdb create mode 100644 include/configs/PSC9131RDB.h create mode 100644 nand_spl/board/freescale/psc9131rdb/Makefile create mode 100644 nand_spl/board/freescale/psc9131rdb/nand_boot.c diff --git a/board/freescale/psc9131rdb/Makefile b/board/freescale/psc9131rdb/Makefile new file mode 100644 index 0000000..0d01b8d --- /dev/null +++ b/board/freescale/psc9131rdb/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2011-2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o +#COBJS-y += psc9131rdb_mux.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/board/freescale/psc9131rdb/ddr.c b/board/freescale/psc9131rdb/ddr.c new file mode 100644 index 0000000..7e5db83 --- /dev/null +++ b/board/freescale/psc9131rdb/ddr.c @@ -0,0 +1,186 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_DRAM_SIZE 1024 + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {0, 0, NULL} +}; + +unsigned long get_sdram_size(void) +{ + return CONFIG_SYS_DRAM_SIZE; +} + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, + LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + + return ddr_size; +} + +#else /* CONFIG_SYS_DDR_RAW_TIMING */ +/* Micron MT41J256M8HX-15E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1870, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} + +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/psc9131rdb/law.c b/board/freescale/psc9131rdb/law.c new file mode 100644 index 0000000..201c147 --- /dev/null +++ b/board/freescale/psc9131rdb/law.c @@ -0,0 +1,31 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/psc9131rdb/psc9131rdb.c b/board/freescale/psc9131rdb/psc9131rdb.c new file mode 100644 index 0000000..59b4124 --- /dev/null +++ b/board/freescale/psc9131rdb/psc9131rdb.c @@ -0,0 +1,116 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <netdev.h> + + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS); + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK | + MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD); + setbits_be32(HALTED_TO_HALT_REQ_MASK_REG, HALTED_TO_HALT_REQ_MASK_0); + clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK | + MPC85xx_PMUXCR_IFC_AD17_GPO_MASK, + MPC85xx_PMUXCR_IFC_AD_GPIO | + MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM); + + return 0; +} + +int checkboard(void) +{ + struct cpu_type *cpu; + + cpu = gd->cpu; + printf("Board: %sRDB\n", cpu->name); + + return 0; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[2]; + + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif + +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + tsec_eth_init(bis, tsec_info, num); + + return 0; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/psc9131rdb/tlb.c b/board/freescale/psc9131rdb/tlb.c new file mode 100644 index 0000000..5b68f4a --- /dev/null +++ b/board/freescale/psc9131rdb/tlb.c @@ -0,0 +1,67 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR (PA) */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1M, 1) + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 2f90dbf..8ea52bb 100644 --- a/boards.cfg +++ b/boards.cfg @@ -755,6 +755,8 @@ P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +PSC9131RDB_NAND powerpc mpc85xx psc9131rdb freescale - PSC9131RDB:PSC9131RDB,NAND +PSC9131RDB_SPIFLASH powerpc mpc85xx psc9131rdb freescale - PSC9131RDB:PSC9131RDB,SPIFLASH stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/doc/README.psc9131rdb b/doc/README.psc9131rdb new file mode 100644 index 0000000..9151de0 --- /dev/null +++ b/doc/README.psc9131rdb @@ -0,0 +1,137 @@ +Overview +-------- +- PSC9131 is integrated device that targets Femto base station market. + It combines Power Architecture e500v2 and DSP StarCore SC3850 core + technologies with MAPLE-B2F baseband acceleration processing elements. +- It's MAPLE disabled personality is called 9231. + +The PSC9131 SoC includes the following function and features: +. Power Architecture subsystem including a e500 processor with 256-Kbyte shared + L2 cache +. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache +. The Multi Accelerator Platform Engine for Femto BaseStation Baseband + Processing (MAPLE-B2F) +. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, + Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, + and CRC algorithms +. Consists of accelerators for Convolution, Filtering, Turbo Encoding, + Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion + operations +. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with + ECC, up to 400-MHz clock/800 MHz data rate +. Dedicated security engine featuring trusted boot +. DMA controller +. OCNDMA with four bidirectional channels +. Interfaces +. Two triple-speed Gigabit Ethernet controllers featuring network acceleration + including IEEE 1588. v2 hardware support and virtualization (eTSEC) +. eTSEC 1 supports RGMII/RMII +. eTSEC 2 supports RGMII +. High-speed USB 2.0 host and device controller with ULPI interface +. Enhanced secure digital (SD/MMC) host controller (eSDHC) +. Antenna interface controller (AIC), supporting three industry standard + JESD207/three custom ADI RF interfaces (two dual port and one single port) + and three MAXIM's MaxPHY serial interfaces +. ADI lanes support both full duplex FDD support and half duplex TDD support +. Universal Subscriber Identity Module (USIM) interface that facilitates + communication to SIM cards or Eurochip pre-paid phone cards +. TDM with one TDM port +. Two DUART, four eSPI, and two I2C controllers +. Integrated Flash memory controller (IFC) +. TDM with 256 channels +. GPIO +. Sixteen 32-bit timers + +The e500 core subsystem within the Power Architecture consists of the following: +. 32-Kbyte L1 instruction cache +. 32-Kbyte L1 data cache +. 256-Kbyte L2 cache/L2 memory/L2 stash +. programmable interrupt controller (PIC) +. Debug support +. Timers + +The SC3850 core subsystem consists of the following: +. 32 Kbyte 8-way level 1 instruction cache (L1 ICache) +. 32 Kbyte 8-way level 1 data cache (L1 DCache) +. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory) +. Memory management unit (MMU) +. Enhanced programmable interrupt controller (EPIC) +. Debug and profiling unit (DPU) +. Two 32-bit timers + +PSC9131RDB board Overview +------------------------- + 1Gbyte DDR3 (on board DDR) + 128Mbyte 2K page size NAND Flash + 256 Kbit M24256 I2C EEPROM + 128 Mbit SPI Flash memory + USB-ULPI + eTSEC1: Connected to RGMII PHY + eTSEC2: Connected to RGMII PHY + DUART interface: supports one UARTs up to 115200 bps for console display + USIM connector + +Frequency Combinations Supported +-------------------------------- +Core MHz/CCB MHz/DDR(MT/s) +1. 1000/500/800 +2. 800/400/667 + +Boot Methods Supported +----------------------- +1. NAND Flash +2. SPI Flash + +Default Boot Method +-------------------- +NAND boot + +Building U-boot +-------------- +To build the u-boot for PSC9131RDB: +1. NAND Flash + make PSC9131RDB_NAND +2. SPI Flash + make PSC9131RDB_SPIFLASH + +Memory map +----------- + 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable + 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M + 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K + 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K + 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K + 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M + 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M + +Flashing Images +--------------- +To place a new u-boot image in the NAND flash and then boot +with that new image temporarily, use this: + tftp 1000000 u-boot-nand.bin + nand erase 0 100000 + nand write 1000000 0 100000 + reset + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb psc9131rdb.dts > psc9131rdb.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/psc9131rdb.dts + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 psc9131rdb.dtb + bootm 1000000 2000000 c00000 diff --git a/include/configs/PSC9131RDB.h b/include/configs/PSC9131RDB.h new file mode 100644 index 0000000..b9c6224 --- /dev/null +++ b/include/configs/PSC9131RDB.h @@ -0,0 +1,484 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PSC9131 RDB board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_PSC9131RDB +#define CONFIG_PSC9131 +#define CONFIG_NAND_FSL_IFC +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifdef CONFIG_NAND /* NAND Boot */ +#define CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_NAND_U_BOOT +#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000 +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL +#else +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#endif /* CONFIG_NAND_SPL */ +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ +#define CONFIG_FSL_IFC /* Enable IFC Support */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_TSEC_ENET +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x1fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#undef CONFIG_SYS_DDR_RAW_TIMING +#undef CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ +#define CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#ifndef __ASSEMBLY__ +extern unsigned long get_sdram_size(void); +#endif +#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +/* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT + +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ + /* CONFIG_SYS_IMMR */ + +/* + * Memory map + * + * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable + * 0x8800_0000 0x8810_0000 NAND memory 1M + * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K + * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K + * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M + * + */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NO_FLASH + +/* NAND Flash on IFC */ +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +/* NAND Flash Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ + | FTIM0_NAND_TWP(0x06) \ + | FTIM0_NAND_TWCHT(0x03) \ + | FTIM0_NAND_TWH(0x04)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ + | FTIM1_NAND_TWBE(0x23) \ + | FTIM1_NAND_TRR(0x08) \ + | FTIM1_NAND_TRP(0x05)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ + | FTIM2_NAND_TREH(0x04) \ + | FTIM2_NAND_TWHRE(0x3f)) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* Set up IFC registers for boot location NAND */ +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* NAND boot: 8K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x2000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +/* Seconed UART port is connected to GPS */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_OFFSET 0x3000 + +/* I2C EEPROM */ +#undef CONFIG_ID_EEPROM +/* enable read and write access to EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_CMD_I2C + + +#define CONFIG_FSL_ESPI +/* eSPI - Enhanced SPI */ +#ifdef CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 + +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_NAND_U_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x400 +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_DHCP +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#endif + + +#define CONFIG_HOSTNAME 9131rdb +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "loadaddr=1000000\0" \ + "bootfile=uImage\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=psc9131rdb.dtb\0" \ + "bdev=sda1\0" \ + "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ + "othbootargs=ramdisk_size=600000 \0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/nand_spl/board/freescale/psc9131rdb/Makefile b/nand_spl/board/freescale/psc9131rdb/Makefile new file mode 100644 index 0000000..c851b68 --- /dev/null +++ b/nand_spl/board/freescale/psc9131rdb/Makefile @@ -0,0 +1,145 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# Copyright 2011-2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +CONFIG_SYS_TEXT_BASE_SPL := 0xff800000 +PAD_TO := 0xff802000 + +include $(TOPDIR)/config.mk + +nandobj := $(OBJTREE)/nand_spl/ + +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \ + $(LDFLAGS_FINAL) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL +ifdef CONFIG_CW +AFLAGS += -Wa,-gdwarf2 +CFLAGS += -g2 -gdwarf-2 +endif + +SOBJS = start.o resetvec.o ticks.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(nandobj)board/$(BOARDDIR) + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_ifc.c: + @rm -f $(obj)nand_boot_fsl_ifc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \ + $(obj)nand_boot_fsl_ifc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S + +$(obj)ticks.S: + @rm -f $(obj)ticks.S + ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/psc9131rdb/nand_boot.c b/nand_spl/board/freescale/psc9131rdb/nand_boot.c new file mode 100644 index 0000000..58998cf --- /dev/null +++ b/nand_spl/board/freescale/psc9131rdb/nand_boot.c @@ -0,0 +1,122 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <mpc85xx.h> +#include <asm/io.h> +#include <ns16550.h> +#include <nand.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_law.h> + +#define udelay(x) \ + {int i, j; for (i = 0; i < x; i++) for (j = 0; j < 10000; j++); } + +unsigned long ddr_freq_mhz; + +void sdram_init(void) +{ + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); + out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); +#endif + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); + out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800); + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800); + out_be32(&ddr->ddr_wrlvl_cntl, + CONFIG_SYS_DDR_WRLVL_CONTROL_800); + + out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); + out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); + out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); + + asm volatile("sync;isync"); + udelay(500); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); + + set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, ddr_ratio; + unsigned long bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; + ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* Initialize the DDR3 */ + sdram_init(); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} -- 1.7.5.4

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[U-Boot] Building imximage for mx53ard board, supporting NAND and YAFFS2
by Bud Miljkovic 06 Mar '12

06 Mar '12

Hi Fabio, I understand, from the MAINTAINERS file list, that you are the maintainer for the mx53ard board. I took a copy of the u-boot sources for the Freescale SABRE Automotive Infotainment board (aka mx53ard board) from the Freescale site. As the result I got the u-boot-2009.08 building tree directory along with the associated cross compiler gcc-4.4.4-glibc-2.11.1-multilib-1.0-1.386 tools. After some trial and error I managed to configure the mx53_ard_dd3.h for NAND and YAFFS2 support and successfully ran make, resulting in creation of the following files: * u-boot * u-boot.bin * u-boot.srec * u-boot.map * u-boot.lds However, I would want to initially boot from SD-card and I would like to be able to generate an imx image of the u-boot when running make. I looked at the Makefile from the Freescale release of u-boot-2009.08 and saw that it is fairly outdated - it does not support making of u-boot.imx image. At the same time I see that the general denx distribution (u-boot-2011.12) of u-boot sources does have the support for making u-boot.imx image in its Makefile. So I am wondering if a patch that can be applied to the u-boot-2009.08 Freescale u-boot source that will bring the make tools up to date and able to make u-boot.imx file does exist? Failing that, is there another way to configure the denx u-boot-2011.12 release to support NAND and YAFFS2 and thus, by successfully compiling, generate a u-boot.imx image file. Cheers, Bud Miljkovic

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