March 2012 - U-Boot

[U-Boot] [PATCH V2 0/5] USB: Add support for designware UDC
by Amit Virdi 07 Mar '12

07 Mar '12

Support for designware USB device controller (UDC) exists in the u-boot for SPEAr platform. This patchset makes the driver more generic so that it can be used across multiple platforms. V2: - Configure the gadget in HS only if CONFIG_USBD_HS is defined - Made local functions static in a separate commit - In "Fix memory nonalignment issue" used memcpy instead of copying byte-by-byte - Define the HS_PACKET_SIZE unconditionally V1: - Added support for designware UDC in a more generic way Amit Virdi (1): USB:gadget:designware Make locally used functions static Shiraz Hashim (1): USB:gadget:designware Fix memory nonalignment issue Vipin KUMAR (3): USB:gadget:designware USB device controller (UDC) implementation USB:gadget:designware Device controller bugfixes USB:gadget:designware Support high speed drivers/serial/usbtty.h | 4 +- drivers/usb/gadget/Makefile | 2 +- drivers/usb/gadget/{spr_udc.c => designware_udc.c} | 138 ++++++++++++------- include/configs/spear-common.h | 4 +- include/usb/{spr_udc.h => designware_udc.h} | 7 +- 5 files changed, 97 insertions(+), 58 deletions(-) rename drivers/usb/gadget/{spr_udc.c => designware_udc.c} (89%) rename include/usb/{spr_udc.h => designware_udc.h} (98%) -- 1.7.2.2

5 9

[U-Boot] [PATCH] USB:host: Attribute packed removed from usb structures
by Amit Virdi 07 Mar '12

07 Mar '12

From: Vipin Kumar <vipin.kumar(a)st.com> Packed attribute is forcing a bytewise write on device registers, there by, resulting in a misbehavior on gcc-4.4.1. Reverting the structures to non-packed Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> Signed-off-by: Amit Virdi <amit.virdi(a)st.com> --- drivers/usb/host/ehci.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 3d0ad0c..df9f055 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -55,7 +55,7 @@ struct ehci_hccr { #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) uint32_t cr_hccparams; uint8_t cr_hcsp_portrt[8]; -} __attribute__ ((packed, aligned(4))); +}; struct ehci_hcor { uint32_t or_usbcmd; @@ -85,7 +85,7 @@ struct ehci_hcor { #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; uint32_t or_systune; -} __attribute__ ((packed, aligned(4))); +}; #define USBMODE 0x68 /* USB Device mode */ #define USBMODE_SDIS (1 << 3) /* Stream disable */ -- 1.7.2.2

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[U-Boot] [PATCH 1/5] mx31ads: Provide proper range for memtest
by Fabio Estevam 07 Mar '12

07 Mar '12

memtest adresses should contain proper DRAM address range. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/mx31ads.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 87638a4..fe073ba 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -146,8 +146,8 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2) +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- 1.7.1

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[U-Boot] [PATCH 1/8 v3] powerpc/srio: Rewrite the struct ccsr_rio
by Liu Gang 07 Mar '12

07 Mar '12

Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu(a)freescale.com> --- Changes in v2: - Change the subject and commit message. - Remove the offsets in the comments. - Rewrite the struct for the support of two ports and two message units registers. Changes in v3: - Move some SRIO macros to the appropriate board configure header files. arch/powerpc/include/asm/immap_85xx.h | 384 +++++++++++++++++++-------------- include/configs/MPC8548CDS.h | 5 + include/configs/MPC8568MDS.h | 5 + include/configs/MPC8569MDS.h | 5 + include/configs/P2020DS.h | 5 + include/configs/P2041RDB.h | 3 + include/configs/corenet_ds.h | 7 + 7 files changed, 254 insertions(+), 160 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9b08cb8..42db6c9 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1353,171 +1353,235 @@ typedef struct ccsr_cpm { } ccsr_cpm_t; #endif -/* RapidIO Registers */ -typedef struct ccsr_rio { - u32 didcar; /* Device Identity Capability */ - u32 dicar; /* Device Information Capability */ - u32 aidcar; /* Assembly Identity Capability */ - u32 aicar; /* Assembly Information Capability */ - u32 pefcar; /* Processing Element Features Capability */ - u32 spicar; /* Switch Port Information Capability */ - u32 socar; /* Source Operations Capability */ - u32 docar; /* Destination Operations Capability */ +#ifdef CONFIG_SYS_SRIO +/* Architectural regsiters */ +struct rio_arch { + u32 didcar; /* Device Identity CAR */ + u32 dicar; /* Device Information CAR */ + u32 aidcar; /* Assembly Identity CAR */ + u32 aicar; /* Assembly Information CAR */ + u32 pefcar; /* Processing Element Features CAR */ + u8 res0[4]; + u32 socar; /* Source Operations CAR */ + u32 docar; /* Destination Operations CAR */ u8 res1[32]; - u32 msr; /* Mailbox Cmd And Status */ - u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ + u32 mcsr; /* Mailbox CSR */ + u32 pwdcsr; /* Port-Write and Doorbell CSR */ u8 res2[4]; u32 pellccsr; /* Processing Element Logic Layer CCSR */ u8 res3[12]; - u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ - u32 bdidcsr; /* Base Device ID Cmd & Status */ + u32 lcsbacsr; /* Local Configuration Space BACSR */ + u32 bdidcsr; /* Base Device ID CSR */ u8 res4[4]; - u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ - u32 ctcsr; /* Component Tag Cmd & Status */ - u8 res5[144]; - u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ - u8 res6[28]; - u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ - u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ - u8 res7[20]; - u32 pgccsr; /* Port General Cmd & Status */ - u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ - u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ - u32 plascsr; /* Port Local Ackid Status Cmd & Status */ - u8 res8[12]; - u32 pescsr; /* Port Error & Status Cmd & Status */ - u32 pccsr; /* Port Control Cmd & Status */ - u8 res9[65184]; - u32 cr; /* Port Control Cmd & Status */ - u8 res10[12]; - u32 pcr; /* Port Configuration */ - u32 peir; /* Port Error Injection */ - u8 res11[3048]; - u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ - u8 res12[12]; - u32 rowar0; /* RIO Outbound Attrs 0 */ - u8 res13[12]; - u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ - u8 res14[4]; - u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ - u8 res15[4]; - u32 rowar1; /* RIO Outbound Attrs 1 */ - u8 res16[12]; - u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ - u8 res17[4]; - u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ - u8 res18[4]; - u32 rowar2; /* RIO Outbound Attrs 2 */ - u8 res19[12]; - u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ - u8 res20[4]; - u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ - u8 res21[4]; - u32 rowar3; /* RIO Outbound Attrs 3 */ - u8 res22[12]; - u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ - u8 res23[4]; - u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ - u8 res24[4]; - u32 rowar4; /* RIO Outbound Attrs 4 */ - u8 res25[12]; - u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ - u8 res26[4]; - u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ - u8 res27[4]; - u32 rowar5; /* RIO Outbound Attrs 5 */ - u8 res28[12]; - u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ - u8 res29[4]; - u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ - u8 res30[4]; - u32 rowar6; /* RIO Outbound Attrs 6 */ - u8 res31[12]; - u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ - u8 res32[4]; - u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ - u8 res33[4]; - u32 rowar7; /* RIO Outbound Attrs 7 */ - u8 res34[12]; - u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ - u8 res35[4]; - u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ - u8 res36[4]; - u32 rowar8; /* RIO Outbound Attrs 8 */ - u8 res37[76]; - u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ - u8 res38[4]; - u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ - u8 res39[4]; - u32 riwar4; /* RIO Inbound Attrs 4 */ - u8 res40[12]; - u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ - u8 res41[4]; - u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ - u8 res42[4]; - u32 riwar3; /* RIO Inbound Attrs 3 */ - u8 res43[12]; - u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ - u8 res44[4]; - u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ - u8 res45[4]; - u32 riwar2; /* RIO Inbound Attrs 2 */ - u8 res46[12]; - u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ - u8 res47[4]; - u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ - u8 res48[4]; - u32 riwar1; /* RIO Inbound Attrs 1 */ - u8 res49[12]; - u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ - u8 res50[12]; - u32 riwar0; /* RIO Inbound Attrs 0 */ - u8 res51[12]; - u32 pnfedr; /* Port Notification/Fatal Error Detect */ - u32 pnfedir; /* Port Notification/Fatal Error Detect */ - u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ - u32 pecr; /* Port Error Control */ - u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ - u32 pepr1; /* Port Error Packet 1 */ - u32 pepr2; /* Port Error Packet 2 */ - u8 res52[4]; - u32 predr; /* Port Recoverable Error Detect */ - u8 res53[4]; - u32 pertr; /* Port Error Recovery Threshold */ - u32 prtr; /* Port Retry Threshold */ - u8 res54[464]; - u32 omr; /* Outbound Mode */ - u32 osr; /* Outbound Status */ - u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ - u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ - u32 eosar; /* Extended Outbound Unit Source Addr */ - u32 osar; /* Outbound Unit Source Addr */ - u32 odpr; /* Outbound Destination Port */ - u32 odatr; /* Outbound Destination Attrs */ - u32 odcr; /* Outbound Doubleword Count */ - u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ - u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ - u8 res55[52]; - u32 imr; /* Outbound Mode */ - u32 isr; /* Inbound Status */ - u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ - u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ - u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ - u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ - u8 res56[1000]; - u32 dmr; /* Doorbell Mode */ - u32 dsr; /* Doorbell Status */ - u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ - u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ - u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ - u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ - u8 res57[104]; - u32 pwmr; /* Port-Write Mode */ - u32 pwsr; /* Port-Write Status */ - u32 epwqbar; /* Extended Port-Write Queue Base Addr */ - u32 pwqbar; /* Port-Write Queue Base Addr */ - u8 res58[60176]; -} ccsr_rio_t; + u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ + u32 ctcsr; /* Component Tag CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial Port registers */ +struct rio_lp_serial_port { + u32 plmreqcsr; /* Port Link Maintenance Request CSR */ + u32 plmrespcsr; /* Port Link Maintenance Response CS */ + u32 plascsr; /* Port Local Ackid Status CSR */ + u8 res0[12]; + u32 pescsr; /* Port Error and Status CSR */ + u32 pccsr; /* Port Control CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial registers */ +struct rio_lp_serial { + u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ + u8 res0[28]; + u32 pltoccsr; /* Port Link Time-out CCSR */ + u32 prtoccsr; /* Port Response Time-out CCSR */ + u8 res1[20]; + u32 pgccsr; /* Port General CSR */ + struct rio_lp_serial_port port[CONFIG_SRIO_PORT_MAX_NUM]; +}; + +/* Logical error reporting registers */ +struct rio_logical_err { + u32 erbh; /* Error Reporting Block Header Register */ + u8 res0[4]; + u32 ltledcsr; /* Logical/Transport layer error DCSR */ + u32 ltleecsr; /* Logical/Transport layer error ECSR */ + u8 res1[4]; + u32 ltlaccsr; /* Logical/Transport layer ACCSR */ + u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ + u32 ltlcccsr; /* Logical/Transport layer control CCSR */ +}; + +/* Physical error reporting port registers */ +struct rio_phys_err_port { + u32 edcsr; /* Port error detect CSR */ + u32 erecsr; /* Port error rate enable CSR */ + u32 ecacsr; /* Port error capture attributes CSR */ + u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ + u32 peccsr[3]; /* Port error capture CSR */ + u8 res0[12]; + u32 ercsr; /* Port error rate CSR */ + u32 ertcsr; /* Port error rate threshold CSR */ + u8 res1[16]; +}; + +/* Physical error reporting registers */ +struct rio_phys_err { + struct rio_phys_err_port port[CONFIG_SRIO_PORT_MAX_NUM]; +}; + +/* Implementation Space: General Port-Common */ +struct rio_impl_common { + u8 res0[4]; + u32 llcr; /* Logical Layer Configuration Register */ + u8 res1[8]; + u32 epwisr; /* Error / Port-Write Interrupt SR */ + u8 res2[12]; + u32 lretcr; /* Logical Retry Error Threshold CR */ + u8 res3[92]; + u32 pretcr; /* Physical Retry Erorr Threshold CR */ + u8 res4[124]; +}; + +/* Implementation Space: Port Specific */ +struct rio_impl_port_spec { + u32 adidcsr; /* Port Alt. Device ID CSR */ + u8 res0[28]; + u32 ptaacr; /* Port Pass-Through/Accept-All CR */ + u32 lopttlcr; + u8 res1[8]; + u32 iecsr; /* Port Implementation Error CSR */ + u8 res2[12]; + u32 pcr; /* Port Phsyical Configuration Register */ + u8 res3[20]; + u32 slcsr; /* Port Serial Link CSR */ + u8 res4[4]; + u32 sleicr; /* Port Serial Link Error Injection */ + u32 a0txcr; /* Port Arbitration 0 Tx CR */ + u32 a1txcr; /* Port Arbitration 1 Tx CR */ + u32 a2txcr; /* Port Arbitration 2 Tx CR */ + u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ + u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ +}; + +/* Implementation Space: register */ +struct rio_implement { + struct rio_impl_common com; + struct rio_impl_port_spec port[CONFIG_SRIO_PORT_MAX_NUM]; +}; + +/* Revision Control Register */ +struct rio_rev_ctrl { + u32 ipbrr[2]; /* IP Block Revision Register */ +}; + +struct rio_atmu_row { + u32 rowtar; /* RapidIO Outbound Window TAR */ + u32 rowtear; /* RapidIO Outbound Window TEAR */ + u32 rowbar; + u8 res0[4]; + u32 rowar; /* RapidIO Outbound Attributes Register */ + u32 rowsr[3]; /* Port RapidIO outbound window segment register */ +}; + +struct rio_atmu_riw { + u32 riwtar; /* RapidIO Inbound Window Translation AR */ + u8 res0[4]; + u32 riwbar; /* RapidIO Inbound Window Base AR */ + u8 res1[4]; + u32 riwar; /* RapidIO Inbound Attributes Register */ + u8 res2[12]; +}; + +/* ATMU window registers */ +struct rio_atmu_win { + struct rio_atmu_row outbw[CONFIG_SRIO_OB_WIN_NUM]; + u8 res0[64]; + struct rio_atmu_riw inbw[CONFIG_SRIO_IB_WIN_NUM]; +}; + +struct rio_atmu { + struct rio_atmu_win port[CONFIG_SRIO_PORT_MAX_NUM]; +}; + +#ifdef CONFIG_SYS_RMU +struct rio_msg { + u32 omr; /* Outbound Mode Register */ + u32 osr; /* Outbound Status Register */ + u32 eodqdpar; /* Extended Outbound DQ DPAR */ + u32 odqdpar; /* Outbound Descriptor Queue DPAR */ + u32 eosar; /* Extended Outbound Unit Source AR */ + u32 osar; /* Outbound Unit Source AR */ + u32 odpr; /* Outbound Destination Port Register */ + u32 odatr; /* Outbound Destination Attributes Register */ + u32 odcr; /* Outbound Doubleword Count Register */ + u32 eodqepar; /* Extended Outbound DQ EPAR */ + u32 odqepar; /* Outbound Descriptor Queue EPAR */ + u32 oretr; /* Outbound Retry Error Threshold Register */ + u32 omgr; /* Outbound Multicast Group Register */ + u32 omlr; /* Outbound Multicast List Register */ + u8 res0[40]; + u32 imr; /* Outbound Mode Register */ + u32 isr; /* Inbound Status Register */ + u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ + u32 idqdpar; /* Inbound Descriptor Queue DPAR */ + u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ + u32 ifqepar; /* Inbound Frame Queue EPAR */ + u32 imirir; /* Inbound Maximum Interrutp RIR */ + u8 res1[4]; + u32 eihqepar; /* Extended inbound message header queue EPAR */ + u32 ihqepar; /* Inbound message header queue EPAR */ + u8 res2[120]; +}; + +struct rio_dbell { + u32 odmr; /* Outbound Doorbell Mode Register */ + u32 odsr; /* Outbound Doorbell Status Register */ + u8 res0[16]; + u32 oddpr; /* Outbound Doorbell Destination Port */ + u32 oddatr; /* Outbound Doorbell Destination AR */ + u8 res1[12]; + u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ + u8 res2[48]; + u32 idmr; /* Inbound Doorbell Mode Register */ + u32 idsr; /* Inbound Doorbell Status Register */ + u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ + u32 iqdpar; /* Inbound Doorbell Queue DPAR */ + u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ + u32 idqepar; /* Inbound Doorbell Queue EPAR */ + u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ +}; + +struct rio_pw { + u32 pwmr; /* Port-Write Mode Register */ + u32 pwsr; /* Port-Write Status Register */ + u32 epwqbar; /* Extended Port-Write Queue BAR */ + u32 pwqbar; /* Port-Write Queue Base Address Register */ +}; +#endif + +/* RapidIO Registers */ +struct ccsr_rio { + struct rio_arch arch; + u8 res0[144]; + struct rio_lp_serial lp_serial; + u8 res1[1152]; + struct rio_logical_err logical_err; + u8 res2[32]; + struct rio_phys_err phys_err; + u8 res3[63808]; + struct rio_implement impl; + u8 res4[2552]; + struct rio_rev_ctrl rev; + struct rio_atmu atmu; +#ifdef CONFIG_SYS_RMU + u8 res5[8192]; + struct rio_msg msg[CONFIG_SRIO_MSG_UNIT_NUM]; + u8 res6[512]; + struct rio_dbell dbell; + u8 res7[100]; + struct rio_pw pw; +#endif +}; +#endif /* Quick Engine Block Pin Muxing Registers */ typedef struct par_io { diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1a6ba69..339749b 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -46,6 +46,11 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO_PORT_MAX_NUM 1 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */ #define CONFIG_PCI /* enable any pci type devices */ #define CONFIG_PCI1 /* PCI controller 1 */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index f9c8dfb..d2c1500 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -37,6 +37,11 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO_PORT_MAX_NUM 1 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 7a5d86d..c5a2115 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -37,6 +37,11 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO_PORT_MAX_NUM 1 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */ #define CONFIG_PCI 1 /* Disable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controller */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index f0eb029..d98a93e 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -66,6 +66,11 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PORT_MAX_NUM 2 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */ #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index da98f8f..6cf4eb4 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -67,6 +67,9 @@ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CONFIG_SRIO_PORT_MAX_NUM 2 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ #define CONFIG_FSL_LAW /* Use common FSL init code */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 77dd0a2..5067bb7 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -62,6 +62,13 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PORT_MAX_NUM 2 /* SRIO port max number */ +#define CONFIG_SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define CONFIG_SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#ifndef CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_RMU +#define CONFIG_SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */ +#endif #define CONFIG_FSL_LAW /* Use common FSL init code */ -- 1.7.3.1

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[U-Boot] [PATCH] mx31: add "ARM11P power gating" to get_reset_cause
by Helmut Raiger 07 Mar '12

07 Mar '12

Add missing reset reason 7 to get_reset_cause(). Signed-off-by: Helmut Raiger <helmut.raiger(a)hale.at> --- arch/arm/cpu/arm1136/mx31/generic.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index d60afc9..8873fb7 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -210,6 +210,8 @@ static char *get_reset_cause(void) return "WDOG"; case 0x0006: return "JTAG"; + case 0x0007: + return "ARM11P power gating"; default: return "unknown reset"; } -- 1.7.4.4 -- Scanned by MailScanner.

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[U-Boot] [PATCH] st_smi: Change timeout loop implementation
by Amit Virdi 07 Mar '12

07 Mar '12

There are two problems in the current timeout loop implementation: 1. In case initial test failing, there will always be a delay of 1 ms 2. The delay duration is not tunable The new implementation addresses both these limitations. Signed-off-by: Amit Virdi <amit.virdi(a)st.com> --- drivers/mtd/st_smi.c | 27 +++++++++++++++++---------- 1 files changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 6d4edba..bd5602b 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -102,11 +102,15 @@ static struct flash_device flash_devices[] = { */ static int smi_wait_xfer_finish(int timeout) { - do { + ulong start = get_timer(0); + + while (get_timer(start) < timeout) { if (readl(&smicntl->smi_sr) & TFF) return 0; - udelay(1000); - } while (timeout--); + + /* Try after 10 ms */ + udelay(10); + }; return -1; } @@ -219,16 +223,17 @@ static int smi_read_sr(int bank) static int smi_wait_till_ready(int bank, int timeout) { int sr; + ulong start = get_timer(0); /* One chip guarantees max 5 msec wait here after page writes, but potentially three seconds (!) after page erase. */ - do { + while (get_timer(start) < timeout) { sr = smi_read_sr(bank); if ((sr >= 0) && (!(sr & WIP_BIT))) return 0; - /* Try again after 1m-sec */ - udelay(1000); + /* Try again after 10 usec */ + udelay(10); } while (timeout--); printf("SMI controller is still in wait, timeout=%d\n", timeout); @@ -245,6 +250,7 @@ static int smi_wait_till_ready(int bank, int timeout) static int smi_write_enable(int bank) { u32 ctrlreg1; + u32 start; int timeout = WMODE_TOUT; int sr; @@ -263,14 +269,15 @@ static int smi_write_enable(int bank) /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); - do { + start = get_timer(0); + while (get_timer(start) < timeout) { sr = smi_read_sr(bank); if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT)))) return 0; - /* Try again after 1m-sec */ - udelay(1000); - } while (timeout--); + /* Try again after 10 usec */ + udelay(10); + }; return -1; } -- 1.7.2.2

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[U-Boot] [PATCH v2] imximage: Remove overwriting of flash_offset
by Dirk Behme 07 Mar '12

07 Mar '12

The flash header supports different flash offsets for different boot devices. E.g. parallel NOR or OneNAND use a different offset than FLASH_OFFSET_STANDARD (== 0x400). The flash offset is correctly read from the configuration in parse_cfg_cmd(). But is then overwritten wrongly in set_imx_hdr_v1/2(). Fix this by removing this overwriting. Use the flash offset correctly read from the configuration, instead. If there is no flash_offset read from the configuration file, i.e. the BOOT_FROM tag is missing, exit with an error message. Signed-off-by: Dirk Behme <dirk.behme(a)de.bosch.com> CC: Jason Liu <liu.h.jason(a)gmail.com> CC: Stefano Babic <sbabic(a)denx.de> --- Changes in v2: Make the BOOT_FROM field mandatory, i.e. exit with an error message if there is no valid flash_offset set. Do the same handling in header v1 and v2, not only in v2. Note: This is tested only for header v2. tools/imximage.c | 18 ++++++++++++++---- tools/imximage.h | 1 + 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/tools/imximage.c b/tools/imximage.c index 1e0f5d4..03a7716 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -216,8 +216,12 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len, dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table; uint32_t base_offset; - /* Set default offset */ - imxhdr->flash_offset = FLASH_OFFSET_STANDARD; + /* Exit if there is no BOOT_FROM field specifying the flash_offset */ + if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) { + fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n", + params->imagename); + exit(EXIT_FAILURE); + } /* Set magic number */ fhdr_v1->app_code_barker = APP_CODE_BARKER; @@ -253,8 +257,12 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len, imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2; flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr; - /* Set default offset */ - imxhdr->flash_offset = FLASH_OFFSET_STANDARD; + /* Exit if there is no BOOT_FROM field specifying the flash_offset */ + if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) { + fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n", + params->imagename); + exit(EXIT_FAILURE); + } /* Set magic number */ fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */ @@ -525,6 +533,8 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd, * set up function ptr group to V1 by default. */ imximage_version = IMXIMAGE_V1; + /* Be able to detect if the cfg file has no BOOT_FROM tag */ + imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED; set_hdr_func(imxhdr); /* Parse dcd configuration file */ diff --git a/tools/imximage.h b/tools/imximage.h index d784a8d..34f293d 100644 --- a/tools/imximage.h +++ b/tools/imximage.h @@ -32,6 +32,7 @@ #define HEADER_OFFSET 0x400 #define CMD_DATA_STR "DATA" +#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF #define FLASH_OFFSET_STANDARD 0x400 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD -- 1.7.0.4

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[U-Boot] Problem in loading kernel image by u-boot..
by Manish 07 Mar '12

07 Mar '12

Hi, I have Uboot loaded in my Coldire processor. My Kernel build for uClinux finally created few files (image.bin linux.bin romfs.img romfs-inst.log) in the images folder and copied image.bin to the /tftp of my system. So, I think image.bin is the one which will be loaded in my coldfire board. But when I tried load it (by TeraTerm) in coldfire with below u-boot commands(tftp and bootm), it fails with error: -> tftp 0x41000000 uImage-5329 (renamed image.bin ) -> bootm 0x41000000 Wrong Image Format for bootm command ERROR: can't get kernel image! Can you please tell me how to make this binary loadable by uboot? my u-boot version is below: U-Boot 2008.10 (Dec 15 2008 - 11:03:39) CPU: Freescale MCF5329 (Mask:54 Version:2) CPU CLK 240 MHz BUS CLK 80 MHz Board: Freescale FireEngine 5329 EVB I2C: ready DRAM: 32 MB FLASH: 2 MB In: serial Out: serial Err: serial NAND: 16 MiB Net: FEC0 Thnaks & Regards, Manish

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[U-Boot] Please pull u-boot-ti/master
by Tom Rini 07 Mar '12

07 Mar '12

Hello, The following changes since commit 3513896e57c6757c411e0633ccb5da08c36ad7d4: Robert Delien (1): Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers are available in the git repository at: git://git.denx.de/u-boot-ti.git master Matt Porter (2): SPL: Add YMODEM over UART load support SPL: Enable YMODEM support on BeagleBone and AM335x EVM Tom Rini (6): .gitignore: Add .su files config.mk: Make cc-option create a file under include/generated config.mk: Check for -fstack-usage support spl.c: Use __noreturn decorator README: document more SPL config options SPL: Add README.omap3 .gitignore | 1 + Makefile | 2 +- README | 69 +++++++++++++++++++++---- arch/arm/cpu/armv7/omap-common/Makefile | 3 + arch/arm/cpu/armv7/omap-common/spl.c | 10 +++- arch/arm/cpu/armv7/omap-common/spl_ymodem.c | 76 +++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 3 + common/Makefile | 3 + config.mk | 11 +++-- doc/SPL/README.omap3 | 74 ++++++++++++++++++++++++++ include/configs/am335x_evm.h | 1 + lib/Makefile | 3 + 12 files changed, 238 insertions(+), 18 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/spl_ymodem.c create mode 100644 doc/SPL/README.omap3 With the documentation / related changes, Wolfgang said on IRC he was OK for now with the additional SPL bits going on. -- Tom

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[U-Boot] [PATCH 0/4] USB: Add support for designware UDC
by Amit Virdi 07 Mar '12

07 Mar '12

Support for designware USB device controller (UDC) exists in the u-boot for SPEAr platform. This patchset makes the driver more generic so that it can be used across multiple platforms. Shiraz Hashim (1): USB:gadget:designware Fix memory nonalignment issue Vipin KUMAR (3): USB:gadget:designware USB device controller (UDC) implementation USB:gadget:designware Device controller bugfixes USB:gadget:designware Support high speed drivers/serial/usbtty.h | 4 +- drivers/usb/gadget/Makefile | 2 +- drivers/usb/gadget/{spr_udc.c => designware_udc.c} | 138 ++++++++++++-------- include/configs/spear-common.h | 4 +- include/usb/{spr_udc.h => designware_udc.h} | 9 +- 5 files changed, 98 insertions(+), 59 deletions(-) rename drivers/usb/gadget/{spr_udc.c => designware_udc.c} (89%) rename include/usb/{spr_udc.h => designware_udc.h} (97%) -- 1.7.2.2

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