March 2012 - U-Boot

[U-Boot] [PATCH v2] CPCI750: Add CPCI-HD/2 support
by Reinhard Arlt 18 Mar '12

18 Mar '12

From: Reinhard Arlt <reinhard.arlt(a)esd.eu> This patch adds support for the esd CPCI-HD/2 board to u-boot for CPCI-CPU/750. As the primary devices on the CPCI-HD/2 board are connected to device 1 and 3, the device must be swaped. Signed-off-by: Reinhard Arlt <reinhard.arlt(a)esd.eu> -- diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index a3bd1b7..aa001df 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -31,6 +31,18 @@ #include <pci.h> extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; +int cpci_hd_type; + +int ata_device(int dev) +{ + int retval; + + retval = (dev & 1) << 4; + if (cpci_hd_type == 2) + retval ^= 1 << 4; + return retval; +} + int ide_preinit (void) { @@ -39,14 +51,21 @@ int ide_preinit (void) int l; status = 1; + cpci_hd_type = 0; if (CPCI750_SLAVE_TEST != 0) return status; for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { ide_bus_offset[l] = -ATA_STATUS; } devbusfn = pci_find_device (0x1103, 0x0004, 0); - if (devbusfn == -1) + if (devbusfn != -1) { + cpci_hd_type = 1; + } else { devbusfn = pci_find_device (0x1095, 0x3114, 0); + if (devbusfn != -1) { + cpci_hd_type = 2; + } + } if (devbusfn != -1) { ulong *ide_bus_offset_ptr; diff --git a/include/ata.h b/include/ata.h index b51475d..3b2d737 100644 --- a/include/ata.h +++ b/include/ata.h @@ -82,7 +82,9 @@ /* * Device / Head Register Bits */ +#ifndef ATA_DEVICE #define ATA_DEVICE(x) ((x & 1)<<4) +#endif /* ATA_DEVICE */ #define ATA_LBA 0xE0 /* diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index d735e61..a6af86c 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -187,6 +187,8 @@ #define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */ +#define CONFIG_PRAM 0 + #define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ @@ -241,11 +243,6 @@ #define CONFIG_SYS_TCLK 133000000 -/*#define CONFIG_SYS_750FX_HID0 0x8000c084*/ -#define CONFIG_SYS_750FX_HID0 0x80008484 -#define CONFIG_SYS_750FX_HID1 0x54800000 -#define CONFIG_SYS_750FX_HID2 0x00000000 - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) @@ -457,7 +454,11 @@ #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ - +#ifndef __ASSEMBLY__ +int ata_device(int dev); +#endif +#define ATA_DEVICE(dev) ata_device(dev) +#define CONFIG_ATAPI 1 /*---------------------------------------------------------------------- * Initial BAT mappings @@ -497,8 +498,8 @@ * IBAT4 and DBAT4 * FIXME: ingo disable BATs for Linux Kernel */ -#undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */ -/*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */ +/* #undef SETUP_HIGH_BATS_FX750 */ /* don't initialize BATS 4-7 */ +#define SETUP_HIGH_BATS_FX750 /* initialize BATS 4-7 */ #ifdef SETUP_HIGH_BATS_FX750 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) @@ -622,4 +623,6 @@ #define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) #define CONFIG_SYS_PLD_VER 0xf0e00000 +#define CONFIG_OF_LIBFDT 1 + #endif /* __CONFIG_H */

2 1

[U-Boot] [PATCH v3] add new board nas62x0
by Luka Perkov 18 Mar '12

18 Mar '12

Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220. Only difference between boards is number of SATA ports. Signed-off-by: Luka Perkov <uboot(a)lukaperkov.net> Signed-off-by: Gerald Kerma <dreagle(a)doukki.net> --- Changes from version v2: * use defined() in macros for board selection for robustness MAINTAINERS | 4 + board/Marvell/ib62x0/Makefile | 51 +++++++++++ board/Marvell/ib62x0/ib62x0.c | 114 ++++++++++++++++++++++++ board/Marvell/ib62x0/ib62x0.h | 41 +++++++++ board/Marvell/ib62x0/kwbimage.cfg | 167 +++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/ib62x0.h | 176 +++++++++++++++++++++++++++++++++++++ 7 files changed, 555 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46f63a0..11d023e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -782,6 +782,10 @@ Linus Walleij <linus.walleij(a)linaro.org> integratorap various integratorcp various +Luka Perkov <uboot(a)lukaperkov.net> + + ib62x0 ARM926EJS + Dave Peverley <dpeverley(a)mpc-data.co.uk> omap730p2 ARM926EJS diff --git a/board/Marvell/ib62x0/Makefile b/board/Marvell/ib62x0/Makefile new file mode 100644 index 0000000..3d82f27 --- /dev/null +++ b/board/Marvell/ib62x0/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ib62x0.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/ib62x0/ib62x0.c b/board/Marvell/ib62x0/ib62x0.c new file mode 100644 index 0000000..2b7762a --- /dev/null +++ b/board/Marvell/ib62x0/ib62x0.c @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2011 Gérald Kerma <dreagle(a)doukki.net> + * + * Written-by: Gérald Kerma <dreagle(a)doukki.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "ib62x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_UART0_RTS, + MPP9_UART0_CTS, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, /* Power LED red */ + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, /* Power LED green */ + MPP26_GPIO, + MPP27_GPIO, /* USB transfer LED */ + MPP28_GPIO, /* Reset button */ + MPP29_TSMP9, /* USB Copy button */ + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_NAS6210; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/Marvell/ib62x0/ib62x0.h b/board/Marvell/ib62x0/ib62x0.h new file mode 100644 index 0000000..b26a257 --- /dev/null +++ b/board/Marvell/ib62x0/ib62x0.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2011 Gérald Kerma <dreagle(a)doukki.net> + * + * Written-by: Gérald Kerma <dreagle(a)doukki.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __IB62x0_H +#define __IB62x0_H + +#define IB62x0_OE_LOW (~(0)) +#define IB62x0_OE_HIGH (~(0)) +#define IB62x0_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ +#define IB62x0_OE_VAL_HIGH (1 << 17) /* LED pin high */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __IB62x0_H */ diff --git a/board/Marvell/ib62x0/kwbimage.cfg b/board/Marvell/ib62x0/kwbimage.cfg new file mode 100644 index 0000000..ffa3c18 --- /dev/null +++ b/board/Marvell/ib62x0/kwbimage.cfg @@ -0,0 +1,167 @@ +# +# Copyright (C) 2011 Gérald Kerma <dreagle(a)doukki.net> +# +# Written-by: Gérald Kerma <dreagle(a)doukki.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # change from nand to uart if building UART image +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000CC # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 1, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 0, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 28cc345..a4e8852 100644 --- a/boards.cfg +++ b/boards.cfg @@ -147,6 +147,8 @@ netspace_max_v2 arm arm926ejs netspace_v2 LaCie netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2 dreamplug arm arm926ejs - Marvell kirkwood guruplug arm arm926ejs - Marvell kirkwood +ib_nas6210 arm arm926ejs ib62x0 Marvell kirkwood ib62x0:BOARD_IS_IB_NAS6210 +ib_nas6220 arm arm926ejs ib62x0 Marvell kirkwood ib62x0:BOARD_IS_IB_NAS6220 mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE openrd_client arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_CLIENT diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h new file mode 100644 index 0000000..1609dd6 --- /dev/null +++ b/include/configs/ib62x0.h @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2011-2012 + * Gérald Kerma <dreagle(a)doukki.net> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_IB62x0_H +#define _CONFIG_IB62x0_H + +/* + * Version number information + */ +#if defined(CONFIG_BOARD_IS_IB_NAS6210) +# define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS6210" +#elif defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS6220" +#else +# error Unknown RaidSonic ICY BOX board specified +#endif + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_MACH_NAS6210 /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Other required minimal configurations + */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT +#if defined(CONFIG_BOARD_IS_IB_NAS6210) +# define CONFIG_SYS_PROMPT "IB-NAS6210 # " +#elif defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_SYS_PROMPT "IB-NAS6220 # " +#else +# error Unknown RaidSonic ICY BOX board specified +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount root; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x1100000 ${initrd}; " \ + "bootm 0x800000 0x1100000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0x80000@0x0(uboot)," \ + "0x20000@0x80000(uboot_env)," \ + "-@0xa0000(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/uImage\0" \ + "initrd=/boot/uInitrd\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:root rootfstype=ubifs\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_MVSATA_IDE_USE_PORT0 +# if defined(CONFIG_BOARD_IS_IB_NAS6210) +# undef CONFIG_SYS_IDE_MAXBUS +# define CONFIG_SYS_IDE_MAXBUS 1 +# undef CONFIG_SYS_IDE_MAXDEVICE +# define CONFIG_SYS_IDE_MAXDEVICE 1 +# elif defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_MVSATA_IDE_USE_PORT1 +# endif +#define CONFIG_SYS_ATA_IDE0_OFFSET KW_SATA_PORT0_OFFSET +# if defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_SYS_ATA_IDE1_OFFSET KW_SATA_PORT1_OFFSET +# endif +#endif /* CONFIG_CMD_IDE */ + +/* + * RTC driver configuration + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + +#endif /* _CONFIG_IB62x0_H */

1 0

[U-Boot] How to specify the TEXT_BASE
by jingchaotian6 18 Mar '12

18 Mar '12

Hi All, I am working on the porting of uboot at freescale MPC8360, now stuck on the address TEXT_BASE. in our board, the address of Nor Flash is 0xfc00_0000-0xffff_ffff, the high 1MB from 0xfff0_0000 is used for boot rom. could you instruct me how to specify the TEXT_BASE? is the same to the 0xfc00_0000 ? in addition, the region of SDRAM is 0x0000_0000 to 0x0fff_ffff. Besd regards, -Peter

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[U-Boot] pull request for u-boot-avr32
by Andreas Bießmann 17 Mar '12

17 Mar '12

The following changes since commit 6751b05f855bbe56005d5b88d4eb58bcd52170d2: Revert "post/Makefile: Only build FP post tests if enabled via CONFIG_SYS_POST_FPU" (2012-03-12 15:00:23 +0100) are available in the git repository at: git://git.denx.de/u-boot-avr32.git master for you to fetch changes up to a7a564c55c3b53e5af091b82070ca1f67cba70f7: atmel_mci.h: remove outdated register macros (2012-03-13 14:29:14 +0100) ---------------------------------------------------------------- Andreas Bießmann (2): doc/git-mailrc: add <me> to avr32 alias atmel_mci.h: remove outdated register macros Sven Schnelle (2): ATMEL: use generic mmc framework ATMEL: remove old atmel_mci driver arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 2 +- arch/avr32/lib/board.c | 15 + doc/README.atmel_mci | 2 +- doc/git-mailrc | 2 +- drivers/mmc/Makefile | 1 - drivers/mmc/atmel_mci.c | 533 --------------------- {drivers/mmc => include}/atmel_mci.h | 44 +-- include/configs/atngw100.h | 4 +- include/configs/atstk1002.h | 4 +- include/configs/atstk1003.h | 6 +- include/configs/atstk1004.h | 6 +- include/configs/atstk1006.h | 4 +- include/configs/favr-32-ezkit.h | 4 +- include/configs/hammerhead.h | 4 +- include/configs/mimc200.h | 4 +- include/mmc.h | 1 - 16 files changed, 49 insertions(+), 587 deletions(-) delete mode 100644 drivers/mmc/atmel_mci.c rename {drivers/mmc => include}/atmel_mci.h (83%)

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[U-Boot] Pull request u-boot-blackfin.git (sandbox branch)
by Mike Frysinger 17 Mar '12

17 Mar '12

The following changes since commit e37ae40e9dec9af417c19de72f76becebf160730: image: Support FDTs already loaded at their load address (2012-03-06 22:18:48 +0100) are available in the git repository at: git://www.denx.de/git/u-boot-blackfin.git sandbox The bulk of these were posted initially inside the merge window while the rest fix up build warnings/failures that have cropped up since. Mike Frysinger (6): sandbox: add ifdef protection to os.h sandbox: add lseek helper sandbox: add get_{tbclk,ticks} sandbox: u-boot.lds: tweak style sandbox: disable fortification sandbox: mark os_exit as noreturn Simon Glass (10): sandbox: sort header files in os.c sandbox: add required header to os.c sandbox: fdt: add support for CONFIG_OF_CONTROL sandbox: config: enable fdt and snprintf() options sandbox: add flags for open() call sandbox: gpio: add basic driver for simulating GPIOs sandbox: enable GPIO driver sandbox: add concept of sandbox state sandbox: allow processing before main loop sandbox: add getopt support arch/sandbox/config.mk | 2 +- arch/sandbox/cpu/Makefile | 2 +- arch/sandbox/cpu/os.c | 144 +++++++++++++++++++- arch/sandbox/cpu/start.c | 102 ++++++++++++++- arch/sandbox/cpu/state.c | 51 +++++++ arch/sandbox/cpu/u-boot.lds | 14 ++- arch/sandbox/include/asm/getopt.h | 71 ++++++++++ arch/sandbox/include/asm/global_data.h | 1 + arch/sandbox/include/asm/gpio.h | 81 +++++++++++ arch/sandbox/include/asm/sections.h | 22 +++ arch/sandbox/include/asm/state.h | 62 +++++++++ arch/sandbox/include/asm/u-boot-sandbox.h | 4 + arch/sandbox/lib/board.c | 11 ++ board/sandbox/sandbox/sandbox.c | 10 ++ drivers/gpio/Makefile | 1 + drivers/gpio/sandbox.c | 209 +++++++++++++++++++++++++++++ include/configs/sandbox.h | 10 ++ include/os.h | 51 ++++++- 18 files changed, 828 insertions(+), 20 deletions(-) create mode 100644 arch/sandbox/cpu/state.c create mode 100644 arch/sandbox/include/asm/getopt.h create mode 100644 arch/sandbox/include/asm/gpio.h create mode 100644 arch/sandbox/include/asm/sections.h create mode 100644 arch/sandbox/include/asm/state.h create mode 100644 drivers/gpio/sandbox.c

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[U-Boot] Please pull u-boot-sh/master
by Nobuhiro Iwamatsu 17 Mar '12

17 Mar '12

Dear Wolfgang Denk. Please pull u-boot-sh/master. The following changes since commit e37ae40e9dec9af417c19de72f76becebf160730: image: Support FDTs already loaded at their load address (2012-03-06 22:18:48 +0100) are available in the git repository at: git://git.denx.de/u-boot-sh.git master for you to fetch changes up to 78df8c68cd42c9db3601b331018b82e9627d08ce: sh: timer: Remove unnecessary variable 'ticks' (2012-03-08 10:26:38 +0900) ---------------------------------------------------------------- Nobuhiro Iwamatsu (6): sh: sh_eth: Add support SH7724 sh: ecovec: Add support PHY of SMSC net: sh_eth: Remove SH_ETH_PHY_DELAY net: sh_eth: Collect up EDMR_INIT_CNT to TIMEOUT_CNT net: sh_eth: Remove unnecessary return sh: timer: Remove unnecessary variable 'ticks' Phil Edworthy (1): sh: Fix sh7264 clock speed and related serial setting arch/sh/lib/time.c | 7 +----- drivers/net/sh_eth.c | 52 ++++++++++++++++++++++--------------------- drivers/net/sh_eth.h | 41 +++++++++++++++++++++++++++++++--- drivers/serial/serial_sh.h | 2 - include/configs/ecovec.h | 1 + include/configs/rsk7264.h | 2 +- 6 files changed, 67 insertions(+), 38 deletions(-) Best regards, Nobuhiro -- Nobuhiro Iwamatsu iwamatsu at {nigauri.org / debian.org} GPG ID: 40AD1FA6

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[U-Boot] [PATCH] mxsboot: fix tool name in usage message
by Otavio Salvador 17 Mar '12

17 Mar '12

Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- tools/mxsboot.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 8246831..6c05aa4 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -453,7 +453,7 @@ static int mx28_nand_write_firmware(struct mx28_nand_fcb *fcb, int infd, void usage(void) { printf( - "Usage: mx28image [ops] <type> <infile> <outfile>\n" + "Usage: mxsboot [ops] <type> <infile> <outfile>\n" "Augment BootStream file with a proper header for i.MX28 boot\n" "\n" " <type> type of image:\n" -- 1.7.9.1

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[U-Boot] A question about mpc85xx tlb1
by 徐阳 16 Mar '12

16 Mar '12

Dear list, In u-boot-2011.12/arch/powerpc/cpu/mpc85xx/cpu_init_early.c , line 151 void cpu_init_early_f(void) { ... invalidate_tlb(1); ... } The tlb1 has beening invalidated int the line 151, but I don't know when it was validated again. It makes me feel very confused, please help me. Best regards, Xu Yang

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[U-Boot] [PATCH] sdrc.c: Fix typo in do_sdrc_init() for SPL
by Tom Rini 16 Mar '12

16 Mar '12

We need to setup CS0 and CS1 not CS0 and CS0 again. Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/armv7/omap3/sdrc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 91f42c0..f6d9b97 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -180,7 +180,7 @@ void do_sdrc_init(u32 cs, u32 early) write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, rfr_ctrl, mr); make_cs1_contiguous(); - write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb, + write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb, rfr_ctrl, mr); #endif -- 1.7.0.4

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[U-Boot] [PATCH] i.MX28: Drop __naked function from spl_mem_init
by Marek Vasut 16 Mar '12

16 Mar '12

Instead of compiling the function and using the result as a constant, simply use the constant. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 10 +++------- 1 files changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 43a90ff..911bbef 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -173,22 +173,18 @@ void mx28_mem_setup_vddd(void) &power_regs->hw_power_vdddctrl); } -void data_abort_memdetect_handler(void) __attribute__((naked)); -void data_abort_memdetect_handler(void) -{ - asm volatile("subs pc, r14, #4"); -} - void mx28_mem_get_size(void) { struct mx28_digctl_regs *digctl_regs = (struct mx28_digctl_regs *)MXS_DIGCTL_BASE; uint32_t sz, da; uint32_t *vt = (uint32_t *)0x20; + /* The following is "subs pc, r14, #4", used as return from DABT. */ + const uint32_t data_abort_memdetect_handler = 0xe25ef004; /* Replace the DABT handler. */ da = vt[4]; - vt[4] = (uint32_t)&data_abort_memdetect_handler; + vt[4] = data_abort_memdetect_handler; sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); writel(sz, &digctl_regs->hw_digctl_scratch0); -- 1.7.9

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