March 2012 - U-Boot

[U-Boot] [PATCH] mmc: fsl_esdhc: Add workaround for auto-clock gate errata ENGcm03648
by Dirk Behme 26 Mar '12

26 Mar '12

This patch imports three patches from the Freescale U-Boot with the following commit messages: ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648 http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/… The errata, not applicable to USDHC, causes ESDHC to shut off clock to the card when auto-clock gating is enabled for commands with busy signalling and no data phase. The card might require the clock to exit the busy state, so the workaround is to disable the auto-clock gate bits in SYSCTL register for such commands. The workaround also entails polling on DAT0 bit in the PRSSTAT register to learn when busy state is complete. Auto-clock gating is re-enabled at the end of busy state. ENGR00156670-1 ESDHC/USDHC: Remove delay before each cmd and some bug fixes http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/… Removed delay of 10 ms before each command. There should not be a need to have this delay after the ENGR00156405 patch that polls until card is not busy anymore before proceeding to next cmd. ENGR00161852: remove u-boot build warnings for mx6q http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/… Remove u-boot build warnings for mx6q. SYSCTL_RSTA was defined twice. Remove one definition. Signed-off-by: Dirk Behme <dirk.behme(a)de.bosch.com> CC: Andy Fleming <afleming(a)freescale.com> CC: Fabio Estevam <fabio.estevam(a)freescale.com> --- drivers/mmc/fsl_esdhc.c | 61 ++++++++++++++++++++++++++++++++++++++++------ include/fsl_esdhc.h | 4 ++- 2 files changed, 56 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 30db030..694d6fd 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -259,6 +259,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { uint xfertyp; uint irqstat; + uint sysctl_restore = 0; struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; @@ -279,13 +280,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA) ; - /* Wait at least 8 SD clock cycles before the next command */ - /* - * Note: This is way more than 8 cycles, but 1ms seems to - * resolve timing issues with some cards - */ - udelay(1000); - /* Set up for a data transfer if we have one */ if (data) { int err; @@ -298,6 +292,14 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Figure out the transfer arguments */ xfertyp = esdhc_xfertyp(cmd, data); + /* ESDHC errata ENGcm03648: Turn off auto-clock gate for commands + * with busy signaling and no data + */ + if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { + sysctl_restore = esdhc_read32(&regs->sysctl); + esdhc_write32(&regs->sysctl, sysctl_restore | 0xF); + } + /* Send the command */ esdhc_write32(&regs->cmdarg, cmd->cmdarg); #if defined(CONFIG_FSL_USDHC) @@ -307,19 +309,62 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #else esdhc_write32(&regs->xfertyp, xfertyp); #endif + + /* Mask all irqs */ + esdhc_write32(&regs->irqsigen, 0); + /* Wait for the command to complete */ - while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC)) + while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) ; irqstat = esdhc_read32(&regs->irqstat); esdhc_write32(&regs->irqstat, irqstat); + /* Reset CMD and DATA portions on error */ + if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { + esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) | + SYSCTL_RSTC); + while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC) + ; + + if (data) { + esdhc_write32(&regs->sysctl, + esdhc_read32(&regs->sysctl) | + SYSCTL_RSTD); + while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD)) + ; + } + + /* Restore auto-clock gate if error */ + if (!data && (cmd->resp_type & MMC_RSP_BUSY)) + esdhc_write32(&regs->sysctl, sysctl_restore); + } + if (irqstat & CMD_ERR) return COMM_ERR; if (irqstat & IRQSTAT_CTOE) return TIMEOUT; + /* Workaround for ESDHC errata ENGcm03648 */ + if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { + int timeout = 2500; + + /* Poll on DATA0 line for cmd with busy signal for 250 ms */ + while (timeout > 0 && !(esdhc_read32(&regs->prsstat) & + PRSSTAT_DAT0)) { + udelay(100); + timeout--; + } + + esdhc_write32(&regs->sysctl, sysctl_restore); + + if (timeout <= 0) { + printf("Timeout waiting for DAT0 to go high!\n"); + return TIMEOUT; + } + } + /* Copy the response to the response buffer */ if (cmd->resp_type & MMC_RSP_136) { u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 8418bf7..0e26558 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -34,12 +34,13 @@ #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 #define SYSCTL_CLOCK_MASK 0x0000fff0 -#define SYSCTL_RSTA 0x01000000 #define SYSCTL_CKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 #define SYSCTL_RSTA 0x01000000 +#define SYSCTL_RSTC 0x02000000 +#define SYSCTL_RSTD 0x04000000 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -85,6 +86,7 @@ #define IRQSTATEN_CC (0x00000001) #define PRSSTAT 0x0002e024 +#define PRSSTAT_DAT0 (0x01000000) #define PRSSTAT_CLSL (0x00800000) #define PRSSTAT_WPSPL (0x00080000) #define PRSSTAT_CDPL (0x00040000) -- 1.7.0.4

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[U-Boot] [PATCH] MAKEALL: display SPL size if present
by Scott Wood 26 Mar '12

26 Mar '12

This makes it easier to detect changes in the SPL portion, as can currently be done for the main U-Boot image. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- MAKEALL | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/MAKEALL b/MAKEALL index f735af6..395e982 100755 --- a/MAKEALL +++ b/MAKEALL @@ -508,6 +508,11 @@ build_target() { ${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \ | tee -a ${LOG_DIR}/$target.MAKELOG + + if [ -e ${BUILD_DIR}/spl/u-boot-spl ]; then + ${CROSS_COMPILE}size ${BUILD_DIR}/spl/u-boot-spl \ + | tee -a ${LOG_DIR}/$target.MAKELOG + fi } build_targets() { for t in "$@" ; do -- 1.7.7.rc3.4.g8d714

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[U-Boot] [PATCH resend] ARMV7/Vexpress: add missing get_ticks() and get_tbclk()
by walimis 26 Mar '12

26 Mar '12

From: Liming Wang <walimisdev(a)gmail.com> commit f31a911fe (arm, post: add missing post_time_ms for arm) enables get_ticks and get_tbclk for all arm based boards, arm/vexpress also needs these functions to work. Signed-off-by: Liming Wang <walimisdev(a)gmail.com> --- board/armltd/vexpress/ca9x4_ct_vxp.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c index da6f14d..0b36d12 100644 --- a/board/armltd/vexpress/ca9x4_ct_vxp.c +++ b/board/armltd/vexpress/ca9x4_ct_vxp.c @@ -226,3 +226,13 @@ void lowlevel_init(void) ulong get_board_rev(void){ return readl((u32 *)SYS_ID); } + +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +ulong get_tbclk (void) +{ + return (ulong)CONFIG_SYS_HZ; +} -- 1.7.0.4

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[U-Boot] [PATCH] Avoid using GNU basename
by Keith Mok 26 Mar '12

26 Mar '12

There is no GNU basename support in MacOS. Use generic POSIX basename defined in libgen.h instead. Signed-off-by: Keith Mok <ek9852(a)gmail.com> --- tools/mkenvimage.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index f781731..8b49723 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -25,9 +25,6 @@ * MA 02111-1307 USA */ -/* We want the GNU version of basename() */ -#define _GNU_SOURCE - #include <errno.h> #include <fcntl.h> #include <stdio.h> @@ -35,6 +32,7 @@ #include <string.h> #include <unistd.h> #include <compiler.h> +#include <libgen.h> #include <sys/types.h> #include <sys/stat.h> @@ -85,8 +83,10 @@ int main(int argc, char **argv) int fp, ep; const char *prg; + char *prog_pathname; - prg = basename(argv[0]); + prog_pathname = strdup(argv[0]); + prg = basename(prog_pathname); /* Turn off getopt()'s internal error message */ opterr = 0; -- 1.7.7.4

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Re: [U-Boot] [PATCH V4] net: fec_mxc: allow use with cache enabled
by Eric Nelson 26 Mar '12

26 Mar '12

Hi Marek, Have you had a chance to review this V4 patch for the fec_mxc driver? http://lists.denx.de/pipermail/u-boot/2012-March/120205.html Note that Stefano pointed out yesterday that PPC doesn't properly implement "invalidate_dcache_range". http://lists.denx.de/pipermail/u-boot/2012-March/120918.html I believe you mentioned previously that the fec_mxc driver was compatible with certain PPC SOCs, so this might temporarily block any such transition. Please advise, Eric

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[U-Boot] [PATCH] Enable high speed support for USB device framework and usbtty
by Amit Virdi 26 Mar '12

26 Mar '12

From: Vipin KUMAR <vipin.kumar(a)st.com> This patch adds the support for high speed in usb device framework and usbtty driver. This feature has been kept within a macro CONFIG_USBD_HS, so the board configuration files have to define this macro to enable high speed support. Along with that specific peripheral drivers also need to define a function to let the framework know that the enumeration has happened at high speed. This function prototype is "int is_usbd_high_speed(void)" Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> Signed-off-by: Amit Virdi <amit.virdi(a)st.com> --- README | 8 +++++++ drivers/serial/usbtty.c | 50 ++++++++++++++++++++++++++++++++++++++++++++- drivers/serial/usbtty.h | 4 +++ drivers/usb/gadget/core.c | 14 ++++++++++++ drivers/usb/gadget/ep0.c | 24 ++++++++++++++++++--- include/usbdescriptors.h | 15 +++++++++++++ include/usbdevice.h | 24 ++++++++++++++++++++- 7 files changed, 133 insertions(+), 6 deletions(-) diff --git a/README b/README index eba6378..d54bb68 100644 --- a/README +++ b/README @@ -1165,6 +1165,14 @@ The following options need to be configured: Define this to have a tty type of device available to talk to the UDC device + CONFIG_USBD_HS + Define this to enable the high speed support for usb + device and usbtty. If this feature is enabled, a routine + int is_usbd_high_speed(void) + also needs to be defined by the driver to dynamically poll + whether the enumeration has succeded at high speed or full + speed. + CONFIG_SYS_CONSOLE_IS_IN_ENV Define this if you want stdin, stdout &/or stderr to be set to usbtty. diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index 550bc58..0374c7d 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -133,6 +133,19 @@ static struct usb_device_descriptor device_descriptor = { }; +#if defined(CONFIG_USBD_HS) +static struct usb_qualifier_descriptor qualifier_descriptor = { + .bLength = sizeof(struct usb_qualifier_descriptor), + .bDescriptorType = USB_DT_QUAL, + .bcdUSB = cpu_to_le16(USB_BCD_VERSION), + .bDeviceClass = COMMUNICATIONS_DEVICE_CLASS, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = EP0_MAX_PACKET_SIZE, + .bNumConfigurations = NUM_CONFIGS +}; +#endif + /* * Static CDC ACM specific descriptors */ @@ -638,6 +651,9 @@ static void usbtty_init_instances (void) memset (device_instance, 0, sizeof (struct usb_device_instance)); device_instance->device_state = STATE_INIT; device_instance->device_descriptor = &device_descriptor; +#if defined(CONFIG_USBD_HS) + device_instance->qualifier_descriptor = &qualifier_descriptor; +#endif device_instance->event = usbtty_event_handler; device_instance->cdc_recv_setup = usbtty_cdc_setup; device_instance->bus = bus_instance; @@ -751,6 +767,10 @@ static void usbtty_init_terminal_type(short type) device_descriptor.idProduct = cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM); +#if defined(CONFIG_USBD_HS) + qualifier_descriptor.bDeviceClass = + COMMUNICATIONS_DEVICE_CLASS; +#endif /* Assign endpoint indices */ tx_endpoint = ACM_TX_ENDPOINT; rx_endpoint = ACM_RX_ENDPOINT; @@ -779,7 +799,9 @@ static void usbtty_init_terminal_type(short type) device_descriptor.bDeviceClass = 0xFF; device_descriptor.idProduct = cpu_to_le16(CONFIG_USBD_PRODUCTID_GSERIAL); - +#if defined(CONFIG_USBD_HS) + qualifier_descriptor.bDeviceClass = 0xFF; +#endif /* Assign endpoint indices */ tx_endpoint = GSERIAL_TX_ENDPOINT; rx_endpoint = GSERIAL_RX_ENDPOINT; @@ -932,6 +954,9 @@ static int usbtty_configured (void) static void usbtty_event_handler (struct usb_device_instance *device, usb_device_event_t event, int data) { +#if defined(CONFIG_USBD_HS) + int i; +#endif switch (event) { case DEVICE_RESET: case DEVICE_BUS_INACTIVE: @@ -942,6 +967,29 @@ static void usbtty_event_handler (struct usb_device_instance *device, break; case DEVICE_ADDRESS_ASSIGNED: +#if defined(CONFIG_USBD_HS) + /* + * is_usbd_high_speed routine needs to be defined by + * specific gadget driver + * It returns TRUE if device enumerates at High speed + * Retuns FALSE otherwise + */ + for (i = 1; i <= NUM_ENDPOINTS; i++) { + if (((ep_descriptor_ptrs[i - 1]->bmAttributes & + USB_ENDPOINT_XFERTYPE_MASK) == + USB_ENDPOINT_XFER_BULK) + && is_usbd_high_speed()) { + + ep_descriptor_ptrs[i - 1]->wMaxPacketSize = + CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE; + } + + endpoint_instance[i].tx_packetSize = + ep_descriptor_ptrs[i - 1]->wMaxPacketSize; + endpoint_instance[i].rcv_packetSize = + ep_descriptor_ptrs[i - 1]->wMaxPacketSize; + } +#endif usbtty_init_endpoints (); default: diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 6731c38..bd3bcbc 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -72,6 +72,10 @@ #define CONFIG_USBD_SERIAL_INT_PKTSIZE UDC_INT_PACKET_SIZE #define CONFIG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_PACKET_SIZE +#if defined(CONFIG_USBD_HS) +#define CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE UDC_BULK_HS_PACKET_SIZE +#endif + #define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS #define USBTTY_BCD_DEVICE 0x00 diff --git a/drivers/usb/gadget/core.c b/drivers/usb/gadget/core.c index 4f2ebab..b2212b4 100644 --- a/drivers/usb/gadget/core.c +++ b/drivers/usb/gadget/core.c @@ -212,6 +212,20 @@ struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_i return (device->device_descriptor); } +#if defined(CONFIG_USBD_HS) +/** + * usbd_device_qualifier_descriptor + * @device: which device + * @port: which port + * + * Return the specified qualifier descriptor for the specified device. + */ +struct usb_qualifier_descriptor *usbd_device_qualifier_descriptor( + struct usb_device_instance *device, int port) +{ + return device->qualifier_descriptor; +} +#endif /** * usbd_device_configuration_descriptor diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c index 22499d3..ba8f906 100644 --- a/drivers/usb/gadget/ep0.c +++ b/drivers/usb/gadget/ep0.c @@ -338,12 +338,28 @@ static int ep0_get_descriptor (struct usb_device_instance *device, } break; case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: +#if defined(CONFIG_USBD_HS) { - /* If a USB device supports both a full speed and low speed operation - * we must send a Device_Qualifier descriptor here - */ - return -1; + struct usb_qualifier_descriptor *qualifier_descriptor; + + qualifier_descriptor = usbd_device_qualifier_descriptor + (device, port); + if (!qualifier_descriptor) + return -1; + + /* copy descriptor for this device */ + copy_config(urb, qualifier_descriptor, + sizeof(struct usb_qualifier_descriptor), + max); + } + dbg_ep0(3, "copied qualifier descriptor, actual_length: 0x%x", + urb->actual_length); +#else + return -1; +#endif + break; + default: return -1; } diff --git a/include/usbdescriptors.h b/include/usbdescriptors.h index 2dec3b9..de1069f 100644 --- a/include/usbdescriptors.h +++ b/include/usbdescriptors.h @@ -241,6 +241,21 @@ struct usb_device_descriptor { u8 bNumConfigurations; } __attribute__ ((packed)); +#if defined(CONFIG_USBD_HS) +struct usb_qualifier_descriptor { + u8 bLength; + u8 bDescriptorType; + + u16 bcdUSB; + u8 bDeviceClass; + u8 bDeviceSubClass; + u8 bDeviceProtocol; + u8 bMaxPacketSize0; + u8 bNumConfigurations; + u8 breserved; +} __attribute__ ((packed)); +#endif + struct usb_string_descriptor { u8 bLength; u8 bDescriptorType; /* 0x03 */ diff --git a/include/usbdevice.h b/include/usbdevice.h index 9eb8849..e3eb748 100644 --- a/include/usbdevice.h +++ b/include/usbdevice.h @@ -210,6 +210,10 @@ struct usb_bus_instance; #define USB_DT_INTERFACE 0x04 #define USB_DT_ENDPOINT 0x05 +#if defined(CONFIG_USBD_HS) +#define USB_DT_QUAL 0x06 +#endif + #define USB_DT_HID (USB_TYPE_CLASS | 0x01) #define USB_DT_REPORT (USB_TYPE_CLASS | 0x02) #define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) @@ -291,7 +295,11 @@ struct usb_bus_instance; * USB Spec Release number */ +#if defined(CONFIG_USBD_HS) +#define USB_BCD_VERSION 0x0200 +#else #define USB_BCD_VERSION 0x0110 +#endif /* @@ -567,6 +575,9 @@ struct usb_device_instance { /* generic */ char *name; struct usb_device_descriptor *device_descriptor; /* per device descriptor */ +#if defined(CONFIG_USBD_HS) + struct usb_qualifier_descriptor *qualifier_descriptor; +#endif void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data); @@ -659,8 +670,19 @@ struct usb_class_report_descriptor *usbd_device_class_report_descriptor_index( s struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *, int, int, int, int, int); int usbd_device_endpoint_transfersize (struct usb_device_instance *, int, int, int, int, int); struct usb_string_descriptor *usbd_get_string (u8); -struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *, int); +struct usb_device_descriptor *usbd_device_device_descriptor(struct + usb_device_instance *, int); +#if defined(CONFIG_USBD_HS) +struct usb_qualifier_descriptor *usbd_device_qualifier_descriptor( + struct usb_device_instance *, int); +/* + * is_usbd_high_speed routine needs to be defined by specific gadget driver + * It returns TRUE if device enumerates at High speed + * Retuns FALSE otherwise + */ +int is_usbd_high_speed(void); +#endif int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint); void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad); void usbd_tx_complete (struct usb_endpoint_instance *endpoint); -- 1.7.2.2

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Re: [U-Boot] [PATCH V4 1/2] ext4fs ls load support
by Wolfgang Denk 26 Mar '12

26 Mar '12

Dear UMA SHANKAR, please do not top post / full quote. In message <27542660.71361332746650945.JavaMail.weblogic@epml04> you wrote: > > Currently, Our ext4 implementation is capable of listing and reading (ls and load) ext2 partitions as well. > But, we wanted the ext4 code to be separate from ext2 implementation. This does not make much sense to me. > So, I propose, we can let both these implementations be there in > uboot under different CONFIG Options (as is the case currently). What would be the rationale here? I think more and more people are going to use ext4. It makes no sense to have different commands and different options to support both ext2 (and ext3, to some degree) and ext4 (and ext3?) file systems. And especially, it makes no sense to dusplicate large amounts of code. Please use common code whererver possible. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de "I knew then (in 1970) that a 4-kbyte minicomputer would cost as much as a house. So I reasoned that after college, I'd have to live cheaply in an apartment and put all my money into owning a computer." - Apple co-founder Steve Wozniak, EE Times, June 6, 1988, pg 45

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[U-Boot] [PATCH 4/4][v2] powerpc/85xx:Fix NAND code base to support debugger
by Prabhakar Kushwaha 26 Mar '12

26 Mar '12

Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address. As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to any fetchable valid data Signed-off-by: Radu Lazarescu <radu.lazarescu(a)freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master Changes for v2: - Removed unnecessary CONFIG_E500 - Avoid TLB creation for NAND_SPL Tested on - SoC having E500 Family processor (P1010RDB, BSC9131RDB) - SoC having E500MC Family processor (P4080DS, P3041DS) arch/powerpc/cpu/mpc85xx/start.S | 20 ++++++++++++++------ 1 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 1cfd08a..92d65af 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -182,7 +182,7 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) /* * TLB entry for debuggging in AS1 * Create temporary TLB entry in AS0 to handle debug exception @@ -1437,17 +1437,25 @@ relocate_code: 7: sync /* Wait for all icbi to complete on bus */ isync - /* - * Re-point the IVPR at RAM - */ - mtspr IVPR,r10 - /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ addi r0,r10,in_ram - _start + _START_OFFSET + +#if defined(CONFIG_NAND_SPL) +/* + * As IVPR is going to point RAM address, + * Make sure IVOR15 has valid opcode to support debugger + */ + mtspr IVOR15,r0 +#endif + /* + * Re-point the IVPR at RAM + */ + mtspr IVPR,r10 + mtlr r0 blr /* NEVER RETURNS! */ .globl in_ram -- 1.7.5.4

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[U-Boot] [PATCH 2/4][v2] powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger
by Prabhakar Kushwaha 26 Mar '12

26 Mar '12

Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always. Where MSR = Machine State register Make sure of MSR[DE] bit is set uniformaly across the different execution address space i.e. AS0 and AS1. Signed-off-by: Radu Lazarescu <radu.lazarescu(a)freescale.com> Signed-off-by: Catalin Udma <catalin.udma(a)freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master Changes for v2: - Avoid MSR_DE negation in arch_preboot - Made MSR_DE set code independent of any #define No change, Resending again Tested on - SoC having E500 Family processor (P1010RDB, BSC9131RDB) - SoC having E500MC Family processor (P4080DS, P3041DS) arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/start.S | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2e4a06c..3bcbffa 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -532,7 +532,7 @@ void arch_preboot_os(void) * disabled by the time we get called. */ msr = mfmsr(); - msr &= ~(MSR_ME|MSR_CE|MSR_DE); + msr &= ~(MSR_ME|MSR_CE); mtmsr(msr); setup_ivors(); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 7bfa2d5..597151b 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -82,6 +82,9 @@ .globl _start_e500 _start_e500: +/* Enable debug exception */ + li r1,MSR_DE + mtmsr r1 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) /* ISBC uses L2 as stack. @@ -729,8 +732,8 @@ create_init_ram_area: msync tlbwe - lis r6,MSR_IS|MSR_DS@h - ori r6,r6,MSR_IS|MSR_DS@l + lis r6,MSR_IS|MSR_DS|MSR_DE@h + ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l lis r7,switch_as@h ori r7,r7,switch_as@l -- 1.7.5.4

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[U-Boot] [PATCH 1/4][v3] doc:Add documentation for e500 external debugger support
by Prabhakar Kushwaha 26 Mar '12

26 Mar '12

This describes requirement of e500 and e500v2 processor to support external debugger. It also provide an insight of the configuration switch required and their description. Signed-off-by: Radu Lazarescu <radu.lazarescu(a)freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master Changes for v2: - Recreated README.mpc85xx - Added #define in README Changes for v3: Incorporated Scott's comments - Moved config switch to "85xx CPU options" - Added TLB entry information Tested on - SoC having E500 Family processor (P1010RDB, BSC9131RDB) - SoC having E500MC Family processor (P4080DS, P3041DS) README | 9 +++ doc/README.mpc85xx | 161 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc85xx diff --git a/README b/README index 1f8bd20..37d814b 100644 --- a/README +++ b/README @@ -374,6 +374,15 @@ The following options need to be configured: Defines the string to utilize when trying to match PCIe device tree nodes for the given platform. + CONFIG_SYS_PPC_E500_DEBUG_TLB + + Enables a temporary TLB entry to be used during boot to work + around limitations in e500v1 and e500v2 external debugger + support. This reduces the portions of the boot code where + breakpoints and single stepping do not work. The value of this + symbol should be set to the TLB1 entry to be used for this + purpose. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx new file mode 100644 index 0000000..3942477 --- /dev/null +++ b/doc/README.mpc85xx @@ -0,0 +1,161 @@ +External Debug Support +---------------------- + +Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some +restrictions on external debugging (JTAG). In particular, for the debugger to +be able to receive control after a single step or breakpoint: + - MSR[DE] must be set + - A valid opcode must be fetchable, through the MMU, from the debug + exception vector (IVPR + IVOR15). + +To maximize the time during which this requirement is met, U-Boot sets MSR[DE] +immediately on entry and keeps it set. It also uses a temporary TLB to keep a +mapping to a valid opcode at the debug exception vector, even if we normally +don't support exception vectors being used that early, and that's not the area +where U-Boot currently executes from. + +Note that there may still be some small windows where debugging will not work, +such as in between updating IVPR and IVOR15. + +Config Switches: +---------------- + +Please refer README section "MPC85xx External Debug Support" + +Major Config Switches during various boot Modes +---------------------------------------------- + +NOR boot + !defined(CONFIG_SYS_RAMBOOT) +NOR boot Secure + !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) +RAMBOOT(SD, SPI & NAND boot) + defined(CONFIG_SYS_RAMBOOT) +RAMBOOT Secure (SD, SPI & NAND) + defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) +NAND SPL BOOT + defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL) + + +TLB Entries during u-boot execution +----------------------------------- + +Note: Sequence number is in order of execution + +A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot + + 1) TLB entry to overcome e500 v1/v2 debug restriction + Location : Label "_start_e500" + TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE + Properties : 256K, AS0, I, IPROT + + 2) TLB entry for working in AS1 + Location : Label "create_init_ram_area" + TLB Entry : 15 + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE + Properties : 1M, AS1, I, G,IPROT + + 3) TLB entry for the stack during AS1 + Location : Lable "create_init_ram_area" + TLB Entry : 14 + EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + Properties : 16K, AS1, IPROT + + 4) TLB entry for CCSRBAR during AS1 execution + Location : cpu_init_early_f + TLB Entry : 13 + EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + Properties : 1M, AS1, I, G + + 5) Invalidate unproctected TLB Entries + Location : cpu_init_early_f + Invalidated: 13 + + 6) Create TLB entries as per boards/freescale/<board>/tlb.c + Location : cpu_init_early_f --> init_tlbs() + Properties : ..., AS0, ... + Please note It can overwrites previous TLB Entries. + + 7) Disable TLB Entries of AS1 + Location : cpu_init_f --> disable_tlb() + Disable : 15, 14 + + 8) Update Flash's TLB entry + Location : Board_init_r + TLB entry : Search from TLB entries + EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + Properties : Board specific size, AS0, I, G, IPROT + + +B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot + + 1) TLB entry to overcome e500 v1/v2 debug restriction + Location : Label "_start_e500" + TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB + EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 + Properties : 4M, AS0, I, G,IPROT + + 2) TLB entry for working in AS1 + Location : Label "create_init_ram_area" + TLB Entry : 15 +#if defined(CONFIG_SECURE_BOOT) + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + Properties : 1M, AS1, I, G,IPROT +#else + EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 + Properties : 4M, AS1, I, G,IPROT +#endif + + 3) TLB entry for the stack during AS1 + Location : Lable "create_init_ram_area" + TLB Entry : 14 + EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + Properties : 16K, AS1, IPROT + + 4) TLB entry for CCSRBAR during AS1 execution + Location : cpu_init_early_f + TLB Entry : 13 + EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + Properties : 1M, AS1, I, G + + 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 + Location : cpu_init_early_f + TLB Entry : 9 + EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR + Properties : 1M, AS1, I + + 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr + Location : cpu_init_early_f --> setup_ifc + TLB Entry : Get Flash TLB + EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys + Properties : 4M, AS1, I, G, IPROT + + 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction + Location : cpu_init_early_f --> setup_ifc + TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB + EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys + Properties : 4M, AS0, I, G, IPROT + + 8) Invalidate unproctected TLB Entries + Location : cpu_init_early_f + Invalidated: 13, 9 + + 9) Create TLB entries as per boards/freescale/<board>/tlb.c + Location : cpu_init_early_f --> init_tlbs() + Properties : ..., AS0, ... + Note: It can overwrites previous TLB Entries + + 10) Disable TLB Entries of AS1 + Location : cpu_init_f --> disable_tlb() + Disable : 15, 14 + + 11) Create DDR's TLB entriy + Location : Board_init_f -> init_func_ram -> initdram + TLB entry : Search free TLB entry + + 12) Update Flash's TLB entry + Location : Board_init_r + TLB entry : Search from TLB entries + EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + Properties : Board specific size, AS0, I, G, IPROT -- 1.7.5.4

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