March 2012 - U-Boot

[U-Boot] [PATCH v5] kirkwood: add NAS62x0 board support
by Luka Perkov 27 Mar '12

27 Mar '12

Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220. Only difference between boards is number of SATA ports. More information about the boards can be found here: http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7036 http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7515 Signed-off-by: Luka Perkov <uboot(a)lukaperkov.net> Signed-off-by: Gerald Kerma <dreagle(a)doukki.net> Signed-off-by: Simon Baatz <gmbnomis(a)gmail.com> --- Changes from version v1: * use tools/checkpatch.pl to locate patch errors and fix them * add two entries in boards.cfg, one for each board * fixed CONFIG_RESET_PHY_R * don't define values for macros that enable features only * remove static RAM configuration * fix comments * use only CONFIG_ENV_OFFSET and remove CONFIG_ENV_ADDR * clean coding style * add entry in MAINTAINERS file Changes from version v2: * use defined() in macros for board selection for robustness Changes from version v3: * don't use utf8 for Geralds name * don't mix upper/lower case in kwbimage.cfg * fix prompt Changes from version v4: * fix board Makefile (clean and distclean) * use generic way to handle arch number of the board * fix MAINTAINERS file * move code from Marvell to raidsonic folder * use CONFIG_MACH_TYPE * set only necessary GPIOs * use link instead of address for license * add few links about board being supported for quick reference * add previous change logs * multiple updates to kwbimage.cfg, thank you Simon About kwbimage.cfg - first version was taken from sheevaplug with change only regarding memory. Now it's rewriten so it uses settings like manufacturer. MAINTAINERS | 5 + board/raidsonic/ib62x0/Makefile | 43 +++++++++ board/raidsonic/ib62x0/ib62x0.c | 79 ++++++++++++++++ board/raidsonic/ib62x0/ib62x0.h | 40 ++++++++ board/raidsonic/ib62x0/kwbimage.cfg | 172 +++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/ib62x0.h | 172 +++++++++++++++++++++++++++++++++++ 7 files changed, 513 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 46f63a0..deb093e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -782,6 +782,11 @@ Linus Walleij <linus.walleij(a)linaro.org> integratorap various integratorcp various +Luka Perkov <uboot(a)lukaperkov.net> + + ib6210 ARM926EJS + ib6220 ARM926EJS + Dave Peverley <dpeverley(a)mpc-data.co.uk> omap730p2 ARM926EJS diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile new file mode 100644 index 0000000..d450f8d --- /dev/null +++ b/board/raidsonic/ib62x0/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ib62x0.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c new file mode 100644 index 0000000..65f2c2e --- /dev/null +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma <dreagle(a)doukki.net> + * Luka Perkov <uboot(a)lukaperkov.net> + * Simon Baatz <gmbnomis(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "ib62x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, /* Power LED red */ + MPP24_GPIO, /* Power off device */ + MPP25_GPIO, /* Power LED green */ + MPP27_GPIO, /* USB transfer LED */ + MPP28_GPIO, /* Reset button */ + MPP29_GPIO, /* USB Copy button */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h new file mode 100644 index 0000000..0c30690 --- /dev/null +++ b/board/raidsonic/ib62x0/ib62x0.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma <dreagle(a)doukki.net> + * Simon Baatz <gmbnomis(a)gmail.com> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __IB62x0_H +#define __IB62x0_H + +#define IB62x0_OE_LOW (~(1 << 22 | 1 << 24 | 1 << 25 | 1 << 27)) +#define IB62x0_OE_HIGH (~(0)) +#define IB62x0_OE_VAL_LOW 0 +#define IB62x0_OE_VAL_HIGH 0 + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __IB62x0_H */ diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg new file mode 100644 index 0000000..bc5a355 --- /dev/null +++ b/board/raidsonic/ib62x0/kwbimage.cfg @@ -0,0 +1,172 @@ +# +# Copyright (C) 2011-2012 +# Gerald Kerma <dreagle(a)doukki.net> +# Simon Baatz <gmbnomis(a)gmail.com> +# Luka Perkov <uboot(a)lukaperkov.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # change from nand to uart if building UART image +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xffd01410 0x0000000c # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 1, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 0, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +DATA 0xffd01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 28cc345..fe1c489 100644 --- a/boards.cfg +++ b/boards.cfg @@ -153,6 +153,8 @@ openrd_client arm arm926ejs openrd Marvell openrd_ultimate arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_ULTIMATE rd6281a arm arm926ejs - Marvell kirkwood sheevaplug arm arm926ejs - Marvell kirkwood +ib_nas6210 arm arm926ejs ib62x0 raidsonic kirkwood ib62x0:BOARD_IS_IB_NAS6210 +ib_nas6220 arm arm926ejs ib62x0 raidsonic kirkwood ib62x0:BOARD_IS_IB_NAS6220 dockstar arm arm926ejs - Seagate kirkwood jadecpu arm arm926ejs jadecpu syteco mb86r0x mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h new file mode 100644 index 0000000..2dc698e --- /dev/null +++ b/include/configs/ib62x0.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma <dreagle(a)doukki.net> + * Luka Perkov <uboot(a)lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _CONFIG_IB62x0_H +#define _CONFIG_IB62x0_H + +/* + * Version number information + */ +#if defined(CONFIG_BOARD_IS_IB_NAS6210) +# define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS6210" +#elif defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_IDENT_STRING " RaidSonic ICY BOX IB-NAS6220" +#else +# error Unknown RaidSonic ICY BOX board specified +#endif + +/* + * High level configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Machine type + */ +#define CONFIG_MACH_TYPE MACH_TYPE_NAS6210 + +/* + * Compression configuration + */ +#define CONFIG_BZIP2 +#define CONFIG_LZMA +#define CONFIG_LZO + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include <config_cmd_default.h> +#define CONFIG_CMD_ENV +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#undef CONFIG_SYS_PROMPT +#if defined(CONFIG_BOARD_IS_IB_NAS6210) +# define CONFIG_SYS_PROMPT "IB-NAS6210 => " +#elif defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_SYS_PROMPT "IB-NAS6220 => " +#else +# error Unknown RaidSonic ICY BOX board specified +#endif + +/* + * Environment variables configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ + "ubi part root; " \ + "ubifsmount root; " \ + "ubifsload 0x800000 ${kernel}; " \ + "ubifsload 0x1100000 ${initrd}; " \ + "bootm 0x800000 0x1100000" + +#define CONFIG_MTDPARTS \ + "mtdparts=orion_nand:" \ + "0x80000@0x0(uboot)," \ + "0x20000@0x80000(uboot_env)," \ + "-@0xa0000(root)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=console=ttyS0,115200\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts="CONFIG_MTDPARTS \ + "kernel=/boot/uImage\0" \ + "initrd=/boot/uInitrd\0" \ + "bootargs_root=ubi.mtd=2 root=ubi0:root rootfstype=ubifs\0" + +/* + * Ethernet driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +/* + * SATA driver configuration + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_DOS_PARTITION +#define CONFIG_MVSATA_IDE_USE_PORT0 +# if defined(CONFIG_BOARD_IS_IB_NAS6210) +# undef CONFIG_SYS_IDE_MAXBUS +# define CONFIG_SYS_IDE_MAXBUS 1 +# undef CONFIG_SYS_IDE_MAXDEVICE +# define CONFIG_SYS_IDE_MAXDEVICE 1 +# elif defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_MVSATA_IDE_USE_PORT1 +# endif +#define CONFIG_SYS_ATA_IDE0_OFFSET KW_SATA_PORT0_OFFSET +# if defined(CONFIG_BOARD_IS_IB_NAS6220) +# define CONFIG_SYS_ATA_IDE1_OFFSET KW_SATA_PORT1_OFFSET +# endif +#endif /* CONFIG_CMD_IDE */ + +/* + * RTC driver configuration + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif /* CONFIG_CMD_DATE */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS + +#endif /* _CONFIG_IB62x0_H */

5 7

[U-Boot] [PATCH] cmd_nand: Fix possible uninited max_size variable
by Marek Vasut 27 Mar '12

27 Mar '12

GCC 4.7 error: cmd_nand.c: In function ‘arg_off_size’: cmd_nand.c:216:5: warning: ‘maxsize’ may be used uninitialized in this function [-Wmaybe-uninitialized] Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Scott Wood <scottwood(a)freescale.com> --- common/cmd_nand.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 035a6f6..b015d11 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -191,7 +191,7 @@ static int arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, loff_t *size) { int ret; - loff_t maxsize; + loff_t maxsize = 0; if (argc == 0) { *off = 0; -- 1.7.9.1

3 2

[U-Boot] USB xHCI Support?
by Aaron Williams 26 Mar '12

26 Mar '12

Hi all, I was wondering if anyone has done any work on supporting USB 3.0 xHCI in U- Boot? -Aaron -- Aaron Williams <Aaron.Williams(a)cavium.com> (408) 943-7198

1 0

[U-Boot] Please pull u-boot-ti/master
by Tom Rini 26 Mar '12

26 Mar '12

Hello, The following changes since commit 32ec258f829808dd7cf74fd83ba999fdaaeab715: Marek Vasut (1): IXP: Fix GPIO_INT_ACT_LOW_SET() are available in the git repository at: git://git.denx.de/u-boot-ti master Simon Schwarz (8): Add cmd_spl command devkit8000: add config for spl command omap-common: Add NAND SPL linux booting devkit8000/spl: init GPMC for dm9000 in SPL omap-common/spl: Add linux boot to SPL omap/spl: change output of spl_parse_image_header devkit8000: Implement and activate direct OS boot arm: Add Prep subcommand support to bootm Stefano Babic (4): Add cache functions to SPL for armv7 OMAP3: SPL: do not call I2C init if no I2C is set. SPL: call cleanup_before_linux() before booting Linux OMAP3: twister: add support to boot Linux from SPL Tom Rini (1): cam_enc_4xx: Rename 'images' to 'imgs' arch/arm/cpu/armv7/Makefile | 2 - arch/arm/cpu/armv7/cpu.c | 2 + arch/arm/cpu/armv7/omap-common/spl.c | 46 ++++- arch/arm/cpu/armv7/omap-common/spl_nand.c | 47 ++++- arch/arm/cpu/armv7/omap3/board.c | 2 + arch/arm/include/asm/bootm.h | 26 +++ arch/arm/include/asm/omap_common.h | 2 + arch/arm/lib/Makefile | 5 +- arch/arm/lib/bootm.c | 341 +++++++++++++++-------------- board/ait/cam_enc_4xx/cam_enc_4xx.c | 48 ++-- board/technexion/twister/twister.c | 23 ++ board/timll/devkit8000/devkit8000.c | 37 +++ common/Makefile | 1 + common/cmd_spl.c | 188 ++++++++++++++++ doc/README.commands.spl | 31 +++ include/cmd_spl.h | 31 +++ include/configs/devkit8000.h | 15 +- include/configs/twister.h | 12 + include/image.h | 2 + 19 files changed, 662 insertions(+), 199 deletions(-) create mode 100644 arch/arm/include/asm/bootm.h create mode 100644 common/cmd_spl.c create mode 100644 doc/README.commands.spl create mode 100644 include/cmd_spl.h These patches have been in progress for quite some time and Wolfgang has requested that they go in now rather than after the upcoming release. -- Tom

2 3

[U-Boot] Please pull u-boot-ti/next
by Tom Rini 26 Mar '12

26 Mar '12

Hello, The following changes since commit 5c91ee919c359e89fcb3230722253dbb9b4f7e32: Ian Campbell (1): ARM: dreamplug: Enable FDT support are available in the git repository at: git://git.denx.de/u-boot-ti next Balaji T K (3): arm: omap5: correct boot device mode7 for eMMC omap5: pbias ldo9 turn on mmc: omap5evm: Add eMMC saveenv support Enric Balletbò i Serra (1): OMAP3: igep00x0: Reduce lines of code for IGEP-based boards. Heiko Schocher (1): ARM: davinci: fixes for cam_enc_4xx board Jonathan Solnit (1): ARM:OMAP+:MMC: Add parameters to MMC init Nishanth Menon (3): OMAP3+: Introduce generic logic for OMAP voltage controller OMAP4460: TPS Ensure SET1 is selected after voltage configuration OMAP4: scale voltage of core before MPU scales SRICHARAN R (16): OMAP5: clocks: Change clock settings as required for ES1.0 silicon. OMAP5: board: Add pinmux data for omap5_evm board. OMAP5: io: Configure the io settings for omap5430 sevm board. OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon. OMAP5: palmas: Configure nominal opp vdd values OMAP5: hwinit: Add the missing break statement OMAP4/5: Make the silicon revision variable common. OMAP5: SRAM: Change the SRAM base address. OMAP4/5: Make the sysctrl structure common OMAP4/5: device: Add support to get the device type. OMAP5: defconfig: Align the defconfig for 5430 ES1.0 OMAP5: ddr: Change the ddr device name. OMAP4/5: emif: Correct the emif power mgt shadow register bit fields. power: twl6035: add palmas PMIC support OMAP3+: reset: Create a common reset layer. OMAP5: reset: Use cold reset in case of 5430ES1.0 arch/arm/cpu/armv7/am33xx/board.c | 2 +- arch/arm/cpu/armv7/omap-common/Makefile | 1 + arch/arm/cpu/armv7/omap-common/clocks-common.c | 99 ++--- arch/arm/cpu/armv7/omap-common/emif-common.c | 41 ++- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 6 +- .../arm/cpu/armv7/omap-common/{reset.S => reset.c} | 30 +- arch/arm/cpu/armv7/omap-common/spl.c | 1 + arch/arm/cpu/armv7/omap-common/spl_mmc.c | 5 +- arch/arm/cpu/armv7/omap-common/vc.c | 138 ++++++ arch/arm/cpu/armv7/omap4/clocks.c | 77 ++- arch/arm/cpu/armv7/omap4/hwinit.c | 24 +- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 4 + arch/arm/cpu/armv7/omap5/Makefile | 2 +- arch/arm/cpu/armv7/omap5/clocks.c | 143 ++++-- arch/arm/cpu/armv7/omap5/hwinit.c | 104 ++++- .../cpu/armv7/omap5/{sdram_elpida.c => sdram.c} | 101 +++-- arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 2 +- arch/arm/include/asm/arch-omap3/cpu.h | 5 +- arch/arm/include/asm/arch-omap3/mmc_host_def.h | 8 +- arch/arm/include/asm/arch-omap4/clocks.h | 18 +- arch/arm/include/asm/arch-omap4/cpu.h | 11 + arch/arm/include/asm/arch-omap4/mmc_host_def.h | 2 +- arch/arm/include/asm/arch-omap4/omap.h | 25 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 8 +- arch/arm/include/asm/arch-omap5/clocks.h | 52 ++- arch/arm/include/asm/arch-omap5/cpu.h | 11 + arch/arm/include/asm/arch-omap5/mmc_host_def.h | 2 +- arch/arm/include/asm/arch-omap5/mux_omap5.h | 502 ++++++++++---------- arch/arm/include/asm/arch-omap5/omap.h | 153 +++++-- arch/arm/include/asm/arch-omap5/sys_proto.h | 8 +- arch/arm/include/asm/emif.h | 76 +++- arch/arm/include/asm/omap_common.h | 11 +- board/ait/cam_enc_4xx/cam_enc_4xx.c | 55 ++- board/ait/cam_enc_4xx/config.mk | 7 + board/ait/cam_enc_4xx/u-boot-spl.lds | 2 +- board/cm_t35/cm_t35.c | 2 +- board/comelit/dig297/dig297.c | 2 +- board/corscience/tricorder/tricorder.c | 2 +- board/htkw/mcx/mcx.c | 2 +- board/isee/igep0020/igep0020.c | 4 +- board/isee/igep0030/igep0030.c | 4 +- board/logicpd/am3517evm/am3517evm.c | 2 +- board/logicpd/omap3som/omap3logic.c | 2 +- board/logicpd/zoom1/zoom1.c | 2 +- board/logicpd/zoom2/zoom2.c | 2 +- board/matrix_vision/mvblx/mvblx.c | 4 +- board/overo/overo.c | 2 +- board/pandora/pandora.c | 2 +- board/technexion/twister/twister.c | 2 +- board/teejet/mt_ventoux/mt_ventoux.c | 2 +- board/ti/am3517crane/am3517crane.c | 2 +- board/ti/beagle/beagle.c | 2 +- board/ti/evm/evm.c | 2 +- board/ti/omap5_evm/evm.c | 10 +- board/ti/omap5_evm/mux_data.h | 489 ++++++++++--------- board/ti/panda/panda.c | 2 +- board/ti/panda/panda_mux_data.h | 2 +- board/ti/sdp3430/sdp.c | 2 +- board/ti/sdp4430/sdp.c | 4 +- board/ti/sdp4430/sdp4430_mux_data.h | 2 +- board/timll/devkit8000/devkit8000.c | 2 +- boards.cfg | 4 +- drivers/mmc/omap_hsmmc.c | 61 +++- drivers/power/Makefile | 1 + drivers/power/twl6035.c | 65 +++ include/configs/cam_enc_4xx.h | 13 +- include/configs/igep0030.h | 261 ---------- include/configs/{igep0020.h => igep00x0.h} | 15 +- include/configs/omap5_evm.h | 25 +- .../armv7/omap-common/reset.S => include/twl6035.h | 38 +- 70 files changed, 1612 insertions(+), 1162 deletions(-) copy arch/arm/cpu/armv7/omap-common/{reset.S => reset.c} (70%) create mode 100644 arch/arm/cpu/armv7/omap-common/vc.c rename arch/arm/cpu/armv7/omap5/{sdram_elpida.c => sdram.c} (64%) create mode 100644 drivers/power/twl6035.c delete mode 100644 include/configs/igep0030.h rename include/configs/{igep0020.h => igep00x0.h} (97%) rename arch/arm/cpu/armv7/omap-common/reset.S => include/twl6035.h (53%) -- Tom

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[U-Boot] [PATCH] powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
by Timur Tabi 26 Mar '12

26 Mar '12

The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but that register does not exist on e500v1. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/start.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 4d37d6e..d0872cf 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -434,13 +434,15 @@ create_ccsr_new_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + mtspr MAS7, r7 +#endif mtspr MAS0, r0 mtspr MAS1, r1 mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe @@ -456,12 +458,14 @@ create_ccsr_old_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS li r7, 0 /* The default CCSR address is always a 32-bit number */ + mtspr MAS7, r7 +#endif mtspr MAS0, r0 /* MAS1 is the same as above */ mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe -- 1.7.10.rc1.8.ga99c5.dirty

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[U-Boot] T4 U-boot: ctrl_regs.c: wr used uninitialized
by Scott Wood 26 Mar '12

26 Mar '12

I get this in the T4 branch of U-Boot: > Configuring for T4240QDS_EMU - Board: T4240QDS, Options: EMU > ctrl_regs.c: In function 'compute_fsl_memctl_config_regs': > ctrl_regs.c:852:15: warning: 'wr' may be used uninitialized in this function It does not appear to be a false positive (though it is an error path), and in any case such warnings should be squashed so that real warnings stick out. It was introduced by this patch: > commit 18496c6d6cf46177e7faeb364cfe5baddb8cf71e > Author: York Sun <yorksun(a)freescale.com> > Date: Tue Dec 13 14:16:55 2011 -0800 > > powerpc/mpc8xxx: Add support for cas latency 12 and above > > Required by JEDEC 79-3E for high speed DDR3. > Also change "CSn disabled" message to debug. > > Signed-off-by: York Sun <yorksun(a)freescale.com> I also don't see the T4 patches being posted to the mailing list -- why? And why is there any notion of a 32-bit physical address map for T4, and a README that suggests the 32-bit address map is used? -Scott

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[U-Boot] [PATCH 3/4][v2] powerpc/85xx:Make debug exception vector accessible
by Prabhakar Kushwaha 26 Mar '12

26 Mar '12

Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR + IVOR15) to have valid and fetchable OP code. While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to fetch an instruction from the debug exception vector (IVPR + IVOR15); since now we are in AS=0, the application needs to ensure the proper TLB configuration to have (IVOR + IVOR15) accessible from AS=0 also. Create a temporary TLB in AS0 to make sure debug exception verctor is accessible on debug exception. Signed-off-by: Radu Lazarescu <radu.lazarescu(a)freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master Changes for v2: - Put Temporary TLB creation under #define Tested on - SoC having E500 Family processor (P1010RDB, BSC9131RDB) - SoC having E500MC Family processor (P4080DS, P3041DS) arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 32 +++++++++++++++- arch/powerpc/cpu/mpc85xx/start.S | 60 +++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 3 +- 3 files changed, 93 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 091af7c..d0b15a4 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc + * Copyright 2009-2012 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -53,6 +53,36 @@ void setup_ifc(void) asm volatile("isync;msync;tlbwe;isync"); +#if defined(CONFIG_E500) && defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) +/* + * TLB for debuggging in AS1 + * Create temporary TLB in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB (in AS0) is required to handle debug exception generated + * in AS1. + * + * TLB is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's physical address is going to change as + * CONFIG_SYS_FLASH_BASE_PHYS. + */ + _mas0 = MAS0_TLBSEL(1) | + MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); + _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT | + MAS1_TSIZE(BOOKE_PAGESZ_4M); + _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); + _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); + _mas7 = FSL_BOOKE_MAS7(flash_phys); + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); + mtspr(MAS7, _mas7); + + asm volatile("isync;msync;tlbwe;isync"); +#endif + + /* Change flash's physical address */ out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 597151b..cef00ba 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -182,6 +182,66 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b +#if defined(CONFIG_E500) && defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) +/* + * TLB for debuggging in AS1 + * Create temporary TLB in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB (in AS0) is required to handle debug exception generated + * in AS1. + */ + + lis r6,FSL_BOOKE_MAS0(1, + CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, + CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l + +#if !defined(CONFIG_SYS_RAMBOOT) +/* + * TLB is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. + * and this window is outside of 4K boot window. + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, + (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, + (MAS2_I|MAS2_G))@l + + /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ + lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#else +/* + * TLB is created for IVPR + IVOR15 to map on valid OP code address + * because "nexti" will resize TLB to 4K + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, + (MAS2_I|MAS2_G))@l + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif + lis r10,0xffc00000@h + ori r10,r10,0xffc00000@l + + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + mtspr MAS7,r10 + isync + msync + tlbwe +#endif + /* * Ne need to setup interrupt vector for NAND SPL * because NAND SPL never compiles it. diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8654625..268c56e 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -107,6 +107,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_FSL_SATA_V2 -- 1.7.5.4

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[U-Boot] Patchwork housekeeping
by Graeme Russ 26 Mar '12

26 Mar '12

Hello Custodians and Mailing List Aficionados, I don't know if anyone has noticed, but patchwork is starting to collect a rather large amount of cruft. I occasionally jump onto patchwork and do a little housekeeping by marking updated patches as 'Superceeded' and anything applied by Wolfgang as 'Accepted' (There may be a few patches that have been applied to custodian tress that I marked as 'Accepted' when really they should have been marked as 'Awaiting Upstream') I really don't mind doing this housekeeping, but I would like to make a few suggestions that will make the work a little easier: - If you are a custodian: o When you apply a patch to your repo, can you please assign it to yourself in patchwork and set it to 'Awaiting Upstream' o Reply to the ML with 'Applied to <repo>/<branch>' o When you send a pull request, create a bundle with all the patches that are to be pulled (you can create the bundle early and add patches as you apply them) o When Wolfgang pulls your repo, go to the bundle and mark all the patches 'Accepted' - If you are a patch submitter: o Visit http://patchwork.ozlabs.org/project/uboot/list/ o Search for your patches by following the 'Filters'link and entering your name o Send and email (with 'patchwork' somewhere in the subject) to the ML with a list of patches that you submitted say more than one month ago. For each patch, please indicate if the patch is: * Superseded - By another patch (either by you or someone else) * Not Applicable - The patch can be ignored (was an RFC, was due to a misunderstanding, another patch did the same thing, etc) * Applied - Has been applied (state the repo and branch) * Rejected - Patch has been officially rejected * Waiting - You believe the patch is still valid but has not been applied (send a ping as a reply to the patch on the mailing list as well * Other - Please describe what state you feel the patch is in Once I get the raw list down to a manageable level, I'll start to look at the leftovers... Regards, "Your friendly Patchwork janitor" Graeme

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[U-Boot] [PATCH v2] mmc: fsl_esdhc: Poll until card is not busy anymore
by Dirk Behme 26 Mar '12

26 Mar '12

This patch imports parts of two patches from the Freescale U-Boot with the following commit messages: ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648 http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/… The errata, not applicable to USDHC, causes ESDHC to shut off clock to the card when auto-clock gating is enabled for commands with busy signalling and no data phase. The card might require the clock to exit the busy state, so the workaround is to disable the auto-clock gate bits in SYSCTL register for such commands. The workaround also entails polling on DAT0 bit in the PRSSTAT register to learn when busy state is complete. Auto-clock gating is re-enabled at the end of busy state. ENGR00156670-1 ESDHC/USDHC: Remove delay before each cmd and some bug fixes http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/drivers/mmc/… Removed delay of 10 ms before each command. There should not be a need to have this delay after the ENGR00156405 patch that polls until card is not busy anymore before proceeding to next cmd. This patch imports the polling part of both patches. The auto-clock gating code don't apply for i.MX6 as implemented in these two patches. SYSCTL_RSTA was defined twice. Remove one definition. Signed-off-by: Dirk Behme <dirk.behme(a)de.bosch.com> CC: Andy Fleming <afleming(a)freescale.com> CC: Fabio Estevam <fabio.estevam(a)freescale.com> CC: Stefano Babic <sbabic(a)denx.de> --- Changes in v2: * Drop the removal of the udelay(). It's not sure if the PowerPC would be ok with this removal. * Drop touching the sysctl register. Reviewing the iMX6 spec shows that this was an NOP. drivers/mmc/fsl_esdhc.c | 39 ++++++++++++++++++++++++++++++++++++++- include/fsl_esdhc.h | 4 +++- 2 files changed, 41 insertions(+), 2 deletions(-) Index: freescale-u-boot-imx.git/drivers/mmc/fsl_esdhc.c =================================================================== --- freescale-u-boot-imx.git.orig/drivers/mmc/fsl_esdhc.c +++ freescale-u-boot-imx.git/drivers/mmc/fsl_esdhc.c @@ -307,19 +307,56 @@ esdhc_send_cmd(struct mmc *mmc, struct m #else esdhc_write32(&regs->xfertyp, xfertyp); #endif + + /* Mask all irqs */ + esdhc_write32(&regs->irqsigen, 0); + /* Wait for the command to complete */ - while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC)) + while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) ; irqstat = esdhc_read32(&regs->irqstat); esdhc_write32(&regs->irqstat, irqstat); + /* Reset CMD and DATA portions on error */ + if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { + esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) | + SYSCTL_RSTC); + while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC) + ; + + if (data) { + esdhc_write32(&regs->sysctl, + esdhc_read32(&regs->sysctl) | + SYSCTL_RSTD); + while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD)) + ; + } + } + if (irqstat & CMD_ERR) return COMM_ERR; if (irqstat & IRQSTAT_CTOE) return TIMEOUT; + /* Workaround for ESDHC errata ENGcm03648 */ + if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { + int timeout = 2500; + + /* Poll on DATA0 line for cmd with busy signal for 250 ms */ + while (timeout > 0 && !(esdhc_read32(&regs->prsstat) & + PRSSTAT_DAT0)) { + udelay(100); + timeout--; + } + + if (timeout <= 0) { + printf("Timeout waiting for DAT0 to go high!\n"); + return TIMEOUT; + } + } + /* Copy the response to the response buffer */ if (cmd->resp_type & MMC_RSP_136) { u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; Index: freescale-u-boot-imx.git/include/fsl_esdhc.h =================================================================== --- freescale-u-boot-imx.git.orig/include/fsl_esdhc.h +++ freescale-u-boot-imx.git/include/fsl_esdhc.h @@ -34,12 +34,13 @@ #define SYSCTL_INITA 0x08000000 #define SYSCTL_TIMEOUT_MASK 0x000f0000 #define SYSCTL_CLOCK_MASK 0x0000fff0 -#define SYSCTL_RSTA 0x01000000 #define SYSCTL_CKEN 0x00000008 #define SYSCTL_PEREN 0x00000004 #define SYSCTL_HCKEN 0x00000002 #define SYSCTL_IPGEN 0x00000001 #define SYSCTL_RSTA 0x01000000 +#define SYSCTL_RSTC 0x02000000 +#define SYSCTL_RSTD 0x04000000 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -85,6 +86,7 @@ #define IRQSTATEN_CC (0x00000001) #define PRSSTAT 0x0002e024 +#define PRSSTAT_DAT0 (0x01000000) #define PRSSTAT_CLSL (0x00800000) #define PRSSTAT_WPSPL (0x00080000) #define PRSSTAT_CDPL (0x00040000)

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