March 2012 - U-Boot

[U-Boot] [PATCH 00/11] mtd/SMI: Add support for ST SMI controller
by Amit Virdi 20 Apr '12

20 Apr '12

In the current u-boot, a driver exists for ST's SMI controller. However, the driver is SPEAr specific. This patchset makes the driver more generic so that it can be used across multiple platforms. In the first commit, the driver is renamed to st_smi. In subsequent patches, changes are introduced so as to make the driver generic. Amit Virdi (4): st_smi: Remove compilation warning st_smi: Return error in case TFF is not set st_smi: Change SMI timeout values st_smi: Enhance the error handling Armando Visconti (3): st_smi: Removed no needed dependency on ST_M25Pxx_ID st_smi: Change the flash probing method st_smi: Fix bug in flash_print_info() Shiraz Hashim (1): st_smi: Move status register read before modifying ctrl register Vipin KUMAR (2): st_smi: Add support for SPEAr SMI driver st_smi: Read status until timeout happens Vipin Kumar (1): st_smi: Fix smi read status drivers/mtd/Makefile | 2 +- drivers/mtd/{spr_smi.c => st_smi.c} | 223 ++++++++++++-------- include/configs/spear-common.h | 6 +- .../spr_smi.h => include/linux/mtd/st_smi.h | 10 +- 4 files changed, 140 insertions(+), 101 deletions(-) rename drivers/mtd/{spr_smi.c => st_smi.c} (66%) rename arch/arm/include/asm/arch-spear/spr_smi.h => include/linux/mtd/st_smi.h (95%) -- 1.7.2.2

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[U-Boot] [PATCH v5] kirkwood: add support for Cloud Engines Pogoplug E02
by Dave Purdy 20 Apr '12

20 Apr '12

This patch adds support for Cloud Engines Pogoplug E02 Information regarding the CE Pogoplug E02 board can be found at: http://archlinuxarm.org/platforms/armv5/pogoplug-v2-pinkgray Signed-off-by: Dave Purdy <david.c.purdy(a)gmail.com> Cc: prafulla(a)marvell.com Cc: albert.u.boot(a)aribaud.net --- Changes for v5: - eliminated nonessential code in all files - changed boardname to conform to "pogo_e02" which is already in kernel mach-type table - cleaned up GNU license address/URL - fixed hexadecimal mixed-case in data, a typo and comments in kwbimage.cfg - minimized GPIO setup in pogo_e02.c Changes for v4: - remove parentheses from simple args - remove erroneous comment and redundant code in config - remove line wraps Changes for v3: - fix ordering mistake in boards.cfg Changes for v2: - added MAINTAINERS info for pogoplug_e02 - fixed format to ensure capture of all files in path MAINTAINERS | 4 + board/cloudengines/pogo_e02/Makefile | 43 ++++++++ board/cloudengines/pogo_e02/kwbimage.cfg | 169 ++++++++++++++++++++++++++++++ board/cloudengines/pogo_e02/pogo_e02.c | 118 +++++++++++++++++++++ board/cloudengines/pogo_e02/pogo_e02.h | 44 ++++++++ boards.cfg | 1 + include/configs/pogo_e02.h | 119 +++++++++++++++++++++ 7 files changed, 498 insertions(+), 0 deletions(-) create mode 100644 board/cloudengines/pogo_e02/Makefile create mode 100644 board/cloudengines/pogo_e02/kwbimage.cfg create mode 100644 board/cloudengines/pogo_e02/pogo_e02.c create mode 100644 board/cloudengines/pogo_e02/pogo_e02.h create mode 100644 include/configs/pogo_e02.h diff --git a/MAINTAINERS b/MAINTAINERS index 46f63a0..f80f7ad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -793,6 +793,10 @@ Stelian Pop <stelian(a)popies.net> at91sam9263ek ARM926EJS (AT91SAM9263 SoC) at91sam9rlek ARM926EJS (AT91SAM9RL SoC) +Dave Purdy <david.c.purdy(a)gmail.com> + + pogo_e02 ARM926EJS (Kirkwood SoC) + Thierry Reding <thierry.reding(a)avionic-design.de> plutux Tegra2 (ARM7 & A9 Dual Core) diff --git a/board/cloudengines/pogo_e02/Makefile b/board/cloudengines/pogo_e02/Makefile new file mode 100644 index 0000000..7f86691 --- /dev/null +++ b/board/cloudengines/pogo_e02/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; If not, see <http://www.gnu.org/licenses/>. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := pogo_e02.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cloudengines/pogo_e02/kwbimage.cfg b/board/cloudengines/pogo_e02/kwbimage.cfg new file mode 100644 index 0000000..a02e88d --- /dev/null +++ b/board/cloudengines/pogo_e02/kwbimage.cfg @@ -0,0 +1,169 @@ +# +# Copyright (C) 2012 +# David Purdy <david.c.purdy(a)gmail.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; If not, see <http://www.gnu.org/licenses/>. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xffd01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[2]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c new file mode 100644 index 0000000..ff3421d --- /dev/null +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2012 + * David Purdy <david.c.purdy(a)gmail.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "pogo_e02.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(POGO_E02_OE_VAL_LOW, + POGO_E02_OE_VAL_HIGH, + POGO_E02_OE_LOW, POGO_E02_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_UART0_RTS, + MPP9_UART0_CTS, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP29_TSMP9, /* USB Power Enable */ + MPP48_GPIO, /* LED green */ + MPP49_GPIO, /* LED orange */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and initialize PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + debug("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/cloudengines/pogo_e02/pogo_e02.h b/board/cloudengines/pogo_e02/pogo_e02.h new file mode 100644 index 0000000..40b4bab --- /dev/null +++ b/board/cloudengines/pogo_e02/pogo_e02.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 + * David Purdy <david.c.purdy(a)gmail.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __POGO_E02_H +#define __POGO_E02_H + +/* GPIO configuration */ +#define POGO_E02_OE_LOW (~(0)) +#define POGO_E02_OE_HIGH (~(0)) +#define POGO_E02_OE_VAL_LOW (1 << 29) +#define POGO_E02_OE_VAL_HIGH 0 + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __POGO_E02_H */ diff --git a/boards.cfg b/boards.cfg index 28cc345..e070f69 100644 --- a/boards.cfg +++ b/boards.cfg @@ -136,6 +136,7 @@ hawkboard arm arm926ejs da8xxevm davinci hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT enbw_cmc arm arm926ejs enbw_cmc enbw davinci calimain arm arm926ejs calimain omicron davinci +pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h new file mode 100644 index 0000000..ad4a1fb --- /dev/null +++ b/include/configs/pogo_e02.h @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2012 + * David Purdy <david.c.purdy(a)gmail.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _CONFIG_POGO_E02_H +#define _CONFIG_POGO_E02_H + +/* + * Machine type definition and ID + */ +#define MACH_TYPE_POGO_E02 3542 +#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02 +#define CONFIG_IDENT_STRING "\nPogo E02" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#define CONFIG_SYS_MVFS +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ +#define CONFIG_SYS_PROMPT "PogoE02> " + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs $(bootargs_console); " \ + "run bootcmd_usb; " \ + "bootm 0x00800000 0x01100000" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \ + "32M(rootfs),-(data)\0"\ + "mtdids=nand0=orion_nand\0"\ + "bootargs_console=console=ttyS0,115200\0" \ + "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ + "ext2load usb 0:1 0x01100000 /uInitrd\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#endif /* CONFIG_CMD_NET */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +#endif /* _CONFIG_POGO_E02_H */ -- 1.7.0.4

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[U-Boot] [PATCH] powerpc/85xx: Add USB device-tree fixup for various platforms
by Ramneek Mehresh 19 Apr '12

19 Apr '12

Add USB device-tree fixup for following platforms: MPC8536DS, P1022DS, P1023RDS, P2020COME, P2020DS, P2041RDB, P3060QDS Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> --- board/freescale/mpc8536ds/mpc8536ds.c | 7 ++++++- board/freescale/p1022ds/p1022ds.c | 6 +++++- board/freescale/p1023rds/p1023rds.c | 6 +++++- board/freescale/p2020come/p2020come.c | 6 +++++- board/freescale/p2020ds/p2020ds.c | 6 +++++- board/freescale/p2041rdb/p2041rdb.c | 6 +++++- board/freescale/p3060qds/p3060qds.c | 6 +++++- include/configs/MPC8536DS.h | 5 ++++- include/configs/P1022DS.h | 5 ++++- include/configs/P1023RDS.h | 5 ++++- include/configs/P2020COME.h | 6 ++++-- include/configs/P2020DS.h | 5 ++++- include/configs/P2041RDB.h | 8 +++++++- include/configs/corenet_ds.h | 8 ++++++-- 14 files changed, 69 insertions(+), 16 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index c9f85c8..fb20192 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -295,5 +295,10 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + +#ifdef CONFIG_HAS_FSL_MPH_USB + fdt_fixup_dr_usb(blob, bd); +#endif + } #endif diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 456d9b0..f9ba1f8 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan <srikanth.srinivasan(a)freescale.com> * Timur Tabi <timur(a)freescale.com> * @@ -341,6 +341,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 546819c..2f87583 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * Authors: Roy Zang <tie-fei.zang(a)freescale.com> * Chunhe Lan <b25806(a)freescale.com> @@ -197,6 +197,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + fdt_fixup_fman_ethernet(blob); } #endif diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c index 8cf7bee..ce78016 100644 --- a/board/freescale/p2020come/p2020come.c +++ b/board/freescale/p2020come/p2020come.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -282,6 +282,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + fdt_fixup_dr_usb(blob, bd); } #endif diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index d3af6cf..d9465f9 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -261,6 +261,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 1f6a34b..51c4310 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -215,6 +215,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + #ifdef CONFIG_PCI pci_of_setup(blob, bd); #endif diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c index c6c74f2..a413b71 100644 --- a/board/freescale/p3060qds/p3060qds.c +++ b/board/freescale/p3060qds/p3060qds.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -326,6 +326,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + #ifdef CONFIG_PCI pci_of_setup(blob, bd); #endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index c26cb63..e152999 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -714,6 +714,8 @@ /* * USB */ +#define CONFIG_HAS_FSL_MPH_USB +#ifdef CONFIG_HAS_FSL_MPH_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -722,6 +724,7 @@ #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_STORAGE #endif +#endif #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) #define CONFIG_CMD_EXT2 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 70d751d..7096ac0 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan <srikanth.srinivasan(a)freescale.com> * Timur Tabi <timur(a)freescale.com> * @@ -434,6 +434,8 @@ /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -443,6 +445,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_CMD_FAT #endif +#endif /* * Miscellaneous configurable options diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index e057b1f..be55da4 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * Authors: Roy Zang <tie-fei.zang(a)freescale.com> * Chunhe Lan <b25806(a)freescale.com> @@ -447,6 +447,8 @@ extern unsigned long get_clock_freq(void); /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -459,6 +461,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #endif +#endif /* * Miscellaneous configurable options diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h index 365322c..5d50a55 100644 --- a/include/configs/P2020COME.h +++ b/include/configs/P2020COME.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2010,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -399,6 +399,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif /* CONFIG_MMC */ +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -406,7 +408,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_STORAGE -#define CONFIG_HAS_FSL_DR_USB +#endif #endif #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index f0eb029..76a9d17 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -646,6 +646,8 @@ /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -654,6 +656,7 @@ #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif +#endif #undef CONFIG_WATCHDOG /* watchdog disabled */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index da98f8f..4c18daa 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -518,11 +518,17 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_HAS_FSL_MPH_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + #define CONFIG_CMD_EXT2 #define CONFIG_MMC diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 77dd0a2..38cf5d1 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -582,13 +582,17 @@ /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_HAS_FSL_MPH_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_CMD_EXT2 -#define CONFIG_HAS_FSL_DR_USB +#endif #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC -- 1.7.1

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[U-Boot-Users] Ethernet loopback command
by Thomas Schäfer 17 Apr '12

17 Apr '12

Hi, The patch attached provides a command called 'ethloop' which allows to perform loopback testing on the current eth device. To achieve this, a new ethernet packet type (PROT_TEST, 0x0808, AFAIK this is not used otherwise) is introduced in net/net.c. The patch is against SF CVS from 20050307. The functions EthLoopStart, EthLoopSend and EthLoopHandler generate a simple ethernet frame with NetOurEther as destination address and packet type PROT_TEST. The looped back package is compared with the original one and a message is displayed. It is necessary to set the ethernet line into loopback mode either by programming the PHY or using a loopback plug. I've tested this on our PPC405 custom board, but it should also work on all other systems because packet generation is independent of the underlying ethernet hardware. Example usage: => mii w 0 0 7100 <-- sets PHY into loopback mode => ethloop Using ppc_405x_eth0 device Got ethernet loopback frame, len=64 loopback test successfully completed => mii w 0 0 8000 <-- PHY reset after test is completed Maybe this is also useful for others.. Best regards, Thomas Schäfer ____________________________________ Kontron Modular Computers GmbH Konrad-Zuse-Str. 9 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: thomas.schaefer(a)kontron.com

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[U-Boot] [PATCH] drivers/mtd/spr_smi.c: Fix build warning
by Anatolij Gustschin 14 Apr '12

14 Apr '12

Fix: spr_smi.c: In function 'smi_write': spr_smi.c:325:15: warning: variable 'WM' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Cc: Vipin Kumar <vipin.kumar(a)st.com> --- drivers/mtd/spr_smi.c | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c index 9a70a19..6d4257a 100644 --- a/drivers/mtd/spr_smi.c +++ b/drivers/mtd/spr_smi.c @@ -322,24 +322,19 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, unsigned int length, ulong bank_addr) { int banknum; - unsigned int WM; switch (bank_addr) { case SMIBANK0_BASE: banknum = BANK0; - WM = WM0; break; case SMIBANK1_BASE: banknum = BANK1; - WM = WM1; break; case SMIBANK2_BASE: banknum = BANK2; - WM = WM2; break; case SMIBANK3_BASE: banknum = BANK3; - WM = WM3; break; default: return -1; -- 1.7.7.6

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[U-Boot] usb ethernet working on panda?
by Kumar Gala 13 Apr '12

13 Apr '12

Does anyone have usb ethernet working on top of git tree on a panda board? If so any gotcha's or details on how you have it working. thanks - k

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[U-Boot] [PATCH 0/6] tegra: Add NAND flash support
by Simon Glass 13 Apr '12

13 Apr '12

This series adds NAND flash support to Tegra and enables it on Seaboard. Included here is a proposed device tree binding which I'm sure will stretch some eyes. The binding includes information about the NAND controller as well as the connected NAND device. The Seaboard has a Hynix HY27UF4G2B. The driver supports ECC-based access and uses DMA and NAND acceleration features of the Tegra SOC to provide access at reasonable speed. Jim Lin (1): tegra: nand: Add Tegra NAND driver Simon Glass (5): fdt: Add debugging to fdtdec_get_int/addr() tegra: Add NAND support to funcmux tegra: fdt: Add NAND controller binding and definitions tegra: fdt: Add NAND definitions to fdt tegra: Enable NAND on Seaboard arch/arm/cpu/armv7/tegra2/funcmux.c | 7 + arch/arm/dts/tegra20.dtsi | 7 +- arch/arm/include/asm/arch-tegra2/funcmux.h | 3 + arch/arm/include/asm/arch-tegra2/tegra2.h | 1 + board/nvidia/dts/tegra2-seaboard.dts | 15 + doc/device-tree-bindings/nand/nvidia-nand.txt | 68 ++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/tegra2_nand.c | 1074 +++++++++++++++++++++++++ drivers/mtd/nand/tegra2_nand.h | 303 +++++++ include/configs/seaboard.h | 9 + include/fdtdec.h | 1 + lib/fdtdec.c | 23 +- 12 files changed, 1505 insertions(+), 7 deletions(-) create mode 100644 doc/device-tree-bindings/nand/nvidia-nand.txt create mode 100644 drivers/mtd/nand/tegra2_nand.c create mode 100644 drivers/mtd/nand/tegra2_nand.h -- 1.7.7.3

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[U-Boot] device tree compilation problems.
by hanumant 13 Apr '12

13 Apr '12

Hi I am getting DTC when compiling dts file with CONFIG_OF_CONTROL. The message says that it cannot find skeleton.dtsi though its placed in the same directory as the dts file. I notice that if i remove this line from the dts Makefile, the error disappears $(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts - cat $< | $(CPP) -P $(DTS_CPPFLAGS) - >$@.tmp - $(DTC) -R 4 -p 0x1000 -O dtb -o ${DT_BIN} $@.tmp - rm $@.tmp + $(DTC) -R 4 -p 0x1000 -O dtb -o ${DT_BIN} $< Has anyone faced this issue? Thanks Hanumant

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[U-Boot] [PATCH v2 0/20] tegra: warmboot (suspend / resume) support
by Simon Glass 13 Apr '12

13 Apr '12

This series adds support for warm boot, allowing the device to suspend and resume. U-Boot sets up some 'warm boot' code in a special area such that the SOC can find it on a resume. This code is responsible for setting up memory and clocked and then allowing the OS to continue where it left off. Also included here is support for the EMC, which allows setting the memory timings correctly in U-Boot for maximum speed operation. Note: sign-offs are needed from Jimmy Zhang, Wei Ni and Yen Lin. Changes in v2: - Add check of undocumented values in hidrev register - Add debug() output to EMC - Add new fdtdec_locate_array() function - Add patch to find DVC bus number - Check error return from pmu_set_nominal() in debug mode - Move EMC tables to device tree - Move structs shared between A9 and AVP into warmboot.h header file - New patch to add low-level clock functions - Rely on compiler to optimise out debug_print_vector() - Remove unused crypto code - Remove unused crypto code from crypto.c - Removed check for nominal voltage (not needed as it is done just before) - Split PMU code into separate TPS6586X driver - Tidy SDRAM range check in warmboot_prepare_code() - Tidy whitespace problems - Use const for sbox arrays - Use low-level clock functions in warmboot code instead of register access Jimmy Zhang (3): tegra: Add EMC support for optimal memory timings tegra: Add PMU to manage power supplies tegra: Add EMC settings for Seaboard Simon Glass (11): fdt: Add function to locate an array in the device tree i2c: Add TPS6586X driver tegra: Move ap20.h header into arch location tegra: Add functions to access low-level Osc/PLL details tegra: Add tegra_get_chip_type() to detect SKU tegra: Set up PMU for Nvidia boards tegra: Set up warmboot code on Nvidia boards fdt: tegra: Add EMC node to device tree tegra: i2c: Add function to find DVC bus tegra: fdt: Add EMC data for Tegra2 Seaboard tegra: Enable LP0 on Seaboard Wei Ni (1): Tegra2: Turn off power detect in board init Yen Lin (5): Add AES crypto library tegra: Add crypto library for warmboot code tegra: Add flow, gp_padctl, fuse, sdram headers tegra: Add warmboot implementation tegra: Setup PMC scratch info from ap20 setup arch/arm/cpu/armv7/tegra2/Makefile | 4 + arch/arm/cpu/armv7/tegra2/ap20.c | 44 ++- arch/arm/cpu/armv7/tegra2/board.c | 4 +- arch/arm/cpu/armv7/tegra2/clock.c | 32 + arch/arm/cpu/armv7/tegra2/crypto.c | 230 ++++++++ arch/arm/cpu/armv7/tegra2/crypto.h | 36 ++ arch/arm/cpu/armv7/tegra2/emc.c | 192 +++++++ arch/arm/cpu/armv7/tegra2/pmu.c | 70 +++ arch/arm/cpu/armv7/tegra2/warmboot.c | 382 +++++++++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.c | 250 ++++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.h | 81 +++ arch/arm/dts/tegra20.dtsi | 7 + .../tegra2 => include/asm/arch-tegra2}/ap20.h | 7 + arch/arm/include/asm/arch-tegra2/clk_rst.h | 3 + arch/arm/include/asm/arch-tegra2/clock.h | 22 + arch/arm/include/asm/arch-tegra2/emc.h | 112 ++++ arch/arm/include/asm/arch-tegra2/flow.h | 36 ++ arch/arm/include/asm/arch-tegra2/fuse.h | 39 ++ arch/arm/include/asm/arch-tegra2/gp_padctrl.h | 73 +++ arch/arm/include/asm/arch-tegra2/pmu.h | 30 + arch/arm/include/asm/arch-tegra2/sdram_param.h | 148 +++++ arch/arm/include/asm/arch-tegra2/tegra2.h | 25 + arch/arm/include/asm/arch-tegra2/tegra2_i2c.h | 7 + arch/arm/include/asm/arch-tegra2/warmboot.h | 150 +++++ board/nvidia/common/Makefile | 1 + board/nvidia/common/board.c | 38 ++- board/nvidia/common/emc.c | 53 ++ board/nvidia/common/emc.h | 29 + board/nvidia/dts/tegra2-seaboard.dts | 73 +++ drivers/i2c/tegra2_i2c.c | 14 + drivers/power/Makefile | 1 + drivers/power/tps6586x.c | 293 ++++++++++ include/aes.h | 70 +++ include/configs/seaboard.h | 8 + include/configs/tegra2-common.h | 17 + include/fdtdec.h | 21 + include/tps6586x.h | 68 +++ lib/Makefile | 1 + lib/aes.c | 598 ++++++++++++++++++++ lib/fdtdec.c | 13 + 40 files changed, 3278 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/crypto.c create mode 100644 arch/arm/cpu/armv7/tegra2/crypto.h create mode 100644 arch/arm/cpu/armv7/tegra2/emc.c create mode 100644 arch/arm/cpu/armv7/tegra2/pmu.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot_avp.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot_avp.h rename arch/arm/{cpu/armv7/tegra2 => include/asm/arch-tegra2}/ap20.h (96%) create mode 100644 arch/arm/include/asm/arch-tegra2/emc.h create mode 100644 arch/arm/include/asm/arch-tegra2/flow.h create mode 100644 arch/arm/include/asm/arch-tegra2/fuse.h create mode 100644 arch/arm/include/asm/arch-tegra2/gp_padctrl.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmu.h create mode 100644 arch/arm/include/asm/arch-tegra2/sdram_param.h create mode 100644 arch/arm/include/asm/arch-tegra2/warmboot.h create mode 100644 board/nvidia/common/emc.c create mode 100644 board/nvidia/common/emc.h create mode 100644 drivers/power/tps6586x.c create mode 100644 include/aes.h create mode 100644 include/tps6586x.h create mode 100644 lib/aes.c -- 1.7.7.3

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[U-Boot] CONFIG_SYS_FDT_PAD: Why do we need this?
by Dirk Behme 12 Apr '12

12 Apr '12

In boot_relocate_fdt() [1] we increase the size of the loaded fdt by a predefined, hard coded CONFIG_SYS_FDT_PAD. The basic idea seem to be to create some space for adding additional information later, like the bootargs. I wonder why we have to do this by a hard coded, predefined value (which is most probably always to large)? Why can't we increase 'totalsize' in the fdt_header just if we add anything? Individually by the size of the element added, at runtime? E.g. by anything like [2]? I debugged a system were #define CONFIG_SYS_FDT_PAD 0x3000 was used. These 0x3000 are added to totalsize before something is added at all. Then, if an element is added, always the whole 0x3000 bytes have to be memmoved additionally. And in the end only ~0x100 additional space was really needed. Best regards Dirk [1] http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=blob;f=common/image.c;… [2] static int _fdt_splice_struct(void *fdt, void *p, int oldlen, int newlen) { int delta = newlen - oldlen; int err; if ((err = _fdt_splice(fdt, p, oldlen, newlen))) return err; fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta); fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta); + fdt_set_totalsize(fdt, fdt_totalsize(fdt) + delta); return 0; } in http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=blob;f=lib/libfdt/fdt_…

2 1