November 2012 - U-Boot

[U-Boot] [PATCH] Pass sdrc timing values through board_sdrc_timings structure
by Peter Barada 10 Dec '12

10 Dec '12

Instead of passing individual registers by value to board_get_mem_timings, pass a board_mem_timings structure pointer for the board files to fill in. Pass same structure pointer to write_sdrc_timings. This saves about 90 bytes of space in SPL. Signed-off-by: Peter Barada <peter.barada(a)logicpd.com> --- arch/arm/cpu/armv7/omap3/sdrc.c | 36 ++++++++---------- arch/arm/include/asm/arch-omap3/sys_proto.h | 13 ++++++- board/corscience/tricorder/tricorder.c | 13 +++---- board/isee/igep0020/igep0020.c | 29 +++++++-------- board/isee/igep0030/igep0030.c | 29 +++++++-------- board/overo/overo.c | 37 +++++++++---------- board/ti/beagle/beagle.c | 53 +++++++++++++-------------- board/ti/evm/evm.c | 19 +++++----- board/timll/devkit8000/devkit8000.c | 13 +++---- 9 files changed, 120 insertions(+), 122 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index f6d9b97..e32bf11 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -113,18 +113,18 @@ u32 get_sdr_cs_offset(u32 cs) * - Test CS to make sure it's OK for use */ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, - u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr) + struct board_sdrc_timings *timings) { /* Setup timings we got from the board. */ - writel(mcfg, &sdrc_base->cs[cs].mcfg); - writel(ctrla, &sdrc_actim_base->ctrla); - writel(ctrlb, &sdrc_actim_base->ctrlb); - writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); + writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); + writel(timings->ctrla, &sdrc_actim_base->ctrla); + writel(timings->ctrlb, &sdrc_actim_base->ctrlb); + writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); writel(CMD_NOP, &sdrc_base->cs[cs].manual); writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(mr, &sdrc_base->cs[cs].mr); + writel(timings->mr, &sdrc_base->cs[cs].mr); /* * Test ram in this bank @@ -143,7 +143,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, void do_sdrc_init(u32 cs, u32 early) { struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; - u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr; + struct board_sdrc_timings timings; sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; @@ -158,7 +158,7 @@ void do_sdrc_init(u32 cs, u32 early) * setup CS1. */ #ifdef CONFIG_SPL_BUILD - get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr); + get_board_mem_timings(&timings); #endif if (early) { /* reset sdrc controller */ @@ -177,11 +177,9 @@ void do_sdrc_init(u32 cs, u32 early) writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); #ifdef CONFIG_SPL_BUILD - write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, - rfr_ctrl, mr); + write_sdrc_timings(CS0, sdrc_actim_base0, &timings); make_cs1_contiguous(); - write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb, - rfr_ctrl, mr); + write_sdrc_timings(CS1, sdrc_actim_base1, &timings); #endif } @@ -193,14 +191,12 @@ void do_sdrc_init(u32 cs, u32 early) * so we may be asked now to setup CS1. */ if (cs == CS1) { - mcfg = readl(&sdrc_base->cs[CS0].mcfg), - rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); - ctrla = readl(&sdrc_actim_base0->ctrla), - ctrlb = readl(&sdrc_actim_base0->ctrlb); - mr = readl(&sdrc_base->cs[CS0].mr); - write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb, - rfr_ctrl, mr); - + timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), + timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); + timings.ctrla = readl(&sdrc_actim_base0->ctrla); + timings.ctrlb = readl(&sdrc_actim_base0->ctrlb); + timings.mr = readl(&sdrc_base->cs[CS0].mr); + write_sdrc_timings(cs, sdrc_actim_base1, &timings); } } diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 9e52b12..d60f2ad 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -32,6 +32,15 @@ struct emu_hal_params { u32 param1; }; +/* Board SDRC timing values */ +struct board_sdrc_timings { + u32 mcfg; + u32 ctrla; + u32 ctrlb; + u32 rfr_ctrl; + u32 mr; +}; + void prcm_init(void); void per_clocks_enable(void); void ehci_clocks_enable(void); @@ -39,8 +48,8 @@ void ehci_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr); + +void get_board_mem_timings(struct board_sdrc_timings *timings); void identify_nand_chip(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index aaff2e8..56fe495 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -91,15 +91,14 @@ int board_mmc_init(bd_t *bis) * provides the timing values back to the function that configures * the memory. We have either one or two banks of 128MB DDR. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { /* General SDRC config */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; /* AC timings */ - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *mr = MICRON_V_MR_165; + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->mr = MICRON_V_MR_165; } diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index a8257a3..a0f2aa3 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -72,27 +72,26 @@ void omap_rev_string(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif } diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 107cb7f..a41e752 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -59,27 +59,26 @@ void omap_rev_string(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif } diff --git a/board/overo/overo.c b/board/overo/overo.c index c6d50a0..fdf46a2 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -147,34 +147,33 @@ int get_board_revision(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = MICRON_V_MCFG_165(256 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = HYNIX_V_MCFG_165(256 << 20); - *ctrla = HYNIX_V_ACTIMA_165; - *ctrlb = HYNIX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = HYNIX_V_MCFG_165(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_165; + timings->ctrlb = HYNIX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; default: - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } } #endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6175e1d..4adf982 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -139,8 +139,7 @@ static int get_board_revision(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; @@ -151,29 +150,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, */ identify_nand_chip(&pop_mfr, &pop_id); - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_C4: if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { /* 512MB DDR */ - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) { /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { /* Beagleboard Rev C5, 256MB DDR */ - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; } case REVISION_XM_A: @@ -181,24 +180,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, case REVISION_XM_C: if (pop_mfr == 0) { /* 256MB DDR */ - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } else { /* 512MB DDR */ - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } break; default: /* Assume 128MB and Micron/165MHz timings to be safe */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } } #endif diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 61fc7b5..8a3aa0c 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -128,8 +128,7 @@ int board_init(void) * provides the timing values back to the function that configures * the memory. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; @@ -142,17 +141,17 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { /* 256MB DDR */ - *mcfg = HYNIX_V_MCFG_200(256 << 20); - *ctrla = HYNIX_V_ACTIMA_200; - *ctrlb = HYNIX_V_ACTIMB_200; + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; } else { /* 128MB DDR */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; } - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - *mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mr = MICRON_V_MR_165; } #endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 35f5e15..85685ee 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -188,16 +188,15 @@ int spl_start_uboot(void) * provides the timing values back to the function that configures * the memory. We have either one or two banks of 128MB DDR. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { /* General SDRC config */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; /* AC timings */ - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; } -- 1.7.1

2 1

[U-Boot] [PATCH] omap3_beagle.h: Fix comment for true/false return value.
by Robert P. J. Day 10 Dec '12

10 Dec '12

Signed-off-by: Robert P. J. Day <rpjday(a)crashcourse.ca> --- pretty sure that comment is inaccurate, but i'm willing to be corrected. diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 7a3cc16..741cbd9 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -287,7 +287,7 @@ "else run userbutton_nonxm; fi;\0" \ "userbutton_xm=gpio input 4;\0" \ "userbutton_nonxm=gpio input 7;\0" -/* "run userbutton" will return 1 (false) if is pressed and 0 (false) if not */ +/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run userbutton; then " \ -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

2 1

[U-Boot] [PATCH 0/6] EXYNOS: Add support for Exynos4x10
by Piotr Wilczek 10 Dec '12

10 Dec '12

This patch series adds Register base addresses, clock, gpio, power and system structures for Exynos4x10. Piotr Wilczek (6): Exynos: Exynos4x10: Add base addresses for Exynos4x10 Exynos: Exynos4x10: Add clock structure for exynos4x10 Exynos: Exynos4x10: Add gpio structure for Exynos4X10 Exynos: Exynos4x10: add power structure for Exynos4x10 Exynos: Exynos4x10: add sysreg structure for exynos4x10 arm: trats: Use exynos4x10 structures on Trats board arch/arm/include/asm/arch-exynos/clock.h | 236 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 43 +++++- arch/arm/include/asm/arch-exynos/gpio.h | 47 ++++++ arch/arm/include/asm/arch-exynos/power.h | 201 ++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/system.h | 9 + board/samsung/trats/trats.c | 40 +++--- 6 files changed, 551 insertions(+), 25 deletions(-) -- 1.7.5.4

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[U-Boot] [PATCHv3 4/4] at91sam9x5ek: add USB configuration
by richard.genoud＠gmail.com 09 Dec '12

09 Dec '12

From: Richard Genoud <richard.genoud(a)gmail.com> Signed-off-by: Richard Genoud <richard.genoud(a)gmail.com> --- include/configs/at91sam9x5ek.h | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+), 0 deletions(-) diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 5e5f9c1..915714f 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -91,6 +91,13 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_MMC #define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +/* + * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0) + * NB: in this case, USB 1.1 devices won't be recognized. + */ + /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 @@ -158,6 +165,22 @@ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_MACB_SEARCH_PHY +/* USB */ +#ifdef CONFIG_CMD_USB +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#else +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#endif +#define CONFIG_USB_ATMEL +#define CONFIG_USB_STORAGE +#endif + #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -- 1.7.2.5

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[U-Boot] [PATCHv3 3/4] at91sam9x5ek: regroup FAT/DOS features
by richard.genoud＠gmail.com 09 Dec '12

09 Dec '12

From: Richard Genoud <richard.genoud(a)gmail.com> Signed-off-by: Richard Genoud <richard.genoud(a)gmail.com> --- include/configs/at91sam9x5ek.h | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 71f765b..5e5f9c1 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -90,6 +90,7 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_SF #define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 @@ -142,9 +143,12 @@ /* MMC */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_CMD_FAT #define CONFIG_GENERIC_MMC #define CONFIG_GENERIC_ATMEL_MCI +#endif + +/* FAT */ +#ifdef CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #endif -- 1.7.2.5

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[U-Boot] [PATCHv3 2/4] at91sam9x5: enable USB support for 9x5ek board.
by richard.genoud＠gmail.com 09 Dec '12

09 Dec '12

From: Richard Genoud <richard.genoud(a)gmail.com> Signed-off-by: Richard Genoud <richard.genoud(a)gmail.com> --- arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 13 +++++++++++++ arch/arm/include/asm/arch-at91/at91sam9x5.h | 2 ++ board/atmel/at91sam9x5ek/at91sam9x5ek.c | 3 +++ drivers/usb/host/ohci-at91.c | 6 ++++-- 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index 9348552..0448c0b 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -193,6 +193,19 @@ void at91_spi1_hw_init(unsigned long cs_mask) } #endif +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) +void at91_uhp_hw_init(void) +{ + /* Enable VBus on UHP ports */ + at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */ + at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */ +#if defined(CONFIG_USB_OHCI_NEW) + /* port C is OHCI only */ + at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */ +#endif +} +#endif + #ifdef CONFIG_MACB void at91_macb_hw_init(void) { diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index 0e728c9..de0f1b1 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -154,6 +154,8 @@ #define ATMEL_PIO_PORTS 4 #define CPU_HAS_PIO3 #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP +#define ATMEL_ID_UHP ATMEL_ID_UHPHS /* * at91sam9x5 specific prototypes diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index edb0886..8773e6f 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -295,6 +295,9 @@ int board_init(void) at91_macb_hw_init(); #endif +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) + at91_uhp_hw_init(); +#endif #ifdef CONFIG_LCD at91sam9x5ek_lcd_hw_init(); #endif diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 9532dd9..efd711d 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -41,7 +41,8 @@ int usb_cpu_init(void) writel(get_pllb_init(), &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ + defined(CONFIG_AT91SAM9X5) /* Enable UPLL */ writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); @@ -81,7 +82,8 @@ int usb_cpu_stop(void) writel(0, &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ + defined(CONFIG_AT91SAM9X5) /* Disable UPLL */ writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr); while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) -- 1.7.2.5

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[U-Boot] [PATCH v2 0/5] Exynos: Support for display drivers
by Piotr Wilczek 09 Dec '12

09 Dec '12

This patchset add support for display on Universal C210 board. Max8998 is modified to power on display, new driver ld9040 and support for LCD display on universal C210 board is added. Changes in v2: - removed unnecessary function for fimd clock set; - code cleanup - removed patch for fix exynos4_fb structure Piotr Wilczek (5): misc:max8998 Add LDO macros drivers: video: Add ld9040 video driver arm: exynos4: cpu: Add definition for display drivers: video: fix image position arm: exynos4: universal_C210: add display support arch/arm/include/asm/arch-exynos/cpu.h | 1 + board/samsung/universal_c210/universal.c | 201 +++++++++++++++++++++++++++--- drivers/video/Makefile | 1 + drivers/video/exynos_fb.c | 15 ++- drivers/video/ld9040.c | 147 ++++++++++++++++++++++ include/configs/s5pc210_universal.h | 13 ++ include/ld9040.h | 32 +++++ include/max8998_pmic.h | 2 + 8 files changed, 392 insertions(+), 20 deletions(-) create mode 100644 drivers/video/ld9040.c create mode 100644 include/ld9040.h -- 1.7.5.4

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[U-Boot] [PATCH v2 0/6] Added SPL for MX35 boards
by Stefano Babic 08 Dec '12

08 Dec '12

In this patchset, a new i.MX35 board is added implementing the internal boot mode and using the general SPL Framework. To fix that relocation should not happen in SPL, the following patch is also required: http://patchwork.ozlabs.org/patch/181166/ Because the woodburn can boot from different media, two targets are added into boards.cfg: - woodburn : board boots in external mode from NOR flash - woodburn_sd: board boots in internal mode from SD This is the first i.MX board using the SPL framework. Changes in v2: - fix MX35 boot mode (Eric Benard) - uses SPL as binary instead of MLO (Thomas Petazzoni, Tom Rini) - NAND: the harware manufacturer decided for a different chip. Patches / issues related to NAND are dropped. - use board_init_f in SPL for setting SDRAM controller Stefano Babic (6): ARM: Fix start.S when used with SPL in arm1136 MX35: add LOW_LEVEL_SRAM_STACK to use SPL_FRAMEWORK MX35: Add soc_boot_mode and soc_boot_device to MX35 SPL: Added SPL target for mx35 SOC to SPL Makefile ARM: Add SPL target to arm1136 MX35: add support for woodburn board MAINTAINERS | 1 + Makefile | 1 + arch/arm/cpu/arm1136/config.mk | 3 + arch/arm/cpu/arm1136/mx35/Makefile | 1 + arch/arm/cpu/arm1136/mx35/generic.c | 75 ++++++ arch/arm/cpu/arm1136/mx35/mx35_sdram.c | 137 +++++++++++ arch/arm/cpu/arm1136/start.S | 31 ++- arch/arm/cpu/arm1136/u-boot-spl.lds | 62 +++++ arch/arm/include/asm/arch-mx35/imx-regs.h | 2 + arch/arm/include/asm/arch-mx35/mmc_host_def.h | 31 +++ arch/arm/include/asm/arch-mx35/spl.h | 38 +++ arch/arm/include/asm/arch-mx35/sys_proto.h | 2 + board/woodburn/Makefile | 43 ++++ board/woodburn/imximage.cfg | 4 + board/woodburn/lowlevel_init.S | 38 +++ board/woodburn/woodburn.c | 261 +++++++++++++++++++++ boards.cfg | 2 + include/configs/woodburn.h | 34 +++ include/configs/woodburn_common.h | 313 +++++++++++++++++++++++++ include/configs/woodburn_sd.h | 60 +++++ spl/Makefile | 6 + 21 files changed, 1134 insertions(+), 11 deletions(-) create mode 100644 arch/arm/cpu/arm1136/mx35/mx35_sdram.c create mode 100644 arch/arm/cpu/arm1136/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-mx35/mmc_host_def.h create mode 100644 arch/arm/include/asm/arch-mx35/spl.h create mode 100644 board/woodburn/Makefile create mode 100644 board/woodburn/imximage.cfg create mode 100644 board/woodburn/lowlevel_init.S create mode 100644 board/woodburn/woodburn.c create mode 100644 include/configs/woodburn.h create mode 100644 include/configs/woodburn_common.h create mode 100644 include/configs/woodburn_sd.h -- 1.7.9.5

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[U-Boot] [PATCH v2 1/2] cbfs: Remove mention of CREDITS files
by Simon Glass 07 Dec '12

07 Dec '12

As requested by Wolfgang, remove references to CREDITS in the CBFS files. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Add patch to remove mention of CREDITS in CBFS files fs/cbfs/Makefile | 4 +--- fs/cbfs/cbfs.c | 3 --- include/cbfs.h | 3 --- 3 files changed, 1 insertions(+), 9 deletions(-) diff --git a/fs/cbfs/Makefile b/fs/cbfs/Makefile index 2be8a68..e0e6de6 100644 --- a/fs/cbfs/Makefile +++ b/fs/cbfs/Makefile @@ -1,6 +1,4 @@ -# -# See file CREDITS for list of people who contributed to this -# project. +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c index cae6d56..1b25a15 100644 --- a/fs/cbfs/cbfs.c +++ b/fs/cbfs/cbfs.c @@ -1,9 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. * - * See file CREDITS for list of people who contributed to this - * project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of diff --git a/include/cbfs.h b/include/cbfs.h index 6ea3f35..8a780c2 100644 --- a/include/cbfs.h +++ b/include/cbfs.h @@ -1,9 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. All rights reserved. * - * See file CREDITS for list of people who contributed to this - * project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of -- 1.7.7.3

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[U-Boot] [PATCH 1/2] MAKEALL: Fix kill_children
by Joe Hershberger 07 Dec '12

07 Dec '12

When building in parallel, make sure that we look up the children based on the the actual process group id instead of just assuming that the MAKEALL pid is the process group id. Also ensure that logs from incomplete builds are deleted in the process. Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> --- MAKEALL | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/MAKEALL b/MAKEALL index 84a5c92..1f88dc5 100755 --- a/MAKEALL +++ b/MAKEALL @@ -610,6 +610,13 @@ list_target() { donep="${LOG_DIR}/._done_" skipp="${LOG_DIR}/._skip_" +build_target_killed() { + echo "Aborted $target build." + # Remove the logs for this board since it was aborted + rm -f ${LOG_DIR}/$target.MAKELOG ${LOG_DIR}/$target.ERR + exit +} + build_target() { target=$1 build_idx=$2 @@ -622,6 +629,7 @@ build_target() { if [ $BUILD_MANY == 1 ] ; then output_dir="${OUTPUT_PREFIX}/${target}" mkdir -p "${output_dir}" + trap build_target_killed TERM else output_dir="${OUTPUT_PREFIX}" fi @@ -640,6 +648,8 @@ build_target() { fi if [ $BUILD_MANY == 1 ] ; then + trap - TERM + ${MAKE} -s tidy if [ -s ${LOG_DIR}/${target}.ERR ] ; then @@ -721,7 +731,9 @@ build_targets() { if [ $BUILD_MANY == 1 ] ; then build_target ${t} ${TOTAL_CNT} & else + CUR_TGT="${t}" build_target ${t} ${TOTAL_CNT} + CUR_TGT='' fi fi @@ -745,7 +757,11 @@ build_targets() { #----------------------------------------------------------------------- kill_children() { - kill -- "-$1" + local pgid=`ps -p $$ --no-headers -o "%r" | tr -d ' '` + local children=`pgrep -g $pgid | grep -v $$ | grep -v $pgid` + + kill $children 2> /dev/null + wait $children 2> /dev/null exit } @@ -753,6 +769,9 @@ kill_children() { print_stats() { if [ "$ONLY_LIST" == 'y' ] ; then return ; fi + # Only count boards that completed + : $((TOTAL_CNT = `find ${skipp}* 2> /dev/null | wc -l`)) + rm -f ${donep}* ${skipp}* if [ $BUILD_MANY == 1 ] && [ -e "${OUTPUT_PREFIX}/ERR" ] ; then @@ -762,6 +781,9 @@ print_stats() { WRN_LIST=`grep -riwL error ${OUTPUT_PREFIX}/ERR/` WRN_LIST=`for f in $WRN_LIST ; do echo -n " $(basename $f)" ; done` WRN_CNT=`echo $WRN_LIST | wc -w | awk '{print $1}'` + else + # Remove the logs for any board that was interrupted + rm -f ${LOG_DIR}/${CUR_TGT}.MAKELOG ${LOG_DIR}/${CUR_TGT}.ERR fi echo "" @@ -776,7 +798,7 @@ print_stats() { echo "----------------------------------------------------------" if [ $BUILD_MANY == 1 ] ; then - kill_children $$ & + kill_children fi exit $RC -- 1.7.11.5

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