January 2012 - U-Boot

Re: [U-Boot] [PATCH v3] Input: keyboard - add device tree bindings for simple key matrixes
by Simon Glass 03 Jan '12

03 Jan '12

Hi Olof, On Sun, Jan 1, 2012 at 10:09 PM, Olof Johansson <olof(a)lixom.net> wrote: > This adds a simple device tree binding for simple key matrix data and > a helper to fill in the platform data. > > The implementation is in a shared file outside if drivers/input/keyboard > since some drivers in drivers/input/misc might be making use of it > as well. > > Changes since v2: > * Removed reference to "legacy" format with a subnode per key > * Changed to a packed format with one cell per key instead of 3. > * Moved new OF helper to separate file > * Misc fixups based on comments > > Changes since v1: > * Removed samsung-style binding support > * Added linux,fn-keymap and linux,fn-key optional properties > > Signed-off-by: Olof Johansson <olof(a)lixom.net> > --- > .../devicetree/bindings/input/matrix-keymap.txt | 27 ++++++ > drivers/input/Kconfig | 4 + > drivers/input/Makefile | 1 + > drivers/input/keyboard/Kconfig | 1 + > drivers/input/of_keymap.c | 87 ++++++++++++++++++++ > include/linux/input/matrix_keypad.h | 19 ++++ > 6 files changed, 139 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/input/matrix-keymap.txt > create mode 100644 drivers/input/of_keymap.c > > diff --git a/Documentation/devicetree/bindings/input/matrix-keymap.txt b/Documentation/devicetree/bindings/input/matrix-keymap.txt > new file mode 100644 > index 0000000..1db8e12 > --- /dev/null > +++ b/Documentation/devicetree/bindings/input/matrix-keymap.txt > @@ -0,0 +1,27 @@ > +A simple common binding for matrix-connected key boards. Currently targeted at > +defining the keys in the scope of linux key codes since that is a stable and > +standardized interface at this time. > + > +Required properties: > +- compatible: "matrix-keyboard-controller" > +- linux,keymap: an array of packed 1-cell entries containing the equivalent > + of row, column and linux key-code. The 32-bit big endian cell is packed > + as: > + row << 24 | column << 16 | key-code This looks much better than the Samsung binding and the original 3-cell one. U-Boot Tegra (keyboard patch series) currently uses a 16x8 matrix, and uses a single byte (the ASCII character) for a total of 128 bytes per keymap. Since U-Boot does not have (or apparently want) the concept of key codes or the added code and intermediate data this requires, the binding presented here will not suit U-Boot so far. These rows and columns embedded in the cell make it more of a pain to write the fdt description. If you just set up the cells in (column, row) order and set the matrix size (rows, columns) then you end up with 128 entries on Tegra. If you use uint16 then this could be 256 bytes instead of 512. The binding you present for Tegra would be 109 * 4 = 436 bytes. However I take your point that Fn maps are much more sparse, so overall this is likely to be similar (512 bytes for either method once Fn mappings are taken into account). But going back to U-Boot, it does not have the intermediate table that you malloc and decant into, it does not understand key codes so doesn't know what to do when Shift is pressed, doesn't understand languages, etc. In order to use these Linux bindings in U-Boot we would need to add new input layer, extra decode code and intermediate tables. I can almost hear the NAKs already (bear in mind fdt only went into U-Boot in the December release and people are more sensitive to code size / performance there than in Linux). I did ask about this on this list a few weeks ago but no response yet. We could perhaps add an alternative direct ASCII binding like this example (which would have to be in a separate node): /* Use a packed binding which doesn't include row,column numbers in each cell */ packed-binding; matrix-columns = <8>; matrix-rows = <16>; ascii-binding; /* ASCII characters instead of keycodes */ u-boot,keymap = /size/ 8 <00 00 'w' 's' 'a' 'z' 00 DE 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 '5' '4' 'r' 'e' 'f' 'd' 'x' 00 '7' '6' 't' 'h' 'g' 'v' 'c' ' ' '9' '8' 'u' 'y' 'j' 'n' 'b' 5C '-' '0' 'o' 'i' 'l' 'k' ',' 'm' 00 '=' ']' 0D 00 00 00 00 00 00 00 00 DF DF 00 00 00 00 00 00 00 DC 00 DD 00 00 00 00 00 00 00 00 '[' 'p' 27 ';' '/' '.' 00 00 00 00 08 '3' '2' 1E 00 00 00 7F 00 00 00 1D 1F 1C 00 00 00 'q' 00 00 '1' 00 1B '`' 00 09 00 00 00 00>; u-boot,keymap-DF = /size/ 8 <00 00 'W' 'S' 'A' 'Z' 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... The DC-DF codes codes denote Shift, Fn and Ctrl keys which would need a separate keymap - although we could probably calculate the Ctrl one. >From a point of view of efficiency, drivers can simply keep a pointer to the appropriate property and read out the codes based on (row,column) position. If we have something like this, then in order for the keyboard to work in U-Boot, vendors would need to create a completely separate ASCII mapping. Yes I agree this is a bit of a pain, but the above map is fairly easy to type in, and quite compact. Given the push-back on the U-Boot list from Linux people about my bindings, I would like to work out the U-Boot side in this thread if possible, since it seems to be dependent on what Linux does. But I hope what is created is efficient enough not to bloat U-Boot or require an new input layer to be added just to use fdt. Regards, Simon > + > +Optional properties: > +- linux,fn-keymap: A separate array of packed 1-cell entries similar to > + linux,keymap but only to be used when the function key modifier is > + active. This is used for keyboards that have a software-based modifier > + key for 'Fn' but that need to describe the custom layout that should > + be used when said modifier key is active. > + > +- linux,fn-key: a 2-cell entry containing the < row column > of the > + function modifier key used to switch to the above linux,fn-keymap > + layout. > + > +Example: > + linux,keymap = < 0x00030012 > + 0x0102003a >; > + linux,fn-key = < 2 1 >; > + linux,fn-keymap = < 0x0002004a >; [snip] Regards, Simon

4 7

[U-Boot] 4k page ONFI NAND
by Vipin Kumar 03 Jan '12

03 Jan '12

Hello, We have a Micron 4K page sized ONFI NAND MT29F16G08 I am encountering frequent errors while reading the device. Although the data area is protected for 8bit correction with BCH8 algorithm, the oob area is unprotected and is susceptible to bit flips These errors are very frequent and it results in jffs2 file system mounting problems and other related issues I also confirmed the problem through oobtest module. Can you please suggest any solutions/workaround Regards Vipin

2 1

[U-Boot] U-boot doesn't work on OMAP4430 ES2.0
by Raúl Porcel 03 Jan '12

03 Jan '12

Hi, Following with the issue on http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/111922 Looks like the 23e9f0723e48615332119de4f4ec7a833a282628 commit was supposed to fix this, but it doesn't, the problem is still present. Steve Sakoman's git tree has a different patch: http://www.sakoman.com/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=edb61… Indeed applying the patch in his tree makes it work. After talking with him he guessed that maybe the fix was supposed to touch efuse_2 and not efuse_1 like in the original patch. Thanks

5 8

[U-Boot] [PATCH] beagle: add eeprom expansion board info for bct brettl3
by Peter Meerwald 03 Jan '12

03 Jan '12

From: Peter Meerwald <p.meerwald(a)bct-electronic.com> this is for a prototyping board vendor/product ids have been added to http://elinux.org/BeagleBoardPinMux#List_of_Vendor_and_Device_IDs --- board/ti/beagle/beagle.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6a457cb..5c04b34 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -71,6 +71,7 @@ extern volatile struct ehci_hcor *hcor; #define BBTOYS_WIFI 0x01000B00 #define BBTOYS_VGA 0x02000B00 #define BBTOYS_LCD 0x03000B00 +#define BCT_BRETTL3 0x01000F00 #define BEAGLE_NO_EEPROM 0xffffffff DECLARE_GLOBAL_DATA_PTR; @@ -379,6 +380,9 @@ int misc_init_r(void) case BBTOYS_LCD: printf("Recognized BeagleBoardToys LCD board\n"); break;; + case BCT_BRETTL3: + printf("Recognized bct electronic GmbH brettl3 board\n"); + break; case BEAGLE_NO_EEPROM: printf("No EEPROM on expansion board\n"); setenv("buddy", "none"); -- 1.7.4.1

2 1

[U-Boot] [PATCH 1/1] ARMV7: Add support For Logic OMAP35x/DM37x modules
by Peter Barada 03 Jan '12

03 Jan '12

From: Peter Barada <peterb(a)logicpd.com> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo reference boards. It assumes U-boot is loaded to SDRAM with the help of another small bootloader (x-load) running from SRAM. Signed-off-by: Peter Barada <peter.barada(a)logicpd.com> --- board/logicpd/omap3som/Makefile | 48 +++ board/logicpd/omap3som/config.mk | 33 ++ board/logicpd/omap3som/omap3logic.c | 566 +++++++++++++++++++++++++++++++++++ board/logicpd/omap3som/omap3logic.h | 35 +++ boards.cfg | 1 + include/configs/omap3_logic.h | 356 ++++++++++++++++++++++ 6 files changed, 1039 insertions(+), 0 deletions(-) create mode 100644 board/logicpd/omap3som/Makefile create mode 100644 board/logicpd/omap3som/config.mk create mode 100644 board/logicpd/omap3som/omap3logic.c create mode 100644 board/logicpd/omap3som/omap3logic.h create mode 100644 include/configs/omap3_logic.h diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile new file mode 100644 index 0000000..ef0409f --- /dev/null +++ b/board/logicpd/omap3som/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := omap3logic.o + +COBJS := $(sort $(COBJS-y)) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/logicpd/omap3som/config.mk b/board/logicpd/omap3som/config.mk new file mode 100644 index 0000000..897b252 --- /dev/null +++ b/board/logicpd/omap3som/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006 - 2008 +# Texas Instruments, <www.ti.com> +# +# EVM uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +CONFIG_SYS_TEXT_BASE = 0x80400000 diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c new file mode 100644 index 0000000..5c6e896 --- /dev/null +++ b/board/logicpd/omap3som/omap3logic.c @@ -0,0 +1,566 @@ +/* + * (C) Copyright 2011 + * Logic Product Development <www.logicpd.com> + * + * Author : + * Peter Barada <peter.barada(a)logicpd.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <netdev.h> +#include <flash.h> +#include <nand.h> +#include <i2c.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-types.h> +#include "omap3logic.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* Mux hsusb0_data5 as gpio_189 */ +#define MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX() \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4)) + +/* Mux hsusb0_data5 as hasusb0_data5 */ +#define MUX_LOGIC_HSUSB0_DATA5_DATA5() \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) + +/* + * Routine: logic_identify + * Description: Detect if we are running on a Logic or Torpedo. + * This can be done by GPIO_189. If its low after driving it high, + * then its a SOM LV, else Torpedo. + */ +unsigned int logic_identify(void) +{ + unsigned int val = 0; + u32 cpu_family = get_cpu_family(); + int i; + + MUX_LOGIC_HSUSB0_DATA5_GPIO_MUX(); + + if (!gpio_request(189, "")) { + + gpio_direction_output(189, 0); + gpio_set_value(189, 1); + + /* Let it soak for a bit */ + for (i = 0; i < 0x100; ++i) + asm("nop"); + + gpio_direction_input(189); + val = gpio_get_value(189); + gpio_free(189); + + printf("Board:"); + if (cpu_family == CPU_OMAP36XX) { + printf(" DM37xx"); + if (val) { + printf(" Torpedo\n"); + val = MACH_TYPE_DM3730_TORPEDO; + } else { + printf(" SOM LV\n"); + val = MACH_TYPE_DM3730_SOM_LV; + } + } else { + printf(" OMAP35xx"); + if (val) { + printf(" Torpedo\n"); + val = MACH_TYPE_OMAP3_TORPEDO; + } else { + printf(" SOM LV\n"); + val = MACH_TYPE_OMAP3530_LV_SOM; + } + } + } + + MUX_LOGIC_HSUSB0_DATA5_DATA5(); + + return val; +} + +/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ +#define LOGIC_NET_GPMC_CONFIG1 0x00001000 +#define LOGIC_NET_GPMC_CONFIG2 0x00080801 +#define LOGIC_NET_GPMC_CONFIG3 0x00000000 +#define LOGIC_NET_GPMC_CONFIG4 0x08010801 +#define LOGIC_NET_GPMC_CONFIG5 0x00080a0a +#define LOGIC_NET_GPMC_CONFIG6 0x03000280 +#define LOGIC_NET_GPMC_CONFIG7 0x00000848 + +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + /* Configure GPMC registers */ + writel(LOGIC_NET_GPMC_CONFIG1, &gpmc_cfg->cs[1].config1); + writel(LOGIC_NET_GPMC_CONFIG2, &gpmc_cfg->cs[1].config2); + writel(LOGIC_NET_GPMC_CONFIG3, &gpmc_cfg->cs[1].config3); + writel(LOGIC_NET_GPMC_CONFIG4, &gpmc_cfg->cs[1].config4); + writel(LOGIC_NET_GPMC_CONFIG5, &gpmc_cfg->cs[1].config5); + writel(LOGIC_NET_GPMC_CONFIG6, &gpmc_cfg->cs[1].config6); + writel(LOGIC_NET_GPMC_CONFIG7, &gpmc_cfg->cs[1].config7); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + +} + + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + /* board id for Linux */ + gd->bd->bi_arch_number = logic_identify(); + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + + return 0; +} + +int board_late_init(void) +{ + unsigned char enetaddr[6]; + +#ifdef CONFIG_CMD_CACHE + dcache_enable(); + printf("Data (writethrough) Cache is %s\n", + dcache_status() ? "ON" : "OFF"); +#endif + return 0; +} + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + +/* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + */ +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif + + dieid_num_r(); + + return 0; +} + + + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + + + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + /*SDRC*/ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); + /*GPMC*/ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4)); + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M7)); /*safe mode */ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/ + MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M7)); /*safe mode */ + /*DSS*/ + MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA2), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA3), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA4), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA5), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)); /*safe mode */ + /*CAMERA*/ + MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M7)); /*safe mode */ + /*Audio Interface */ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M7)); /*safe mode */ + + /*Expansion card */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/ + /*Wireless LAN */ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/ + /*Bluetooth*/ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M7)); /*safe mode*/ + /*Modem Interface */ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | EN | M7)); /*safe mode*/ + + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/ + /*Serial Interface*/ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(UART3_TX_IRTX), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_STP), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); + + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M7)); /*safe mode*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M7)); /*safe mode*/ + /*Control and debug */ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | EN | M7)); /*safe mode */ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)); + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); + /*Die to Die */ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*safe mode*/ +} diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h new file mode 100644 index 0000000..5b2ca66 --- /dev/null +++ b/board/logicpd/omap3som/omap3logic.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2011 + * Logic Product Development <www.logicpd.com> + * + * Author: + * Peter Barada <peter.barada(a)logicpd.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP3LOGIC_H_ +#define _OMAP3LOGIC_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "Logic DM37x/OMAP35x reference board", + "NAND", +}; + +#endif diff --git a/boards.cfg b/boards.cfg index 1e5b3e0..f07ae28 100644 --- a/boards.cfg +++ b/boards.cfg @@ -202,6 +202,7 @@ igep0030 arm armv7 igep0030 isee am3517_evm arm armv7 am3517evm logicpd omap3 omap3_zoom1 arm armv7 zoom1 logicpd omap3 omap3_zoom2 arm armv7 zoom2 logicpd omap3 +omap3_logic arm armv7 omap3som logicpd omap3 omap3_mvblx arm armv7 mvblx matrix_vision omap3 am3517_crane arm armv7 am3517crane ti omap3 omap3_beagle arm armv7 beagle ti omap3 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h new file mode 100644 index 0000000..3c7c821 --- /dev/null +++ b/include/configs/omap3_logic.h @@ -0,0 +1,356 @@ +/* + * (C) Copyright 2011 Logic Product Development <www.logicpd.com> + * Peter Barada <peter.barada(a)logicpd.com> + * + * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo + * reference boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 35x/37x */ +#define CONFIG_OMAP3_LOGIC 1 /* working with Logic OMAP boards */ + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R /* misc_init_r sets up SMSC911x and + * dumps the die id */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +#define CONFIG_CMDLINE_EDITING 1 /* cmd line edit/history */ +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 /* check keypress w/no delay */ + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_MMC 1 +#define CONFIG_OMAP_HSMMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETECPR /* Evaluate expressions */ + +#define CONFIG_L2_OFF 1 /* Keep L2 Cache Disabled */ + +#define BOARD_LATE_INIT + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER 1 + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST 1 +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 2 + +#define CONFIG_PREBOOT \ + "echo ======================NOTICE============================;"\ + "echo The u-boot environment is not set. - You are;" \ + "echo required to set a valid display for your LCD panel.;" \ + "echo Valid display options are:;" \ + "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \ + "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \ + "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \ + "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \ + "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \ + "echo \" vga[-16 OR -24] LCD VGA 640x480\";" \ + "echo \" svga[-16 OR -24] LCD SVGA 800x600\";" \ + "echo \" xga[-16 OR -24] LCD XGA 1024x768\";" \ + "echo \" 720p[-16 OR -24] LCD 720P 1280x720\";" \ + "echo \" sxga[-16 OR -24] LCD SXGA 1280x1024\";" \ + "echo \" uxga[-16 OR -24] LCD UXGA 1600x1200\";" \ + "echo MAKE SURE YOUR DISPLAY VARIABLE IS CORRECTLY ENTERED!;" \ + "setenv display 15;" \ + "setenv preboot;" \ + "saveenv;" + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x81000000\0" \ + "bootfile=uImage\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "mmcdev=0\0" \ + "autoboot=if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "run defaultboot;" \ + "fi; " \ + "else run defaultboot; fi\0" \ + "defaultboot=run mmcramboot\0" \ + "consoledevice=ttyO0\0" \ + "display=15\0" \ + "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \ + "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \ + "rotation=0\0" \ + "vrfb_arg=if itest ${rotation} -ne 0; then " \ + "setenv bootargs ${bootargs} omapfb.vrfb=y " \ + "omapfb.rotate=${rotation}; " \ + "fi\0" \ + "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \ + "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "common_bootargs=setenv bootargs ${bootargs} display=${display} " \ + "${otherbootargs};" \ + "run addmtdparts; " \ + "run vrfb_arg\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo 'Running bootscript from mmc ...'; " \ + "source ${loadaddr}\0" \ + "loaduimage=mmc rescan ${mmcdev}; " \ + "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "ramdisksize=64000\0" \ + "ramdiskaddr=0x82000000\0" \ + "ramdiskimage=rootfs.ext2.gz.uboot\0" \ + "ramargs=run setconsole; setenv bootargs console=${console} " \ + "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \ + "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \ + "run ramargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "run loaduimage; " \ + "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\ + "bootm ${loadaddr} ${ramdiskaddr}\0" + +#define CONFIG_BOOTCOMMAND \ + "run autoboot" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "OMAP Logic # " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#elif defined(CONFIG_CMD_ONENAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#endif + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#endif + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/*---------------------------------------------------------------------------- + * SMSC9115 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- + */ +#if defined(CONFIG_CMD_NET) + +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X +#define CONFIG_SMC911X_16_BIT +#define CONFIG_SMC911X_BASE 0x08000000 + +#endif /* (CONFIG_CMD_NET) */ + +/* + * BOOTP fields + */ + +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 + +#endif /* __CONFIG_H */ -- 1.7.1

4 20

[U-Boot] [PATCH] arm, davinci: Change byte order of RTC kick register values
by Christian Riesch 03 Jan '12

03 Jan '12

Now the values in the defines agree with those in the manuals. Signed-off-by: Christian Riesch <christian.riesch(a)omicron.at> Cc: Tom Rini <trini(a)ti.com> Cc: Heiko Schocher <hs(a)denx.de> --- arch/arm/include/asm/arch-davinci/hardware.h | 4 ++-- board/enbw/enbw_cmc/enbw_cmc.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index dd89e84..1c71540 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -622,8 +622,8 @@ struct davinci_rtc { #define RTC_STATE_BUSY 0x01 #define RTC_STATE_RUN 0x02 -#define RTC_KICK0R_WE 0x130be783 -#define RTC_KICK1R_WE 0xe0f1a495 +#define RTC_KICK0R_WE 0x83e70b13 +#define RTC_KICK1R_WE 0x95a4f1e0 #define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 5cd5357..98dda1e 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -526,8 +526,8 @@ void bootcount_store(ulong a) * for RTC Scratch registers. Cratch0 and 1 are * used for bootcount values. */ - out_be32(&reg->kick0r, RTC_KICK0R_WE); - out_be32(&reg->kick1r, RTC_KICK1R_WE); + writel(RTC_KICK0R_WE, &reg->kick0r); + writel(RTC_KICK1R_WE, &reg->kick1r); out_be32(&reg->scratch0, a); out_be32(&reg->scratch1, BOOTCOUNT_MAGIC); } -- 1.7.0.4

2 1

[U-Boot] [PATCH resend] OMAP3: Remove unused define CONFIG_OMAP3_*_DDR
by Thomas Weber 03 Jan '12

03 Jan '12

This patch removes the unused definitions: CONFIG_OMAP3_MICRON_DDR CONFIG_OMAP3_NUMONYX_DDR CONFIG_OMAP3_INFINEON_DDR Acked-by: Igor Grinberg <grinberg(a)compulab.co.il> Acked-by: Luca Ceresoli <luca.ceresoli(a)comelit.it> Signed-off-by: Thomas Weber <weber(a)corscience.de> --- Changes: Added received acked-by's include/configs/cm_t35.h | 3 --- include/configs/dig297.h | 3 --- include/configs/igep0020.h | 3 --- include/configs/igep0030.h | 3 --- include/configs/omap3_mvblx.h | 3 --- include/configs/omap3_overo.h | 3 --- include/configs/omap3_pandora.h | 3 --- include/configs/omap3_sdp3430.h | 3 --- include/configs/omap3_zoom1.h | 3 --- include/configs/omap3_zoom2.h | 3 --- 10 files changed, 0 insertions(+), 30 deletions(-) diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index a06a89d..0385ee8 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -112,9 +112,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 42aab27..1626b0e 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -109,9 +109,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR - /* library portions to compile in */ #define CONFIG_RBTREE #define CONFIG_MTD_PARTITIONS diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h index 56fd6de..c2fcdff 100644 --- a/include/configs/igep0020.h +++ b/include/configs/igep0020.h @@ -78,9 +78,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR */ -#define CONFIG_OMAP3_NUMONYX_DDR 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h index 3634618..bf39ba5 100644 --- a/include/configs/igep0030.h +++ b/include/configs/igep0030.h @@ -78,9 +78,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR */ -#define CONFIG_OMAP3_NUMONYX_DDR 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index eb51ea9..a5746d1 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -102,9 +102,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 79eb466..db453ac 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -90,9 +90,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* commands to include */ #include <config_cmd_default.h> diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 1a30454..4df5f5d 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -104,9 +104,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* commands to include */ #include <config_cmd_default.h> diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 90f4b90..404aed2 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -137,9 +137,6 @@ #define CONFIG_SYS_I2C_BUS_SELECT 1 #define CONFIG_DRIVER_OMAP34XX_I2C 1 -/* DDR - I use Infineon DDR */ -#define CONFIG_OMAP3_INFINEON_DDR 1 - /* OMITTED: single 1 Gbit MT29F1G NAND flash */ /* diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index b0e10c7..17608f5 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -99,9 +99,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 8a37ebf..b60ece3 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -99,9 +99,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* Status LED */ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED 1 -- 1.7.8.1

2 1

[U-Boot] [PATCH v3 0/3] Added SPL support
by Chandan Nath 03 Jan '12

03 Jan '12

This patch series is submitted to add support for MMC/SD along with SPL support. Also, fixed incorrect register offset of ddr and timer registers. The patches have been compile tested and run on AM335X EVM. The patches depends on previous patch series which was submitted for supporting AM33xx platform. The patches are applies on uboot master branch. Changes since v2: - Added missing omap.h file in "Add SPL support for AM335X EVM" patch Changes since v1: - Removed unwanted code from omap_hsmmc.c file - Changed CONFIG_AM335X to CONFIG_AM33XX - Rebased to master branch - Replaced am33xx lowleve_init.S with omap-common lowlevel_init.S in order to use common code for omap_bootmode. Chandan Nath (3): ARM:AM33XX: Fix ddr and timer register offset ARM:AM33XX: Add mmc/sd support ARM:AM33XX: Add SPL support for AM335X EVM Makefile | 2 +- arch/arm/cpu/armv7/am33xx/Makefile | 2 - arch/arm/cpu/armv7/am33xx/board.c | 80 ++++++++++- arch/arm/cpu/armv7/am33xx/clock.c | 8 + arch/arm/cpu/armv7/am33xx/config.mk | 18 +++ arch/arm/cpu/armv7/am33xx/emif4.c | 2 +- arch/arm/cpu/armv7/am33xx/lowlevel_init.S | 72 ---------- arch/arm/cpu/armv7/omap-common/Makefile | 3 + arch/arm/include/asm/arch-am33xx/common_def.h | 22 +++ arch/arm/include/asm/arch-am33xx/cpu.h | 44 +++--- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 6 +- arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 164 +++++++++++++++++++++++ arch/arm/include/asm/arch-am33xx/omap.h | 59 ++++++++ arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + arch/arm/include/asm/omap_common.h | 5 + board/ti/am335x/common_def.h | 24 ---- board/ti/am335x/evm.c | 2 +- board/ti/am335x/mux.c | 22 +++- include/configs/am335x_evm.h | 61 +++++++-- spl/Makefile | 13 +- 20 files changed, 457 insertions(+), 153 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/config.mk delete mode 100644 arch/arm/cpu/armv7/am33xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-am33xx/common_def.h create mode 100644 arch/arm/include/asm/arch-am33xx/mmc_host_def.h create mode 100644 arch/arm/include/asm/arch-am33xx/omap.h delete mode 100644 board/ti/am335x/common_def.h

5 12

[U-Boot] [PATCH] arm/omap3: limit chip select iteration based on board config
by Grant Erickson 03 Jan '12

03 Jan '12

Only attempt to configure and add DRAM at chip select 1 if the board has configured more than one bank of DRAM. This prevents boards that have CONFIG_NR_DRAM_BANKS set to 1 from getting an incorrect DRAM size. Signed-off-by: Grant Erickson <marathon96(a)gmail.com> Cc: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/armv7/omap3/sdrc.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index a27b4b1..4c02214 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -213,6 +213,7 @@ int dram_init(void) unsigned int size0 = 0, size1 = 0; size0 = get_sdr_cs_size(CS0); +#if CONFIG_NR_DRAM_BANKS > 1 /* * We always need to have cs_cfg point at where the second * bank would be, if present. Failure to do so can lead to @@ -223,6 +224,7 @@ int dram_init(void) make_cs1_contiguous(); do_sdrc_init(CS1, NOT_EARLY); size1 = get_sdr_cs_size(CS1); +#endif gd->ram_size = size0 + size1; -- 1.7.7.3

2 1

[U-Boot] [PATCH] kirkwood_spi: fix setting of irq mask
by Michael Walle 02 Jan '12

02 Jan '12

Since the data alignment fault was enabled recently in commit arm, arm926ejs: always do cpu critical inits the driver won't work anymore and all boards which use an environment in an SPI flash will fail booting. Signed-off-by: Michael Walle <michael(a)walle.cc> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Prafulla Wadaskar <prafulla(a)marvell.com> --- drivers/spi/kirkwood_spi.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index a50e498..9aaecfe 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -67,7 +67,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, debug("data = 0x%08x \n", data); writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause); - writel(KWSPI_IRQMASK, spireg->irq_mask); + writel(KWSPI_IRQMASK, &spireg->irq_mask); /* program mpp registers to select SPI_CSn */ if (cs) { -- 1.7.2.5

2 3