August 2011 - U-Boot

[U-Boot] [PATCH 1/6] PXA: Fix Lubbock, remove redundant parenthesis
by Marek Vasut 31 Oct '11

31 Oct '11

Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- board/lubbock/flash.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) NOTE: Albert, I'll get you these four PXA-related in a PULL RQ later. diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c index 1ea2893..e1e7807 100644 --- a/board/lubbock/flash.c +++ b/board/lubbock/flash.c @@ -408,7 +408,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } -- 1.7.5.4

3 10

[U-Boot] [PATCH v4 0/6] Add Highbank platform
by Rob Herring 24 Oct '11

24 Oct '11

From: Rob Herring <rob.herring(a)calxeda.com> This series enables non-PCI AHCI controllers and adds support for Calxeda Highbank platform which uses the AHCI changes. Changes from v3: - Added Highbank to MAINTAINERS - Added back patch to fix CONFIG_SKIP_LOWLEVEL_INIT (mistakenly dropped from v2) Wolfgang, Albert, Can you apply these to your trees for v2011.09? All review comments have been addressed. Rob Rob Herring (6): ARM: add missing CONFIG_SKIP_LOWLEVEL_INIT for armv7 ARM: Add Calxeda Highbank platform arm: add __ilog2 function scsi/ahci: ata id little endian fix scsi/ahci: add support for non-PCI controllers ARM: highbank: Add AHCI support MAINTAINERS | 4 + arch/arm/cpu/armv7/highbank/Makefile | 46 ++++++++++++ arch/arm/cpu/armv7/highbank/config.mk | 4 + arch/arm/cpu/armv7/highbank/timer.c | 124 +++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/start.S | 2 + arch/arm/include/asm/bitops.h | 9 +++ board/highbank/Makefile | 49 +++++++++++++ board/highbank/highbank.c | 58 +++++++++++++++ boards.cfg | 1 + common/cmd_scsi.c | 6 +- drivers/block/ahci.c | 72 ++++++++++++++++--- include/ahci.h | 4 + include/configs/highbank.h | 112 +++++++++++++++++++++++++++++ include/scsi.h | 1 + 14 files changed, 480 insertions(+), 12 deletions(-) create mode 100644 arch/arm/cpu/armv7/highbank/Makefile create mode 100644 arch/arm/cpu/armv7/highbank/config.mk create mode 100644 arch/arm/cpu/armv7/highbank/timer.c create mode 100644 board/highbank/Makefile create mode 100644 board/highbank/highbank.c create mode 100644 include/configs/highbank.h -- 1.7.4.1

5 41

[U-Boot] [PATCH v7 01/10] nds32: add header files support for nds32
by Macpaul Lin 22 Oct '11

22 Oct '11

Add generic header files support for nds32 architecture. Cache, ptregs, data type and other definitions are included. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Changes for v1-v4: - Code cleanup and style formatting. Changes for v5-v6: - This patch also updated the following changes against the change after master tree (v2010.12-rc1). - fix upper case definitions in cache.h - Support GD_FLG_ENV_READY and env_buf vars in nds32 global_data.h. - Add readsb, writesb functions into io.h. Changes for v7: - clean up - volatile: - types.h - remove typedef volatile unsigned char vuchar; - remove typedef volatile unsigned long vulong; - remove typedef volatile unsigned short vushort; - u-boot.h: remove bd_info_ext bi_ext - bitops.h: add accessor function to bit operation with volatile var. - system.h: add system.h for local_irq operation with flag. arch/nds32/include/asm/bitops.h | 186 +++++++++++++++ arch/nds32/include/asm/byteorder.h | 36 +++ arch/nds32/include/asm/cache.h | 54 +++++ arch/nds32/include/asm/config.h | 26 ++ arch/nds32/include/asm/global_data.h | 82 +++++++ arch/nds32/include/asm/io.h | 410 +++++++++++++++++++++++++++++++++ arch/nds32/include/asm/mach-types.h | 29 +++ arch/nds32/include/asm/memory.h | 19 ++ arch/nds32/include/asm/posix_types.h | 84 +++++++ arch/nds32/include/asm/processor.h | 25 ++ arch/nds32/include/asm/ptrace.h | 22 ++ arch/nds32/include/asm/ptregs.h | 81 +++++++ arch/nds32/include/asm/string.h | 57 +++++ arch/nds32/include/asm/system.h | 88 +++++++ arch/nds32/include/asm/types.h | 63 +++++ arch/nds32/include/asm/u-boot-nds32.h | 50 ++++ arch/nds32/include/asm/u-boot.h | 63 +++++ arch/nds32/include/asm/unaligned.h | 31 +++ 18 files changed, 1406 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/include/asm/bitops.h create mode 100644 arch/nds32/include/asm/byteorder.h create mode 100644 arch/nds32/include/asm/cache.h create mode 100644 arch/nds32/include/asm/config.h create mode 100644 arch/nds32/include/asm/global_data.h create mode 100644 arch/nds32/include/asm/io.h create mode 100644 arch/nds32/include/asm/mach-types.h create mode 100644 arch/nds32/include/asm/memory.h create mode 100644 arch/nds32/include/asm/posix_types.h create mode 100644 arch/nds32/include/asm/processor.h create mode 100644 arch/nds32/include/asm/ptrace.h create mode 100644 arch/nds32/include/asm/ptregs.h create mode 100644 arch/nds32/include/asm/string.h create mode 100644 arch/nds32/include/asm/system.h create mode 100644 arch/nds32/include/asm/types.h create mode 100644 arch/nds32/include/asm/u-boot-nds32.h create mode 100644 arch/nds32/include/asm/u-boot.h create mode 100644 arch/nds32/include/asm/unaligned.h diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h new file mode 100644 index 0000000..c56f04b --- /dev/null +++ b/arch/nds32/include/asm/bitops.h @@ -0,0 +1,186 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro(a)andestech.com> + * + * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). + * + * Please note that the code in this file should never be included + * from user space. Many of these are not implemented in assembler + * since they would be too costly. Also, they require priviledged + * instructions (which are not available from user mode) to ensure + * that they are atomic. + */ + +#ifndef __ASM_NDS_BITOPS_H +#define __ASM_NDS_BITOPS_H + +#ifdef __KERNEL__ + +#include <asm/system.h> + +#define smp_mb__before_clear_bit() do { } while (0) +#define smp_mb__after_clear_bit() do { } while (0) + +/* + * Function prototypes to keep gcc -Wall happy. + */ +extern void set_bit(int nr, volatile void *addr); + +static inline void __set_bit(int nr, volatile void *addr) +{ + int *a = (int *)addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +extern void clear_bit(int nr, volatile void *addr); + +static inline void __clear_bit(int nr, volatile void *addr) +{ + int *a = (int *)addr; + int mask; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a &= ~mask; + local_irq_restore(flags); +} + +extern void change_bit(int nr, volatile void *addr); + +static inline void __change_bit(int nr, volatile void *addr) +{ + int mask; + unsigned long *ADDR = (unsigned long *)addr; + + ADDR += nr >> 5; + mask = 1 << (nr & 31); + *ADDR ^= mask; +} + +extern int test_and_set_bit(int nr, volatile void *addr); + +static inline int __test_and_set_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + return retval; +} + +extern int test_and_clear_bit(int nr, volatile void *addr); + +static inline int __test_and_clear_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + return retval; +} + +extern int test_and_change_bit(int nr, volatile void *addr); + +static inline int __test_and_change_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = (volatile unsigned int *)addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + return retval; +} + +extern int find_first_zero_bit(void *addr, unsigned size); +extern int find_next_zero_bit(void *addr, int size, int offset); + +/* + * This routine doesn't need to be atomic. + */ +static inline int test_bit(int nr, const void *addr) +{ + return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); +} + +/* + * ffz = Find First Zero in word. Undefined if no zero exists, + * so code should check against ~0UL first.. + */ +static inline unsigned long ffz(unsigned long word) +{ + int k; + + word = ~word; + k = 31; + if (word & 0x0000ffff) { + k -= 16; word <<= 16; + } + if (word & 0x00ff0000) { + k -= 8; word <<= 8; + } + if (word & 0x0f000000) { + k -= 4; word <<= 4; + } + if (word & 0x30000000) { + k -= 2; word <<= 2; + } + if (word & 0x40000000) + k -= 1; + + return k; +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +/* + * redefined in include/linux/bitops.h + * #define ffs(x) generic_ffs(x) + */ + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +#define ext2_set_bit test_and_set_bit +#define ext2_clear_bit test_and_clear_bit +#define ext2_test_bit test_bit +#define ext2_find_first_zero_bit find_first_zero_bit +#define ext2_find_next_zero_bit find_next_zero_bit + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr, addr) test_and_set_bit(nr, addr) +#define minix_set_bit(nr, addr) set_bit(nr, addr) +#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr) +#define minix_test_bit(nr, addr) test_bit(nr, addr) +#define minix_find_first_zero_bit(addr, size) find_first_zero_bit(addr, size) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_NDS_BITOPS_H */ diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h new file mode 100644 index 0000000..39fd9ed --- /dev/null +++ b/arch/nds32/include/asm/byteorder.h @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/byteorder.h + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro(a)andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul(a)andestech.com> + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ + +#ifndef __ASM_NDS_BYTEORDER_H +#define __ASM_NDS_BYTEORDER_H + +#include <asm/types.h> + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __NDSEB__ +#include <linux/byteorder/big_endian.h> +#else +#include <linux/byteorder/little_endian.h> +#endif + +#endif diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h new file mode 100644 index 0000000..d769196 --- /dev/null +++ b/arch/nds32/include/asm/cache.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro(a)andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul(a)andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CACHE_H +#define _ASM_CACHE_H + +/* cache */ +int icache_status(void); +void icache_enable(void); +void icache_disable(void); +int dcache_status(void); +void dcache_enable(void); +void dcache_disable(void); + +#define DEFINE_GET_SYS_REG(reg) \ + static inline unsigned long GET_##reg(void) \ + { \ + unsigned long val; \ + __asm__ volatile ( \ + "mfsr %0, $"#reg : "=&r" (val) : : "memory" \ + ); \ + return val; \ + } + +enum cache_t {ICACHE, DCACHE}; +DEFINE_GET_SYS_REG(ICM_CFG); +DEFINE_GET_SYS_REG(DCM_CFG); +#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ +#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) +#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ +#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) + +#endif /* _ASM_CACHE_H */ diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h new file mode 100644 index 0000000..23421b7 --- /dev/null +++ b/arch/nds32/include/asm/config.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro(a)andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h new file mode 100644 index 0000000..a3e5b4c --- /dev/null +++ b/arch/nds32/include/asm/global_data.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro(a)andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul(a)andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - so far no one uses the macros defined in this head file. + **************************************************************/ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CONFIG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long fb_base; /* base address of frame buffer */ +#ifdef CONFIG_VFD + unsigned char vfd_type; /* display type */ +#endif + void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ + +#ifdef CONFIG_GLOBAL_DATA_NOT_REG8 +extern volatile gd_t g_gd; +#define DECLARE_GLOBAL_DATA_PTR static volatile gd_t *gd = &g_gd +#else +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("$r8") +#endif + +#endif /* __ASM_GBL_DATA_H */ diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h new file mode 100644 index 0000000..be097ec --- /dev/null +++ b/arch/nds32/include/asm/io.h @@ -0,0 +1,410 @@ +/* + * linux/include/asm-nds/io.h + * + * Copyright (C) 1996-2000 Russell King + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro(a)andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_NDS_IO_H +#define __ASM_NDS_IO_H + +/* + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc... + * iinclude asm/io.h + */ + +#ifdef __KERNEL__ + +#include <linux/types.h> +#include <asm/byteorder.h> +#include <asm/memory.h> + +static inline void sync(void) +{ +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +static inline phys_addr_t virt_to_phys(void *vaddr) +{ + return (phys_addr_t)(vaddr); +} + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v)) + +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v, a) __arch_putb(v, a) +#define __raw_writew(v, a) __arch_putw(v, a) +#define __raw_writel(v, a) __arch_putl(v, a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) + +#define writeb(v, a) __arch_putb(v, a) +#define writew(v, a) __arch_putw(v, a) +#define writel(v, a) __arch_putl(v, a) + +#define readb(a) __arch_getb(a) +#define readw(a) __arch_getw(a) +#define readl(a) __arch_getl(a) + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off) +#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off) +#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off) + +#define __raw_base_readb(base, off) __arch_base_getb(base, off) +#define __raw_base_readw(base, off) __arch_base_getw(base, off) +#define __raw_base_readl(base, off) __arch_base_getl(base, off) + +/* + * Now, pick up the machine-defined IO definitions + * #include <asm/arch/io.h> + */ + +/* + * IO port access primitives + * ------------------------- + * + * The NDS32 doesn't have special IO access instructions just like ARM; + * all IO is memory mapped. + * Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * Note that for a big endian machine, this implies that the following + * big endian mode connectivity is in place, as described by numerious + * ARM documents: + * + * PCI: D0-D7 D8-D15 D16-D23 D24-D31 + * ARM: D24-D31 D16-D23 D8-D15 D0-D7 + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#ifdef __io +#define outb(v, p) __raw_writeb(v, __io(p)) +#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p)) +#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p, d, l) writesb(__io(p), d, l) +#define outsw(p, d, l) writesw(__io(p), d, l) +#define outsl(p, d, l) writesl(__io(p), d, l) + +#define insb(p, d, l) readsb(__io(p), d, l) +#define insw(p, d, l) readsw(__io(p), d, l) +#define insl(p, d, l) readsl(__io(p), d, l) + +static inline void readsb(unsigned int *addr, void * data, int bytelen) +{ + unsigned char *ptr = (unsigned char *)addr; + unsigned char *ptr2 = (unsigned char *)data; + while (bytelen) { + *ptr2 = *ptr; + ptr2++; + bytelen--; + } +} + +static inline void readsw(unsigned int *addr, void * data, int wordlen) +{ + unsigned short *ptr = (unsigned short *)addr; + unsigned short *ptr2 = (unsigned short *)data; + while (wordlen) { + *ptr2 = *ptr; + ptr2++; + wordlen--; + } +} + +static inline void readsl(unsigned int *addr, void * data, int longlen) +{ + unsigned int *ptr = (unsigned int *)addr; + unsigned int *ptr2 = (unsigned int *)data; + while (longlen) { + *ptr2 = *ptr; + ptr2++; + longlen--; + } +} +static inline void writesb(unsigned int *addr, const void * data, int bytelen) +{ + unsigned char *ptr = (unsigned char *)addr; + unsigned char *ptr2 = (unsigned char *)data; + while (bytelen) { + *ptr = *ptr2; + ptr2++; + bytelen--; + } +} +static inline void writesw(unsigned int *addr, const void * data, int wordlen) +{ + unsigned short *ptr = (unsigned short *)addr; + unsigned short *ptr2 = (unsigned short *)data; + while (wordlen) { + *ptr = *ptr2; + ptr2++; + wordlen--; + } +} +static inline void writesl(unsigned int *addr, const void * data, int longlen) +{ + unsigned int *ptr = (unsigned int *)addr; + unsigned int *ptr2 = (unsigned int *)data; + while (longlen) { + *ptr = *ptr2; + ptr2++; + longlen--; + } +} +#endif + +#define outb_p(val, port) outb((val), (port)) +#define outw_p(val, port) outw((val), (port)) +#define outl_p(val, port) outl((val), (port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port, from, len) outsb(port, from, len) +#define outsw_p(port, from, len) outsw(port, from, len) +#define outsl_p(port, from, len) outsl(port, from, len) +#define insb_p(port, to, len) insb(port, to, len) +#define insw_p(port, to, len) insw(port, to, len) +#define insl_p(port, to, len) insl(port, to, len) + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * linux/Documentation/IO-mapping.txt. If you want a + * physical address, use __ioremap instead. + */ +extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags); +extern void __iounmap(void *addr); + +/* + * Generic ioremap support. + * + * Define: + * iomem_valid_addr(off,size) + * iomem_to_phys(off) + */ +#ifdef iomem_valid_addr +#define __arch_ioremap(off, sz, nocache) \ +({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off), _size, 0); \ + _ret; \ +}) + +#define __arch_iounmap __iounmap +#endif + +#define ioremap(off, sz) __arch_ioremap((off), (sz), 0) +#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1) +#define iounmap(_addr) __arch_iounmap(_addr) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * String version of IO memory access ops: + */ +extern void _memcpy_fromio(void *, unsigned long, size_t); +extern void _memcpy_toio(unsigned long, const void *, size_t); +extern void _memset_io(unsigned long, int, size_t); + +extern void __readwrite_bug(const char *fn); + +/* + * If this architecture has PCI memory IO, then define the read/write + * macros. These should only be used with the cookie passed from + * ioremap. + */ +#ifdef __mem_pci + +#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v, c) __raw_writeb(v, __mem_pci(c)) +#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) +#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c)) + +#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l)) +#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l)) +#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l)) + +#define eth_io_copy_and_sum(s, c, l, b) \ + eth_copy_and_sum((s), __mem_pci(c), (l), (b)) + +static inline int +check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#elif !defined(readb) + +#define readb(addr) (__readwrite_bug("readb"), 0) +#define readw(addr) (__readwrite_bug("readw"), 0) +#define readl(addr) (__readwrite_bug("readl"), 0) +#define writeb(v, addr) __readwrite_bug("writeb") +#define writew(v, addr) __readwrite_bug("writew") +#define writel(v, addr) __readwrite_bug("writel") + +#define eth_io_copy_and_sum(a, b, c, d) __readwrite_bug("eth_io_copy_and_sum") + +#define check_signature(io, sig, len) (0) + +#endif /* __mem_pci */ + +/* + * If this architecture has ISA IO, then define the isa_read/isa_write + * macros. + */ +#ifdef __mem_isa + +#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr)) +#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr)) +#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr)) +#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c)) +#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c)) +#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c)) + +#define isa_eth_io_copy_and_sum(a, b, c, d) \ + eth_copy_and_sum((a), __mem_isa(b), (c), (d)) + +static inline int +isa_check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#else /* __mem_isa */ + +#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0) +#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0) +#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0) +#define isa_writeb(val, addr) __readwrite_bug("isa_writeb") +#define isa_writew(val, addr) __readwrite_bug("isa_writew") +#define isa_writel(val, addr) __readwrite_bug("isa_writel") +#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io") +#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio") +#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio") + +#define isa_eth_io_copy_and_sum(a, b, c, d) \ + __readwrite_bug("isa_eth_io_copy_and_sum") + +#define isa_check_signature(io, sig, len) (0) + +#endif /* __mem_isa */ +#endif /* __KERNEL__ */ +#endif /* __ASM_NDS_IO_H */ diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h new file mode 100644 index 0000000..a6f1c93 --- /dev/null +++ b/arch/nds32/include/asm/mach-types.h @@ -0,0 +1,29 @@ +/* + * This was automagically generated from arch/nds/tools/mach-types! + * Do NOT edit + */ + +#ifndef __ASM_NDS32_MACH_TYPE_H +#define __ASM_NDS32_MACH_TYPE_H + +#ifndef __ASSEMBLY__ +/* The type of machine we're running on */ +extern unsigned int __machine_arch_type; +#endif + +/* see arch/arm/kernel/arch.c for a description of these */ +#define MACH_TYPE_ADPAG101 0 + +#ifdef CONFIG_ARCH_ADPAG101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADPAG101 +# endif +# define machine_is_adpag101() (machine_arch_type == MACH_TYPE_ADPAG101) +#else +# define machine_is_adpag101() (0) +#endif + +#endif /* __ASM_NDS32_MACH_TYPE_H */ diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h new file mode 100644 index 0000000..5bcc4e1 --- /dev/null +++ b/arch/nds32/include/asm/memory.h @@ -0,0 +1,19 @@ +/* + * linux/include/asm-arm/memory.h + * + * Copyright (C) 2000-2002 Russell King + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro(a)andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: this file should not be included by non-asm/.h files + */ +#ifndef __ASM_NDS_MEMORY_H +#define __ASM_NDS_MEMORY_H + +#endif /* __ASM_NDS_MEMORY_H */ diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h new file mode 100644 index 0000000..a928038 --- /dev/null +++ b/arch/nds32/include/asm/posix_types.h @@ -0,0 +1,84 @@ +/* + * linux/include/asm-arm/posix_types.h + * + * Copyright (C) 1996-1998 Russell King. + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro(a)andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 05-03-2010 Modified for arch NDS32 + */ +#ifndef __ARCH_NDS_POSIX_TYPES_H +#define __ARCH_NDS_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp))) + +#endif + +#endif /* __ARCH_NDS_POSIX_TYPES_H */ diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h new file mode 100644 index 0000000..e5d186c --- /dev/null +++ b/arch/nds32/include/asm/processor.h @@ -0,0 +1,25 @@ +/* + * linux/include/asm-arm/processor.h + * + * Copyright (C) 1995-2002 Russell King + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro(a)andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_NDS_PROCESSOR_H +#define __ASM_NDS_PROCESSOR_H + +/************************************************************** + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - so far some files include /asm/processor.h, but + * no one uses the macros defined in this head file. + **************************************************************/ + +#endif /* __ASM_ARM_PROCESSOR_H */ diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h new file mode 100644 index 0000000..83e8b81 --- /dev/null +++ b/arch/nds32/include/asm/ptrace.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro(a)andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * CAUTION: + * - do not implement for NDS32 Arch yet. + * - included in common.h + */ + +#ifndef __ASM_NDS_PTRACE_H +#define __ASM_NDS_PTRACE_H + +#include <asm/ptregs.h> + +#endif /* __ASM_NDS_PTRACE_H */ diff --git a/arch/nds32/include/asm/ptregs.h b/arch/nds32/include/asm/ptregs.h new file mode 100644 index 0000000..f78448c --- /dev/null +++ b/arch/nds32/include/asm/ptregs.h @@ -0,0 +1,81 @@ +/* + * linux/include/asm-arm/proc-armv/ptrace.h + * + * Copyright (C) 1996-1999 Russell King + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro(a)andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PTREGS_H +#define __PTREGS_H + +#define USR_MODE 0x00 +#define SU_MODE 0x01 +#define HV_MODE 0x10 +#define MODE_MASK (0x03<<3) +#define GIE_BIT 0x01 + +#ifndef __ASSEMBLY__ + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +struct pt_regs { + long uregs[39]; +}; + +#define PTREGS(reg) [reg] +#define R0 uregs[1] /* R0 */ +#define R1 uregs[2] +#define R2 uregs[3] +#define R3 uregs[4] +#define R4 uregs[5] +#define R5 uregs[6] +#define R6 uregs[7] +#define R7 uregs[8] +#define R8 uregs[9] +#define R9 uregs[10] +#define R10 uregs[11] +#define R11 uregs[12] +#define R12 uregs[13] +#define R13 uregs[14] +#define R14 uregs[15] +#define R15 uregs[16] +#define R16 uregs[17] +#define R17 uregs[18] +#define R18 uregs[19] +#define R19 uregs[20] +#define R20 uregs[21] +#define R21 uregs[22] +#define R22 uregs[23] +#define R23 uregs[24] +#define R24 uregs[25] +#define R25 uregs[26] +#define R26 uregs[27] +#define R27 uregs[28] +#define FP uregs[29] /* R28 */ +#define GP uregs[30] /* R29 */ +#define RA uregs[31] /* R30 */ +#define SP uregs[32] /* R31 */ +#define D0HI uregs[33] +#define D0LO uregs[34] +#define D1HI uregs[35] +#define D1LO uregs[36] +#define PSW uregs[37] /* IR0 */ +#define PC uregs[38] /* PC */ + +#define processor_mode(regs) \ + (((regs)->PSW & MODE_MASK) >> 3) + +#define interrupts_enabled(regs) \ + ((regs)->PSW & GIE_BIT) + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h new file mode 100644 index 0000000..610aa9e --- /dev/null +++ b/arch/nds32/include/asm/string.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro(a)andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_NDS_STRING_H +#define __ASM_NDS_STRING_H + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +extern char *strrchr(const char *s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char *strchr(const char *s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void *memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void *memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void *memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +#undef __HAVE_ARCH_MEMSET +extern void *memset(void *, int, __kernel_size_t); + +#ifdef CONFIG_MARCO_MEMSET +extern void __memzero(void *ptr, __kernel_size_t n); + +#define memset(p, v, n) \ + ({ \ + if ((n) != 0) { \ + if (__builtin_constant_p((v)) && (v) == 0) \ + __memzero((p), (n)); \ + else \ + memset((p), (v), (n)); \ + } \ + (p); \ + }) + +#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); }) +#else +extern void memzero(void *ptr, __kernel_size_t n); +#endif + +#endif /* __ASM_NDS_STRING_H */ diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h new file mode 100644 index 0000000..97f59e9 --- /dev/null +++ b/arch/nds32/include/asm/system.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul(a)andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_NDS_SYSTEM_H +#define __ASM_NDS_SYSTEM_H + +/* + * Interrupt configuring macros. + */ + +extern int irq_flags; + +#define local_irq_enable() \ + __asm__ __volatile__ ( \ + "mfsr %0, $psw\n\t" \ + "andi %0, %0, 0x1\n\t" \ + "setgie.e\n\t" \ + : \ + : "r" (irq_flags) \ + ) + +#define local_irq_disable() \ + do { \ + int __tmp_dummy; \ + __asm__ __volatile__ ( \ + "mfsr %0, $psw\n\t" \ + "andi %0, %0, 0x1\n\t" \ + "setgie.d\n\t" \ + "dsb\n\t" \ + : "=r" (__tmp_dummy) \ + ); \ + } while (0) + +#define local_irq_save(x) \ + __asm__ __volatile__ ( \ + "mfsr %0, $psw\n\t" \ + "andi %0, %0, 0x1\n\t" \ + "setgie.d\n\t" \ + "dsb\n\t" \ + : "=&r" (x) \ + ) + +#define local_save_flags(x) \ + __asm__ __volatile__ ( \ + "mfsr %0, $psw\n\t" \ + "andi %0, %0, 0x1\n\t" \ + "setgie.e\n\t" \ + "setgie.d\n\t" \ + : "=r" (x) \ + ) + +#define irqs_enabled_from_flags(x) ((x) != 0x1f) + +#define local_irq_restore(x) \ + do { \ + if (irqs_enabled_from_flags(x)) \ + local_irq_enable(); \ + } while (0) + +/* + * Force strict CPU ordering. + */ +#define nop() asm volatile ("nop;\n\t" : : ) +#define mb() asm volatile ("" : : : "memory") +#define rmb() asm volatile ("" : : : "memory") +#define wmb() asm volatile ("" : : : "memory") + +#endif /* __ASM_NDS_SYSTEM_H */ diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h new file mode 100644 index 0000000..2e8924f --- /dev/null +++ b/arch/nds32/include/asm/types.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro(a)andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_NDS_TYPES_H +#define __ASM_NDS_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +#include <stddef.h> + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + +#endif /* __KERNEL__ */ + +#endif diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h new file mode 100644 index 0000000..2383e08 --- /dev/null +++ b/arch/nds32/include/asm/u-boot-nds32.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro(a)andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul(a)andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _U_BOOT_NDS32_H_ +#define _U_BOOT_NDS32_H_ 1 + +/* for the following variables, see start.S */ +extern ulong _andesboot_start; /* code start */ +extern ulong _andesboot_end; /* code end */ +extern ulong _andesboot_real_end; /* first usable RAM address */ + +/* cpu/.../cpu.c */ +int cleanup_before_linux(void); + +/* board/.../... */ +int board_init(void); +int dram_init(void); + +/* cpu/.../interrupt.c */ +void reset_timer_masked(void); + +/* cpu/.../timer.c */ +int timer_init(void); + +#endif /* _U_BOOT_NDS32_H_ */ diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h new file mode 100644 index 0000000..fafe4e4 --- /dev/null +++ b/arch/nds32/include/asm/u-boot.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * Copyright (C) 2011 Andes Technology Corporation + * Copyright (C) 2010 Shawn Lin (nobuhiro(a)andestech.com) + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +#include <environment.h> + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + + env_t *bi_env; + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + + struct /* RAM configuration */ + { + unsigned long start; + unsigned long size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; +} bd_t; + +#endif /* _U_BOOT_H_ */ diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h new file mode 100644 index 0000000..ffa7e30 --- /dev/null +++ b/arch/nds32/include/asm/unaligned.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Andes Technology Corporation + * Copyright (C) 2011 Macpaul Lin (macpaul(a)andestech.com) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef _ASM_NDS_UNALIGNED_H +#define _ASM_NDS_UNALIGNED_H + +#include <compiler.h> +/* + * Select endianness + */ +#ifndef __NDSEB__ +#define get_unaligned __get_unaligned_le +#define put_unaligned __put_unaligned_le +#else +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be +#endif /* __NDSEB__ */ + +#include <asm/byteorder.h> + +#include <linux/unaligned/le_byteshift.h> +#include <linux/unaligned/be_byteshift.h> +#include <linux/unaligned/generic.h> + +#endif /* _ASM_NDS_UNALIGNED_H */ -- 1.7.3.5

6 138

[U-Boot] [PATCH 0/3] Makefile & x86 - Move to generic include/asm/arch/asm-offsets.h
by Graeme Russ 21 Oct '11

21 Oct '11

This series creates build rules to create (and clean) include/asm/arch/asm-offsets.h from an asm-offsets.c file located in the SoC directory. In particular, the new rules will skip creating the asm-offsets.h file if the SoC does not have an asm-offsets.c file Big Fat Note: I have not tested this on ARM which needs to be looked at closely as the SoC files are one level deeper than where sc520 sits under x86 Graeme Russ (3): Makefile: Add generic build rules for include/asm/arch/asm-offsets.h x86: Rename include/asm/ic to include/asm/arch-sc520 sc520: Create arch asm-offsets Makefile | 22 ++- arch/x86/cpu/Makefile | 3 + arch/x86/cpu/sc520/Makefile | 2 + arch/x86/cpu/sc520/asm-offsets.c | 45 ++++ arch/x86/cpu/sc520/sc520.c | 2 +- arch/x86/cpu/sc520/sc520_car.S | 5 +- arch/x86/cpu/sc520/sc520_pci.c | 4 +- arch/x86/cpu/sc520/sc520_reset.c | 2 +- arch/x86/cpu/sc520/sc520_sdram.c | 2 +- arch/x86/cpu/sc520/sc520_ssi.c | 4 +- arch/x86/cpu/sc520/sc520_timer.c | 2 +- arch/x86/cpu/start.S | 3 +- arch/x86/include/asm/arch-sc520/pci.h | 79 ++++++ arch/x86/include/asm/arch-sc520/sc520.h | 372 +++++++++++++++++++++++++++++ arch/x86/include/asm/arch-sc520/ssi.h | 34 +++ arch/x86/include/asm/global_data.h | 19 -- arch/x86/include/asm/ic/pci.h | 79 ------ arch/x86/include/asm/ic/sc520.h | 398 ------------------------------- arch/x86/include/asm/ic/ssi.h | 34 --- arch/x86/lib/zimage.c | 1 - board/eNET/eNET.c | 2 +- board/eNET/eNET_pci.c | 2 +- board/eNET/eNET_start16.S | 9 +- 23 files changed, 574 insertions(+), 551 deletions(-) create mode 100644 arch/x86/cpu/sc520/asm-offsets.c create mode 100644 arch/x86/include/asm/arch-sc520/pci.h create mode 100644 arch/x86/include/asm/arch-sc520/sc520.h create mode 100644 arch/x86/include/asm/arch-sc520/ssi.h delete mode 100644 arch/x86/include/asm/ic/pci.h delete mode 100644 arch/x86/include/asm/ic/sc520.h delete mode 100644 arch/x86/include/asm/ic/ssi.h -- 1.7.5.2.317.g391b14

4 6

[U-Boot] [PATCH 0/3] ARM: Clean arm/lib/cache.c, modify ARM1136 and ARM926 accordingly
by Hong Xu 21 Oct '11

21 Oct '11

This series try to clean the code of arch/arm/lib/cache.c Move ARM1136 cache operations into cpu/arm1136/cache.c Add ARM926EJS cache operations into cpu/arm926ejs/cache.c Hong Xu (3): ARM: Clean arch/arm/lib/cache.c ARM: ARM1136 - Remove flush_cache from arch/arm/lib/cache.c ARM: ARM926EJS - Add cache operations arch/arm/cpu/arm1136/Makefile | 2 +- arch/arm/cpu/arm1136/cache.c | 33 +++++++++ arch/arm/cpu/arm926ejs/Makefile | 2 +- arch/arm/cpu/arm926ejs/cache.c | 142 +++++++++++++++++++++++++++++++++++++++ arch/arm/lib/cache.c | 55 +++++++++------- 5 files changed, 208 insertions(+), 26 deletions(-) create mode 100644 arch/arm/cpu/arm1136/cache.c create mode 100644 arch/arm/cpu/arm926ejs/cache.c

3 18

[U-Boot] [PATCH 01/13] BeagleBoard: config: load kernel from MMC ext, not FAT
by Joel A Fernandes 21 Oct '11

21 Oct '11

From: Koen Kooi <koen(a)dominion.thruhere.net> Signed-off-by: Koen Kooi <koen(a)dominion.thruhere.net> Signed-off-by: Joel A Fernandes <agnel.joel(a)gmail.com> --- include/configs/omap3_beagle.h | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index a494f99..038fb5b 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -231,7 +231,8 @@ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ -- 1.7.1

6 20

[U-Boot] [PATCH 0/7][v2] powerpc/85xx: P1010RDB
by Kumar Gala 20 Oct '11

20 Oct '11

Patch series adds support for P1010RDB, NAND support (for IFC on P1010) and various errata fixes for P1010. V2 changes: * re-work based on CCSRBAR cleanup patches * white space fixes * checkpatch cleanup fixes * rework 'dummy' udelay in nand spl code - k

4 16

[U-Boot] P2020 L2 cache as SRAM
by Fabian Cenedese 19 Oct '11

19 Oct '11

Hi We're trying to configure the PPC P2020 cpu to use the L2 cache as SRAM so we can load the U-Boot code in there. However we stumble into problems. Sometimes the cpu goes on trap when trying to access this area. Sometimes there's no trap but we seem to access a different area. That's probably a problem with setting up a TLB/LAW. Has anybody already done this and could share some code with us? I've seen that there's a mpc85xx branch with quite some work going on. Where should we base our work on? Should we use the master or is it better to use this branch? I'm used to svn, not git, so there may be other options I don't know about yet. Thanks bye Fabi

4 5

[U-Boot] [PATCH] STx AMC8548: initial support for Silicon Turnkey Express AMC8548 board
by Alex Dubov 18 Oct '11

18 Oct '11

AMC8548 is a RapidIO development board in AMC form factor, featuring MPC8548E processor, DDR2 SO-DIMM slot, 16MB of hardwired NAND flash memory, real time clock and additional serial EEPROM on i2c bus (enabled). USB controller is available, but not presently enabled. Additional board information is available at: http://www.silicontkx.com/AMC8548.htm Signed-off-by: Alex Dubov <oakad(a)yahoo.com> --- This is really a patch repost from Fall, 2009. The board is old and never was that good, but I still got those running, so I propped up an u-boot config as well. Nothing fancy here, just a fairly standard config. MAINTAINERS | 1 + board/stx/stxamc8548/Makefile | 53 ++++++ board/stx/stxamc8548/law.c | 50 +++++ board/stx/stxamc8548/stxamc8548.c | 120 ++++++++++++ board/stx/stxamc8548/tlb.c | 82 ++++++++ boards.cfg | 1 + include/configs/stxamc8548.h | 374 +++++++++++++++++++++++++++++++++++++ 7 files changed, 681 insertions(+), 0 deletions(-) create mode 100644 board/stx/stxamc8548/Makefile create mode 100644 board/stx/stxamc8548/law.c create mode 100644 board/stx/stxamc8548/stxamc8548.c create mode 100644 board/stx/stxamc8548/tlb.c create mode 100644 include/configs/stxamc8548.h diff --git a/MAINTAINERS b/MAINTAINERS index 14d06ca..787db07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -141,6 +141,7 @@ Jon Diekema <jon.diekema(a)smiths-aerospace.com> Alex Dubov <oakad(a)yahoo.com> mpq101 MPC8548 + stxamc8548 MPC8548 Dirk Eibach <eibach(a)gdsys.de> diff --git a/board/stx/stxamc8548/Makefile b/board/stx/stxamc8548/Makefile new file mode 100644 index 0000000..58bc1b3 --- /dev/null +++ b/board/stx/stxamc8548/Makefile @@ -0,0 +1,53 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/stx/stxamc8548/law.c b/board/stx/stxamc8548/law.c new file mode 100644 index 0000000..0a435d9 --- /dev/null +++ b/board/stx/stxamc8548/law.c @@ -0,0 +1,50 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x1fff_ffff DDR (set elsewhere) autodetect + * 0xc000_0000 0xdfff_ffff RapidIO (set elsewhere) 512M + * 0xe000_0000 0xe000_ffff CCSR (set elsewhere) 1M + * 0xf000_0000 0xffff_ffff LBC options + FLASH 256M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * LAW 0 is reserved for boot mapping + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_LBC) +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxamc8548/stxamc8548.c b/board/stx/stxamc8548/stxamc8548.c new file mode 100644 index 0000000..e0c4f9c --- /dev/null +++ b/board/stx/stxamc8548/stxamc8548.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2011 Alex Dubov <oakad(a)yahoo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> + +/* + * Initialize Local Bus + */ +void local_bus_init(void) +{ + fsl_lbc_t *lbc = LBC_BASE_ADDR; + + out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ + out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ +} + +int checkboard(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + + puts("Board: Silicon Turnkey Express AMC8548 "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif + putc('\n'); + + /* + * Initialize local bus. + */ + local_bus_init(); + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + out_be32(&gur->tsec34ioovcr, 0xe7e0); /* 1110 0111 1110 0xxx */ + + out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ + out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ + return 0; +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) +{ + int rc = 0; + + if (ctrl_num == 0) { + rc = i2c_read(SPD_EEPROM_ADDRESS, 0, 1, (uchar *)ctrl_dimms_spd, + sizeof(ddr2_spd_eeprom_t)); + if (rc) { + debug("DDR: failed to read SPD from address %u\n", + SPD_EEPROM_ADDRESS); + memset(ctrl_dimms_spd, 0, sizeof(ddr2_spd_eeprom_t)); + } + } +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + popts->clk_adjust = 6; + popts->cpo_override = 7; + popts->write_data_delay = 3; + popts->half_strength_driver_enable = 0; +} + +void pci_init_board(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* PCI is disabled */ + out_be32(&gur->devdisr, in_be32(&gur->devdisr) + | MPC85xx_DEVDISR_PCI1 + | MPC85xx_DEVDISR_PCI2 + | MPC85xx_DEVDISR_PCIE); +} + +#if defined(CONFIG_OF_BOARD_SETUP) + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} + +#endif diff --git a/board/stx/stxamc8548/tlb.c b/board/stx/stxamc8548/tlb.c new file mode 100644 index 0000000..fd2eaec --- /dev/null +++ b/board/stx/stxamc8548/tlb.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 256M Non-cacheable, guarded + * 0xf0000000 256M LBC (FLASH included) + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, + CONFIG_SYS_LBC_OPTION_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 1: 1M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_SYS_SRIO1_MEM_PHYS + /* + * TLB 2: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, + CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 141b143..2096cc3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -497,6 +497,7 @@ P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freesca P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SPIFLASH P4080DS powerpc mpc85xx corenet_ds freescale mpq101 powerpc mpc85xx mpq101 mercury - mpq101 +stxamc8548 powerpc mpc85xx stxamc8548 stx - stxamc8548 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/include/configs/stxamc8548.h b/include/configs/stxamc8548.h new file mode 100644 index 0000000..e6eb799 --- /dev/null +++ b/include/configs/stxamc8548.h @@ -0,0 +1,374 @@ +/* + * Copyright 2011 Alex Dubov <oakad(a)yahoo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Merury Computers MPQ101 board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_36BIT +# define CONFIG_PHYS_64BIT +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 /* MPC8548 specific */ +#define CONFIG_MPQ101 /* MPQ101 board specific */ + +#define CONFIG_SYS_SRIO /* enable serial RapidIO */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_PANIC_HANG + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +# define CONFIG_ADDR_MAP +# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + + +#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_CCSRBAR 0xe0000000 + +#ifdef CONFIG_PHYS_64BIT +# define CONFIG_SYS_CCSRBAR_PHYS 0xfe0000000ull +#else +# define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif + +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#define CONFIG_DDR_SPD +#define CONFIG_SPD_EEPROM +#define CONFIG_DDR_2T_TIMING +#define SPD_EEPROM_ADDRESS 0x50 + +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + + +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0ffffffc + +/* + * RAM definitions + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ + + +/* + * FLASH on the Local Bus + * One bank, 16M, using the CFI driver. + */ +#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */ + +#ifdef CONFIG_PHYS_64BIT +# define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull +#else +# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +/* 0xff001801 */ +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_32 | BR_V) + +/* 0xff006e65 */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(16) | OR_GPCM_XAM | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_6 \ + | OR_GPCM_TRLX | OR_GPCM_EAD) + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash. + */ +#define CONFIG_ASSUME_AMD_FLASH + +/* + * Environment parameters + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K boot sector */ +#define CONFIG_ENV_SIZE 0x4000 + +/* Environment at the start of flash sector, before text. */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x58000) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_TEXT_BASE 0xfffA0000 + +/* + * Cypress CY7C67200 USB controller on the Local Bus. + * Not supported by u-boot at present. + */ +#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000 + +#ifdef CONFIG_PHYS_64BIT +# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull +#else +# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE +#endif + +/* 0xf0001001 */ +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \ + | BR_PS_16 | BR_V) + +/* fffff002 */ +#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \ + | OR_GPCM_BCTLD | OR_GPCM_EHTR) + +/* + * Serial Ports + */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \ + 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* + * I2C buses and peripherals + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* I2C RTC - DS1339 */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* I2C EEPROM - 24C32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 + +/* + * RapidIO MMU + */ +#ifdef CONFIG_SYS_SRIO +# define CONFIG_SRIO1 +# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 +# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ + +# ifdef CONFIG_PHYS_64BIT +# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull +# else +# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT +# endif +#endif + +/* + * Ethernet + */ +#ifdef CONFIG_TSEC_ENET + +# ifndef CONFIG_NET_MULTI +# define CONFIG_NET_MULTI +# endif + +# define CONFIG_MII /* MII PHY management */ +# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ + +# define CONFIG_TSEC1 +# define CONFIG_TSEC1_NAME "eTSEC0" +# define TSEC1_PHY_ADDR 0x10 +# define TSEC1_PHYIDX 0 +# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +# define CONFIG_TSEC2 +# define CONFIG_TSEC2_NAME "eTSEC1" +# define TSEC2_PHY_ADDR 0x11 +# define TSEC2_PHYIDX 0 +# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +# define CONFIG_TSEC3 +# define CONFIG_TSEC3_NAME "eTSEC2" +# define TSEC3_PHY_ADDR 0x12 +# define TSEC3_PHYIDX 0 +# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +# define CONFIG_TSEC4 +# define CONFIG_TSEC4_NAME "eTSEC3" +# define TSEC4_PHY_ADDR 0x13 +# define TSEC4_PHYIDX 0 +# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: eTSEC[0-3] */ +# define CONFIG_ETHPRIME "eTSEC0" +# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_JFFS2 + +/* + * Miscellaneous configurable options + */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +#define CONFIG_FIT /* new uImage format support */ +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +#ifdef CONFIG_SYS_HUSH_PARSER +# define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "AMC8548=> " /* Monitor Command Prompt */ + +/* Console I/O Buffer Size */ +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 +#else +# define CONFIG_SYS_CBSIZE 256 +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) + +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +# define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Basic Environment Configuration + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +/*default location for tftp and bootm*/ +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#endif /* __CONFIG_H */ -- 1.7.3.2

3 6

[U-Boot] [RFC PATCH 0/2] Early panic support
by Simon Glass 18 Oct '11

18 Oct '11

This patch set adds support for calling panic() before stdio is initialized. At present this will just hang with little or no indication of what the problem is. A new board_panic_no_console() function is added to the board API. If provided by the board it will be called in the event of a panic before the console is ready. This function should turn on all UARTS and spray the message out if it possibly can. This is somewhat related to the Graeme's pre-console buffer patch, which is why I am sending it for comment now. Simon Glass (2): Add board_panic_no_console to deal with early critical errors Add check that console is ready before output common/console.c | 4 ++-- include/common.h | 8 ++++++++ lib/vsprintf.c | 26 ++++++++++++++++++++++++-- 3 files changed, 34 insertions(+), 4 deletions(-) -- 1.7.3.1

3 13