August 2011 - U-Boot

[U-Boot] "armv7: integrate cache maintenance support" breaks km_kirkwood ethernet
by Holger Brunck 07 Aug '11

07 Aug '11

Hi Aneesh, today I did a rebase of my development branch to current u-boot master. And I saw on our km_kirkwood board that our egiga0 interface isn't working anymore. The CPU is a: SoC: Kirkwood 88F6281_A0 After bisecting the current tree I got: c2dd0d45540397704de9b13287417d21049d34c6 is the first bad commit commit c2dd0d45540397704de9b13287417d21049d34c6 Author: Aneesh V <aneesh(a)ti.com> Date: Thu Jun 16 23:30:49 2011 +0000 armv7: integrate cache maintenance support And indeed after reverting this commit on current HEAD my board is usable again. Any ideas how to fix this problem? Best regards Holger Brunck

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Re: [U-Boot] Fwd: Link stage error of porting uboot2011-06
by Albert ARIBAUD 07 Aug '11

07 Aug '11

Hi Larry, Le 05/08/2011 05:13, larry a écrit : > As your suggestion for me,Albert,I upgrade to uboot-v2011.06-rc3 by > Git.This is the latest version i found on Git .And modified some places > to make uboot buildable.Now arm-linux-readelf has no longer warns > "segmentation fault", but after i burn u-boot.bin into flash,still > nothing happened. > I prefer to sending you a patch and readelf details that i generate with > "git diff" and "arm-linux-readelf". Patches as attachments are not really welcome on this list -- and as I said, patches which are not submissions for mainline inclusion should be avoided too. Note that your patches have the added weirdness that many, if not all files in your patch have undergone attribute changes, with an addition of the "execute" flag that should never be set in a source code file. I suspect you are working on a Windows machine? Also, then changes that are in your patch are strange: I can only see an addition in boards.cfg, based on what is there for B2, but nothing else. Is your board supposed to be so similar to B2 that le U-Boot baseline needs no change in the source code? But then, why would it need a change in boards.cfg? Also, you should refrain from describing problems with "does not work" or "nothing happens". Clearly state what you do, how you do it, and then what you expect and do no get, or conversively, what happens that you did not expect. Here for instance (assuming the code you're building is actually assumed to work with your board, which I cannot check), what exactly "does not happen"? What does the debugger tell you of the execution of the code? Does it go through the board_init_f calls sequence? Does it relocate? Does it enter the RAM execution stage? > I am a freshman with uboot.I found no book or something else introduce > uboot.Even has DULG,but sometimes it was really helpless for me.Just > like the problem i met ,i have no idea how to deal with.I suppose > something wrong with linking stage or my cross-compiler. I suggest you browse the mailing list archives for patch sets meant to add support for a new board and see how they are done and compare with what you did. > Because of attachment size limitation,i compress patch with bzip2. > I suppose you can give me some advices.Thanks a lot. > > Best regards > larry Amicalement, -- Albert.

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[U-Boot] testing x86 builds on the fly
by Mike Frysinger 07 Aug '11

07 Aug '11

disclaimer: i have like 0 u-boot experience on x86. but i cant find README's in the src to answer my questions. the PIC support on x86 is finished right ? so does that mean we can take a u-boot.bin, tftp it to a running system into external memory, and then boot that on the fly purely for testing purposes ? burning to flash is both horribly slow and dangerous :x. -mike

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[U-Boot] [PATCH v3] MAKEALL ARMv7: Use boards.cfg
by Dirk Behme 07 Aug '11

07 Aug '11

From: Dirk Behme <dirk.behme(a)googlemail.com> Use the boards from boards.cfg for building ./MAKEALL ARMV7. Signed-off-by: Dirk Behme <dirk.behme(a)googlemail.com> --- Changes in v3: Instead of touching all ARMx boards, only update ARMV7. Current LIST_ARMV7 builds 19 boards while -c armv7 (i.e. using boards.cfg) builds 31 boards (including all boards from the current LIST_ARMV7). Changes in v2: Instead of dublicating the missing boards from boards.cfg to MAKEALL, use the boards defined in boards.cfg directly. See http://lists.denx.de/pipermail/u-boot/2011-August/097858.html MAKEALL | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-) Index: u-boot.git/MAKEALL =================================================================== --- u-boot.git.orig/MAKEALL +++ u-boot.git/MAKEALL @@ -417,27 +417,8 @@ LIST_ARM11=" \ ######################################################################### ## ARMV7 Systems ######################################################################### -LIST_ARMV7=" \ - am3517_crane \ - am3517_evm \ - ca9x4_ct_vxp \ - devkit8000 \ - dig297 \ - igep0020 \ - igep0030 \ - mx51evk \ - omap3_beagle \ - omap3_overo \ - omap3_evm \ - omap3_pandora \ - omap3_sdp3430 \ - omap3_zoom1 \ - omap3_zoom2 \ - omap4_panda \ - omap4_sdp4430 \ - s5p_goni \ - smdkc100 \ -" + +LIST_ARMV7="$(boards_by_cpu armv7)" ######################################################################### ## AT91 Systems

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[U-Boot] Advertising invitation from SKS
by SKS Media London 07 Aug '11

07 Aug '11

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Re: [U-Boot] [PATCH v2 1/2] gpio: Add GPIO driver framework for Marvell SoCs
by Ajay Bhargav 07 Aug '11

07 Aug '11

----- "Prafulla Wadaskar" <prafulla(a)marvell.com> wrote: > > -----Original Message----- > > From: u-boot-bounces(a)lists.denx.de > [mailto:u-boot-bounces@lists.denx.de] > > On Behalf Of Ajay Bhargav > > Sent: Thursday, August 04, 2011 4:21 PM > > To: Lei Wen > > Cc: u-boot(a)lists.denx.de > > Subject: Re: [U-Boot] [PATCH v2 1/2] gpio: Add GPIO driver framework > for > > Marvell SoCs > > > > ----- "Lei Wen" <adrian.wenl(a)gmail.com> wrote: > > > > > On Thu, Aug 4, 2011 at 4:51 PM, Albert ARIBAUD > > > <albert.u.boot(a)aribaud.net> wrote: > > > > Hi Simon, > > > > > > > > On 04/08/2011 02:04, Simon Guinot wrote: > > > >> Hi Ajay, > > > >> > > > >> On Wed, Aug 03, 2011 at 10:10:00AM +0530, Ajay Bhargav wrote: > > > >>> ----- "Simon Guinot"<simon(a)sequanux.org> wrote: > > > >>> > > > >>>> AFAIK, Orion and Kirkwood SoCs don't provide bitwise > set/clear > > > for > > > >>>> GPIO output/direction registers. Instead, a register must be > > > read > > > >>>> first to leave other bits unchanged (see __set_direction in > > > >>>> kw_gpio.c). > > > >>>> > > > >>>> Is it possible to handle Armada SoCs GPIOs in a same way ? > maybe > > > >>>> using > > > >>>> the pin registers (gpxx in the Armada struct gpio_reg array) > ? > > > >>>> > > > >>>> If not, this code is not Marvell generic but rather specific > for > > > >>>> Armada > > > >>>> SoCs and then maybe armada_gpio is a better name... > > > >>>> > > > >>>> Regards, > > > >>>> > > > >>>> Simon > > > >>> > > > >>> Hi Simon, > > > >>> > > > >>> Yes its possible to implement code that way, Armada SoC does > have > > > GPIO > > > >>> registers for set/clear. what about register naming?? I think > they > > > are > > > >>> different for Kirkwood and Orion. > > > >> > > > >> I think that the register names could be OK. But here is a > most > > > >> important problem: On Orion/Kirkwood SoCs, a single GPIO > output > > > register > > > >> is available (no set/clear variants as for Armada). I missed > that > > > point > > > >> at my first look. It is quite problematic because only two > > > registers are > > > >> shared between the different Marvell SoCs: level and direction. > In > > > fact, > > > >> this registers are probably relevant on every machines > providing > > > GPIOs... > > > >> > > > >> Maybe that having two common registers is not enough to add > > > >> Orion/Kirkwood support to the mvgpio driver ? > > > > > > > > >>> One more thing which can be done to make this code generic is > to > > > have > > > >>> some macros which can be defined by individual arch for > specific > > > registers > > > >>> which are going to be in use e.g. > > > >>> > > > >>> #define GPIO_PIN_LEVEL_REG > > > >>> #define GPIO_DIR_REG > > > >>> #define GPIO_PIN_SET_REG > > > >>> #define GPIO_PIN_CLR_REG > > > >> > > > >> Yes, but how to handle both a single GPI0 output register and > some > > > GPIO > > > >> {set,clear} output registers (in a nice way) ? > > > > > > > > Two distinct gipo drivers for the two marvell variants? > > > > > > If let I choose, I'd prefer two, since the register set is > different. > > > > > > Best regards, > > > Lei > > > > > > > Hi Simon, > > > > For Armada minimum 3 registers are required and available for > armada > > 1. Direction (read/write) > > 2. Pin level set (write only) > > 3. Pin level clear (write only) > > > > @lei > > How bout if we check for architecture and use specific code or > defines? > > i.e. > > #ifdef CONFIG_KIRKWOOD > > //KW code > > #elif CONFIG_ARMADA100 > > //Armada code > > #else > > //orion or other? > > #endif > > Let's avoid this, because there will be several SoC architectures that > uses similar GPIO register definitions, like kirkwood/orion have > similar definition and armada/mmp/pantheon/etc.. have different one. > > So we will end up having several #ifdefs. Ideally #ifdefs are > discouraged for better coding practices. > > Instead, > I would suggest to use macros for this code segments or alternatively > inlined functions and those should be defined in mvgpio.h, #ifdefed > with CPU core subversion (i.e. CONFIG_FEROCEION, > CONFIG_SHEEVA_88SV331xV5) > > Regards.. > Prafulla . . Hi Prafulla, I think it will be better to keep two driver files. Let this patch be for Armada/mmp/pantheon and other compatible SoCs. Should the common GPIO struct for armada/mmp etc.. be moved out of GPIO.h to mvgpio.h? Regards, Ajay Bhargav

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[U-Boot] OrderPost Dris
by James White 07 Aug '11

07 Aug '11

Dear Customer Am emailing your company regarding some Post Drivers i will like to order. .If yes than i will like you to email me back with the pick up price including tax on the Post Drivers that i will responds back with the quantities that i will need.and also i will like to know if you do accept credit card for the payment. .James White Managing Director James & Sons Ltd Email: james_white2001(a)yahoo.com

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[U-Boot] Late Engr. Jurge Krugger...
by Richard Gilbert Chambers 07 Aug '11

07 Aug '11

The Chambers of Richard Gilbert QC and Associates 2 Bedford Row London WC1R 4BU United Kingdom Tel: +44 (0)703 190 1802 Fax +44 (0)700 606 6349 DX LDE 17 Email: barrrgilbertq(a)hotmail.co.uk Attorney at Law Faegre & Benson LLP, UK. Office Hours: Monday - Friday 9:00a.m. - 5:00p.m. Evening Appointments Available On behalf of the Trustees and Executor of the estate of Late Engr. Jurge Krugger. I once again try to notify you as my earlier letter was returned undelivered. I wish to notify you that late Engr. J?rge Kr?gger made you a beneficiary to his WILL. He left the sum of Thirty Million, One Hundred Thousand Dollars ($30, 100.000.00) to you in the Codicil and last testament to his WILL.This may sound strange and unbelievable to you, but it is real and true. Being a widely traveled man, he must have been in contact with you in the past or simply you were nominated to him by one of his numerous friends abroad who wished you good. Engr. J?rge Kr?gger until his death was a member of the Helicopter Society and the Institute of Electronic & Electrical Engineers.According to him this money is to support your humanitarian activities and to help the poor and the needy in our society. Please if I reach you as I am hopeful, endeavor to get back to me as soon as possible to enable me conclude my job. I hope to hear from you in no distant time. Note: You are advise to contact me with my personal email address: barrrgilbertq(a)hotmail.co.uk I await your prompt response. Yours in Service, Barr. Richard GIlbert QC. Tel: +44 (0)703 190 1802 Fax +44 (0)700 606 6349 Email: barrrgilbertq(a)hotmail.co.uk Attorney at Law Faegre & Benson LLP, UK

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[U-Boot] (no subject)
by Bar Yasser 06 Aug '11

06 Aug '11

I am Bar Yasser, I have a very important Business matters i will like to discuss with you.If this your Email is valid Contact me through my personal email:rawashdeh.asseral44@w.cn Thank you Mr. Yasser Al

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[U-Boot] Teresa Joyner - Promotional Pens & Totebags
by custom.pens＠gmx.com 06 Aug '11

06 Aug '11

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