June 2011 - U-Boot

[U-Boot] [PATCH 0/1 v3] Dreamplug support
by u-boot＠lakedaemon.net 09 Jun '11

09 Jun '11

From: Jason Cooper <u-boot(a)lakedaemon.net> It compiles clean, and I've loaded it via JTAG and used it to dump the existing bootloader out of the SPI flash. I have _not_ used it to burn itself to the flash yet. I'm looking for comments before I try that. ;-) Some concerns: - The SPI flash chip is a Macronix MX25L1606, however it has the identical chip idcode to the MX25L1605. How is that properly handled? The 06 does have some new features [1]. [1] http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Ind… Changes from v1 to v2: - resorted series to move 'make all' support last. Changes from v2 to v3: - Use MACH_TYPE_GURUPLUG for now until dreamplug support is in Linux. - Update MAINTAINERS. - Collapse into one patch Jason Cooper (1): dreamplug: Initial support. MAINTAINERS | 1 + MAKEALL | 1 + board/Marvell/dreamplug/Makefile | 51 +++++++++++ board/Marvell/dreamplug/dreamplug.c | 154 ++++++++++++++++++++++++++++++++ board/Marvell/dreamplug/dreamplug.h | 39 ++++++++ board/Marvell/dreamplug/kwbimage.cfg | 160 ++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/dreamplug.h | 111 +++++++++++++++++++++++ 8 files changed, 518 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/dreamplug/Makefile create mode 100644 board/Marvell/dreamplug/dreamplug.c create mode 100644 board/Marvell/dreamplug/dreamplug.h create mode 100644 board/Marvell/dreamplug/kwbimage.cfg create mode 100644 include/configs/dreamplug.h

3 4

[U-Boot] [PATCH] sh: sh2a: Add sh2a optimize to config.mk
by Nobuhiro Iwamatsu 09 Jun '11

09 Jun '11

Only the optimization of sh2 had been supported up. This adds the optimization of sh2a. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- arch/sh/cpu/sh2/config.mk | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk index f2d40aa..f46b38f 100644 --- a/arch/sh/cpu/sh2/config.mk +++ b/arch/sh/cpu/sh2/config.mk @@ -23,6 +23,11 @@ # ENDIANNESS += -EB +ifdef CONFIG_SH2A +PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -mno-fdpic -ffreestanding +else # SH2 PLATFORM_CPPFLAGS += -m3e -mb +endif + PLATFORM_RELFLAGS += -ffixed-r13 PLATFORM_LDFLAGS += $(ENDIANNESS) -- 1.7.5.3

1 0

[U-Boot] cache support make DaVinci dm365 quicker reading emmc
by Raffaele Recalcati 09 Jun '11

09 Jun '11

Thanks to: commit c3330e9d6a11b6ead4a2346001338ce884b5832b Author: Heiko Schocher <hs(a)denx.de> Date: Fri Sep 17 13:10:30 2010 +0200 ARM (ARM926ejs): add data cache support, tested on magnesium and tx25 board My 'Basi' board, based on DaVinci dm365, can read the uImage (1.5MB) in 0.7 sec (with ext2load) instead of 2 sec. If I read using mmc read I can reach 0.3 sec, but I need to know the dimension. Take in account only that tftpboot doesn't work with dcache/icache enabled. Regards, Raffaele

1 1

[U-Boot] [PATCH] sh: Add support for SH2A freestanding build
by Phil Edworthy 09 Jun '11

09 Jun '11

SH2A toolchains often only provide an fdpic version of libgcc. This can't be used with bare-metal software like U-Boot, so this patch provides the necessary functions extracted from libgcc. Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/sh/cpu/sh2/config.mk | 2 +- arch/sh/lib/Makefile | 22 ++++ arch/sh/lib/ashiftlt.S | 192 ++++++++++++++++++++++++++++++++++++ arch/sh/lib/ashiftrt.S | 149 ++++++++++++++++++++++++++++ arch/sh/lib/ashldi3.c | 25 +++++ arch/sh/lib/libgcc.h | 25 +++++ arch/sh/lib/lshiftrt.S | 192 ++++++++++++++++++++++++++++++++++++ arch/sh/lib/lshrdi3.c | 25 +++++ arch/sh/lib/movmem.S | 238 +++++++++++++++++++++++++++++++++++++++++++++ 9 files changed, 869 insertions(+), 1 deletions(-) create mode 100644 arch/sh/lib/ashiftlt.S create mode 100644 arch/sh/lib/ashiftrt.S create mode 100644 arch/sh/lib/ashldi3.c create mode 100644 arch/sh/lib/libgcc.h create mode 100644 arch/sh/lib/lshiftrt.S create mode 100644 arch/sh/lib/lshrdi3.c create mode 100644 arch/sh/lib/movmem.S diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk index f2d40aa..42206e6 100644 --- a/arch/sh/cpu/sh2/config.mk +++ b/arch/sh/cpu/sh2/config.mk @@ -23,6 +23,6 @@ # ENDIANNESS += -EB -PLATFORM_CPPFLAGS += -m3e -mb +PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -mno-fdpic -ffreestanding PLATFORM_RELFLAGS += -ffixed-r13 PLATFORM_LDFLAGS += $(ENDIANNESS) diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index c0670cb..6aaf55a 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -21,8 +21,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o +LIBGCC = $(obj)libgcc.o SOBJS-y += +GLSOBJS += ashiftrt.o +GLSOBJS += ashiftlt.o +GLSOBJS += lshiftrt.o +GLSOBJS += ashldi3.o +GLSOBJS += lshrdi3.o +GLSOBJS += movmem.o COBJS-y += board.o COBJS-y += bootm.o @@ -37,10 +44,25 @@ endif SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +LGOBJS := $(addprefix $(obj),$(GLSOBJS)) \ + $(addprefix $(obj),$(GLCOBJS)) + +# Always build libsh.o +TARGETS := $(LIB) + +# Build private libgcc only when asked for +ifdef USE_PRIVATE_LIBGCC +TARGETS += $(LIBGCC) +endif + +all: $(TARGETS) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +$(LIBGCC): $(obj).depend $(LGOBJS) + $(call cmd_link_o_target, $(LGOBJS)) + ######################################################################### # defines $(obj).depend target diff --git a/arch/sh/lib/ashiftlt.S b/arch/sh/lib/ashiftlt.S new file mode 100644 index 0000000..4940a87 --- /dev/null +++ b/arch/sh/lib/ashiftlt.S @@ -0,0 +1,192 @@ +/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006 + Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ + +!! libgcc routines for the Renesas / SuperH SH CPUs. +!! Contributed by Steve Chamberlain. +!! sac(a)cygnus.com + +!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines +!! recoded in assembly by Toshiyasu Morita +!! tm(a)netcom.com + +/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and + ELF local label prefixes by J"orn Rennecke + amylaar(a)cygnus.com */ + +! +! GLOBAL(ashlsi3) +! +! Entry: +! +! r4: Value to shift +! r5: Shifts +! +! Exit: +! +! r0: Result +! +! Destroys: +! +! (none) +! + .global __ashlsi3 + .align 2 +__ashlsi3: + mov #31,r0 + and r0,r5 + mova __ashlsi3_table,r0 + mov.b @(r0,r5),r5 +#ifdef __sh1__ + add r5,r0 + jmp @r0 +#else + braf r5 +#endif + mov r4,r0 + + .align 2 +__ashlsi3_table: + .byte __ashlsi3_0-__ashlsi3_table + .byte __ashlsi3_1-__ashlsi3_table + .byte __ashlsi3_2-__ashlsi3_table + .byte __ashlsi3_3-__ashlsi3_table + .byte __ashlsi3_4-__ashlsi3_table + .byte __ashlsi3_5-__ashlsi3_table + .byte __ashlsi3_6-__ashlsi3_table + .byte __ashlsi3_7-__ashlsi3_table + .byte __ashlsi3_8-__ashlsi3_table + .byte __ashlsi3_9-__ashlsi3_table + .byte __ashlsi3_10-__ashlsi3_table + .byte __ashlsi3_11-__ashlsi3_table + .byte __ashlsi3_12-__ashlsi3_table + .byte __ashlsi3_13-__ashlsi3_table + .byte __ashlsi3_14-__ashlsi3_table + .byte __ashlsi3_15-__ashlsi3_table + .byte __ashlsi3_16-__ashlsi3_table + .byte __ashlsi3_17-__ashlsi3_table + .byte __ashlsi3_18-__ashlsi3_table + .byte __ashlsi3_19-__ashlsi3_table + .byte __ashlsi3_20-__ashlsi3_table + .byte __ashlsi3_21-__ashlsi3_table + .byte __ashlsi3_22-__ashlsi3_table + .byte __ashlsi3_23-__ashlsi3_table + .byte __ashlsi3_24-__ashlsi3_table + .byte __ashlsi3_25-__ashlsi3_table + .byte __ashlsi3_26-__ashlsi3_table + .byte __ashlsi3_27-__ashlsi3_table + .byte __ashlsi3_28-__ashlsi3_table + .byte __ashlsi3_29-__ashlsi3_table + .byte __ashlsi3_30-__ashlsi3_table + .byte __ashlsi3_31-__ashlsi3_table + +__ashlsi3_6: + shll2 r0 +__ashlsi3_4: + shll2 r0 +__ashlsi3_2: + rts + shll2 r0 + +__ashlsi3_7: + shll2 r0 +__ashlsi3_5: + shll2 r0 +__ashlsi3_3: + shll2 r0 +__ashlsi3_1: + rts + shll r0 + +__ashlsi3_14: + shll2 r0 +__ashlsi3_12: + shll2 r0 +__ashlsi3_10: + shll2 r0 +__ashlsi3_8: + rts + shll8 r0 + +__ashlsi3_15: + shll2 r0 +__ashlsi3_13: + shll2 r0 +__ashlsi3_11: + shll2 r0 +__ashlsi3_9: + shll8 r0 + rts + shll r0 + +__ashlsi3_22: + shll2 r0 +__ashlsi3_20: + shll2 r0 +__ashlsi3_18: + shll2 r0 +__ashlsi3_16: + rts + shll16 r0 + +__ashlsi3_23: + shll2 r0 +__ashlsi3_21: + shll2 r0 +__ashlsi3_19: + shll2 r0 +__ashlsi3_17: + shll16 r0 + rts + shll r0 + +__ashlsi3_30: + shll2 r0 +__ashlsi3_28: + shll2 r0 +__ashlsi3_26: + shll2 r0 +__ashlsi3_24: + shll16 r0 + rts + shll8 r0 + +__ashlsi3_31: + shll2 r0 +__ashlsi3_29: + shll2 r0 +__ashlsi3_27: + shll2 r0 +__ashlsi3_25: + shll16 r0 + shll8 r0 + rts + shll r0 + +__ashlsi3_0: + rts + nop diff --git a/arch/sh/lib/ashiftrt.S b/arch/sh/lib/ashiftrt.S new file mode 100644 index 0000000..45ce865 --- /dev/null +++ b/arch/sh/lib/ashiftrt.S @@ -0,0 +1,149 @@ +/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006 + Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ + +!! libgcc routines for the Renesas / SuperH SH CPUs. +!! Contributed by Steve Chamberlain. +!! sac(a)cygnus.com + +!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines +!! recoded in assembly by Toshiyasu Morita +!! tm(a)netcom.com + +/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and + ELF local label prefixes by J"orn Rennecke + amylaar(a)cygnus.com */ + + .global __ashiftrt_r4_0 + .global __ashiftrt_r4_1 + .global __ashiftrt_r4_2 + .global __ashiftrt_r4_3 + .global __ashiftrt_r4_4 + .global __ashiftrt_r4_5 + .global __ashiftrt_r4_6 + .global __ashiftrt_r4_7 + .global __ashiftrt_r4_8 + .global __ashiftrt_r4_9 + .global __ashiftrt_r4_10 + .global __ashiftrt_r4_11 + .global __ashiftrt_r4_12 + .global __ashiftrt_r4_13 + .global __ashiftrt_r4_14 + .global __ashiftrt_r4_15 + .global __ashiftrt_r4_16 + .global __ashiftrt_r4_17 + .global __ashiftrt_r4_18 + .global __ashiftrt_r4_19 + .global __ashiftrt_r4_20 + .global __ashiftrt_r4_21 + .global __ashiftrt_r4_22 + .global __ashiftrt_r4_23 + .global __ashiftrt_r4_24 + .global __ashiftrt_r4_25 + .global __ashiftrt_r4_26 + .global __ashiftrt_r4_27 + .global __ashiftrt_r4_28 + .global __ashiftrt_r4_29 + .global __ashiftrt_r4_30 + .global __ashiftrt_r4_31 + .global __ashiftrt_r4_32 + + .align 1 +__ashiftrt_r4_32: +__ashiftrt_r4_31: + rotcl r4 + rts + subc r4,r4 +__ashiftrt_r4_30: + shar r4 +__ashiftrt_r4_29: + shar r4 +__ashiftrt_r4_28: + shar r4 +__ashiftrt_r4_27: + shar r4 +__ashiftrt_r4_26: + shar r4 +__ashiftrt_r4_25: + shar r4 +__ashiftrt_r4_24: + shlr16 r4 + shlr8 r4 + rts + exts.b r4,r4 +__ashiftrt_r4_23: + shar r4 +__ashiftrt_r4_22: + shar r4 +__ashiftrt_r4_21: + shar r4 +__ashiftrt_r4_20: + shar r4 +__ashiftrt_r4_19: + shar r4 +__ashiftrt_r4_18: + shar r4 +__ashiftrt_r4_17: + shar r4 +__ashiftrt_r4_16: + shlr16 r4 + rts + exts.w r4,r4 +__ashiftrt_r4_15: + shar r4 +__ashiftrt_r4_14: + shar r4 +__ashiftrt_r4_13: + shar r4 +__ashiftrt_r4_12: + shar r4 +__ashiftrt_r4_11: + shar r4 +__ashiftrt_r4_10: + shar r4 +__ashiftrt_r4_9: + shar r4 +__ashiftrt_r4_8: + shar r4 +__ashiftrt_r4_7: + shar r4 +__ashiftrt_r4_6: + shar r4 +__ashiftrt_r4_5: + shar r4 +__ashiftrt_r4_4: + shar r4 +__ashiftrt_r4_3: + shar r4 +__ashiftrt_r4_2: + shar r4 +__ashiftrt_r4_1: + rts + shar r4 +__ashiftrt_r4_0: + rts + nop diff --git a/arch/sh/lib/ashldi3.c b/arch/sh/lib/ashldi3.c new file mode 100644 index 0000000..9b50d86 --- /dev/null +++ b/arch/sh/lib/ashldi3.c @@ -0,0 +1,25 @@ +#include "libgcc.h" + +long long __ashldi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.low = 0; + w.s.high = (unsigned int) uu.s.low << -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.low >> bm; + + w.s.low = (unsigned int) uu.s.low << b; + w.s.high = ((unsigned int) uu.s.high << b) | carries; + } + + return w.ll; +} diff --git a/arch/sh/lib/libgcc.h b/arch/sh/lib/libgcc.h new file mode 100644 index 0000000..05909d5 --- /dev/null +++ b/arch/sh/lib/libgcc.h @@ -0,0 +1,25 @@ +#ifndef __ASM_LIBGCC_H +#define __ASM_LIBGCC_H + +#include <asm/byteorder.h> + +typedef int word_type __attribute__ ((mode (__word__))); + +#ifdef __BIG_ENDIAN +struct DWstruct { + int high, low; +}; +#elif defined(__LITTLE_ENDIAN) +struct DWstruct { + int low, high; +}; +#else +#error I feel sick. +#endif + +typedef union { + struct DWstruct s; + long long ll; +} DWunion; + +#endif /* __ASM_LIBGCC_H */ diff --git a/arch/sh/lib/lshiftrt.S b/arch/sh/lib/lshiftrt.S new file mode 100644 index 0000000..e6fc1cf --- /dev/null +++ b/arch/sh/lib/lshiftrt.S @@ -0,0 +1,192 @@ +/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006 + Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ + +!! libgcc routines for the Renesas / SuperH SH CPUs. +!! Contributed by Steve Chamberlain. +!! sac(a)cygnus.com + +!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines +!! recoded in assembly by Toshiyasu Morita +!! tm(a)netcom.com + +/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and + ELF local label prefixes by J"orn Rennecke + amylaar(a)cygnus.com */ + +! +! __lshrsi3) +! +! Entry: +! +! r4: Value to shift +! r5: Shifts +! +! Exit: +! +! r0: Result +! +! Destroys: +! +! (none) +! + .global __lshrsi3 + .align 2 +__lshrsi3: + mov #31,r0 + and r0,r5 + mova __lshrsi3_table,r0 + mov.b @(r0,r5),r5 +#ifdef __sh1__ + add r5,r0 + jmp @r0 +#else + braf r5 +#endif + mov r4,r0 + + .align 2 +__lshrsi3_table: + .byte __lshrsi3_0-__lshrsi3_table + .byte __lshrsi3_1-__lshrsi3_table + .byte __lshrsi3_2-__lshrsi3_table + .byte __lshrsi3_3-__lshrsi3_table + .byte __lshrsi3_4-__lshrsi3_table + .byte __lshrsi3_5-__lshrsi3_table + .byte __lshrsi3_6-__lshrsi3_table + .byte __lshrsi3_7-__lshrsi3_table + .byte __lshrsi3_8-__lshrsi3_table + .byte __lshrsi3_9-__lshrsi3_table + .byte __lshrsi3_10-__lshrsi3_table + .byte __lshrsi3_11-__lshrsi3_table + .byte __lshrsi3_12-__lshrsi3_table + .byte __lshrsi3_13-__lshrsi3_table + .byte __lshrsi3_14-__lshrsi3_table + .byte __lshrsi3_15-__lshrsi3_table + .byte __lshrsi3_16-__lshrsi3_table + .byte __lshrsi3_17-__lshrsi3_table + .byte __lshrsi3_18-__lshrsi3_table + .byte __lshrsi3_19-__lshrsi3_table + .byte __lshrsi3_20-__lshrsi3_table + .byte __lshrsi3_21-__lshrsi3_table + .byte __lshrsi3_22-__lshrsi3_table + .byte __lshrsi3_23-__lshrsi3_table + .byte __lshrsi3_24-__lshrsi3_table + .byte __lshrsi3_25-__lshrsi3_table + .byte __lshrsi3_26-__lshrsi3_table + .byte __lshrsi3_27-__lshrsi3_table + .byte __lshrsi3_28-__lshrsi3_table + .byte __lshrsi3_29-__lshrsi3_table + .byte __lshrsi3_30-__lshrsi3_table + .byte __lshrsi3_31-__lshrsi3_table + +__lshrsi3_6: + shlr2 r0 +__lshrsi3_4: + shlr2 r0 +__lshrsi3_2: + rts + shlr2 r0 + +__lshrsi3_7: + shlr2 r0 +__lshrsi3_5: + shlr2 r0 +__lshrsi3_3: + shlr2 r0 +__lshrsi3_1: + rts + shlr r0 + +__lshrsi3_14: + shlr2 r0 +__lshrsi3_12: + shlr2 r0 +__lshrsi3_10: + shlr2 r0 +__lshrsi3_8: + rts + shlr8 r0 + +__lshrsi3_15: + shlr2 r0 +__lshrsi3_13: + shlr2 r0 +__lshrsi3_11: + shlr2 r0 +__lshrsi3_9: + shlr8 r0 + rts + shlr r0 + +__lshrsi3_22: + shlr2 r0 +__lshrsi3_20: + shlr2 r0 +__lshrsi3_18: + shlr2 r0 +__lshrsi3_16: + rts + shlr16 r0 + +__lshrsi3_23: + shlr2 r0 +__lshrsi3_21: + shlr2 r0 +__lshrsi3_19: + shlr2 r0 +__lshrsi3_17: + shlr16 r0 + rts + shlr r0 + +__lshrsi3_30: + shlr2 r0 +__lshrsi3_28: + shlr2 r0 +__lshrsi3_26: + shlr2 r0 +__lshrsi3_24: + shlr16 r0 + rts + shlr8 r0 + +__lshrsi3_31: + shlr2 r0 +__lshrsi3_29: + shlr2 r0 +__lshrsi3_27: + shlr2 r0 +__lshrsi3_25: + shlr16 r0 + shlr8 r0 + rts + shlr r0 + +__lshrsi3_0: + rts + nop diff --git a/arch/sh/lib/lshrdi3.c b/arch/sh/lib/lshrdi3.c new file mode 100644 index 0000000..bb340ac --- /dev/null +++ b/arch/sh/lib/lshrdi3.c @@ -0,0 +1,25 @@ +#include "libgcc.h" + +long long __lshrdi3(long long u, word_type b) +{ + DWunion uu, w; + word_type bm; + + if (b == 0) + return u; + + uu.ll = u; + bm = 32 - b; + + if (bm <= 0) { + w.s.high = 0; + w.s.low = (unsigned int) uu.s.high >> -bm; + } else { + const unsigned int carries = (unsigned int) uu.s.high << bm; + + w.s.high = (unsigned int) uu.s.high >> b; + w.s.low = ((unsigned int) uu.s.low >> b) | carries; + } + + return w.ll; +} diff --git a/arch/sh/lib/movmem.S b/arch/sh/lib/movmem.S new file mode 100644 index 0000000..c7efd40 --- /dev/null +++ b/arch/sh/lib/movmem.S @@ -0,0 +1,238 @@ +/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006 + Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ + +!! libgcc routines for the Renesas / SuperH SH CPUs. +!! Contributed by Steve Chamberlain. +!! sac(a)cygnus.com + +!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines +!! recoded in assembly by Toshiyasu Morita +!! tm(a)netcom.com + +/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and + ELF local label prefixes by J"orn Rennecke + amylaar(a)cygnus.com */ + + .text + .balign 4 + .global __movmem + .global __movstr + .set __movstr, __movmem + /* This would be a lot simpler if r6 contained the byte count + minus 64, and we wouldn't be called here for a byte count of 64. */ +__movmem: + sts.l pr,@-r15 + shll2 r6 + bsr __movmemSI52+2 + mov.l @(48,r5),r0 + .balign 4 +movmem_loop: /* Reached with rts */ + mov.l @(60,r5),r0 + add #-64,r6 + mov.l r0,@(60,r4) + tst r6,r6 + mov.l @(56,r5),r0 + bt movmem_done + mov.l r0,@(56,r4) + cmp/pl r6 + mov.l @(52,r5),r0 + add #64,r5 + mov.l r0,@(52,r4) + add #64,r4 + bt __movmemSI52 +! done all the large groups, do the remainder +! jump to movmem+ + mova __movmemSI4+4,r0 + add r6,r0 + jmp @r0 +movmem_done: ! share slot insn, works out aligned. + lds.l @r15+,pr + mov.l r0,@(56,r4) + mov.l @(52,r5),r0 + rts + mov.l r0,@(52,r4) + .balign 4 + + .global __movmemSI64 + .global __movstrSI64 + .set __movstrSI64, __movmemSI64 +__movmemSI64: + mov.l @(60,r5),r0 + mov.l r0,@(60,r4) + .global __movmemSI60 + .global __movstrSI60 + .set __movstrSI60, __movmemSI60 +__movmemSI60: + mov.l @(56,r5),r0 + mov.l r0,@(56,r4) + .global __movmemSI56 + .global __movstrSI56 + .set __movstrSI56, __movmemSI56 +__movmemSI56: + mov.l @(52,r5),r0 + mov.l r0,@(52,r4) + .global __movmemSI52 + .global __movstrSI52 + .set __movstrSI52, __movmemSI52 +__movmemSI52: + mov.l @(48,r5),r0 + mov.l r0,@(48,r4) + .global __movmemSI48 + .global __movstrSI48 + .set __movstrSI48, __movmemSI48 +__movmemSI48: + mov.l @(44,r5),r0 + mov.l r0,@(44,r4) + .global __movmemSI44 + .global __movstrSI44 + .set __movstrSI44, __movmemSI44 +__movmemSI44: + mov.l @(40,r5),r0 + mov.l r0,@(40,r4) + .global __movmemSI40 + .global __movstrSI40 + .set __movstrSI40, __movmemSI40 +__movmemSI40: + mov.l @(36,r5),r0 + mov.l r0,@(36,r4) + .global __movmemSI36 + .global __movstrSI36 + .set __movstrSI36, __movmemSI36 +__movmemSI36: + mov.l @(32,r5),r0 + mov.l r0,@(32,r4) + .global __movmemSI32 + .global __movstrSI32 + .set __movstrSI32, __movmemSI32 +__movmemSI32: + mov.l @(28,r5),r0 + mov.l r0,@(28,r4) + .global __movmemSI28 + .global __movstrSI28 + .set __movstrSI28, __movmemSI28 +__movmemSI28: + mov.l @(24,r5),r0 + mov.l r0,@(24,r4) + .global __movmemSI24 + .global __movstrSI24 + .set __movstrSI24, __movmemSI24 +__movmemSI24: + mov.l @(20,r5),r0 + mov.l r0,@(20,r4) + .global __movmemSI20 + .global __movstrSI20 + .set __movstrSI20, __movmemSI20 +__movmemSI20: + mov.l @(16,r5),r0 + mov.l r0,@(16,r4) + .global __movmemSI16 + .global __movstrSI16 + .set __movstrSI16, __movmemSI16 +__movmemSI16: + mov.l @(12,r5),r0 + mov.l r0,@(12,r4) + .global __movmemSI12 + .global __movstrSI12 + .set __movstrSI12, __movmemSI12 +__movmemSI12: + mov.l @(8,r5),r0 + mov.l r0,@(8,r4) + .global __movmemSI8 + .global __movstrSI8 + .set __movstrSI8, __movmemSI8 +__movmemSI8: + mov.l @(4,r5),r0 + mov.l r0,@(4,r4) + .global __movmemSI4 + .global __movstrSI4 + .set __movstrSI4, __movmemSI4 +__movmemSI4: + mov.l @(0,r5),r0 + rts + mov.l r0,@(0,r4) + + .global __movmem_i4_even + .global __movstr_i4_even + .set __movstr_i4_even, __movmem_i4_even + + .global __movmem_i4_odd + .global __movstr_i4_odd + .set __movstr_i4_odd, __movmem_i4_odd + + .global __movmemSI12_i4 + .global __movstrSI12_i4 + .set __movstrSI12_i4, __movmemSI12_i4 + + .p2align 5 +L_movmem_2mod4_end: + mov.l r0,@(16,r4) + rts + mov.l r1,@(20,r4) + + .p2align 2 + +__movmem_i4_even: + mov.l @r5+,r0 + bra L_movmem_start_even + mov.l @r5+,r1 + +__movmem_i4_odd: + mov.l @r5+,r1 + add #-4,r4 + mov.l @r5+,r2 + mov.l @r5+,r3 + mov.l r1,@(4,r4) + mov.l r2,@(8,r4) + +L_movmem_loop: + mov.l r3,@(12,r4) + dt r6 + mov.l @r5+,r0 + bt/s L_movmem_2mod4_end + mov.l @r5+,r1 + add #16,r4 +L_movmem_start_even: + mov.l @r5+,r2 + mov.l @r5+,r3 + mov.l r0,@r4 + dt r6 + mov.l r1,@(4,r4) + bf/s L_movmem_loop + mov.l r2,@(8,r4) + rts + mov.l r3,@(12,r4) + + .p2align 4 +__movmemSI12_i4: + mov.l @r5,r0 + mov.l @(4,r5),r1 + mov.l @(8,r5),r2 + mov.l r0,@r4 + mov.l r1,@(4,r4) + rts + mov.l r2,@(8,r4) -- 1.7.0.4

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[U-Boot] [PATCH] sh: Fix rsk7203 alignment problem
by Phil Edworthy 09 Jun '11

09 Jun '11

Signed-off-by: Phil Edworthy <phil.edworthy(a)renesas.com> --- board/renesas/rsk7203/lowlevel_init.S | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index 30ef5ab..ef4e341 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -186,6 +186,7 @@ PCCRL2_D: .word 0x1111 .align 2 PCCRL1_A: .long 0xFFFE3916 PCCRL1_D: .word 0x1010 +.align 2 PDCRL4_A: .long 0xFFFE3990 PDCRL4_D: .word 0x0011 .align 2 -- 1.7.0.4

2 1

[U-Boot] [PATCH V3 0/2] GPIO: Tegra2: add GPIO driver for Tegra2
by Tom Warren 09 Jun '11

09 Jun '11

This patchset adds a GPIO driver for Tegra2 SoC, and enables it for all boards Changes in V2: - use 'gpio_pin' enum in gpio.h (Simon Glass review request) - change 'GPIO_PORT8' to 'GPIO_FULLPORT' (Simon Glass request) - change 'offset' to 'pin' globally - enable GPIO for all boards (tegra2-common.h) Changes in V3: - use common cmd_gpio; remove redundant cmd processing code - add gpio_request, gpio_free and gpio_toggle - alias 'gpio_status' to 'gpio_info' for use in cmd_gpio Tom Warren (2): GPIO: Tegra2: add GPIO driver for Tegra2 arm: Tegra2: GPIO: enable GPIO for Tegra2 boards arch/arm/include/asm/arch-tegra2/gpio.h | 249 ++++++++++++++++++++++++++++++- common/cmd_gpio.c | 4 + drivers/gpio/Makefile | 1 + drivers/gpio/tegra2_gpio.c | 225 ++++++++++++++++++++++++++++ include/configs/tegra2-common.h | 2 + 5 files changed, 474 insertions(+), 7 deletions(-) create mode 100644 drivers/gpio/tegra2_gpio.c -- 1.7.5.1

2 3

[U-Boot] Download the u-boot from flash back to PC
by Rishi Dhupar 09 Jun '11

09 Jun '11

I have a board which has a version of u-boot on it that I would like to save before overwriting. I did not flash this version so I do not have the source code for it. I am trying to figure out is there away to essentially do a 'tftp get' of the u-boot.bin that was originally written to flash. I do not see any methods to "read" data from U-boot back to the PC. Is there any method to do this?

4 5

[U-Boot] Pull request: u-boot-arm/master
by Albert ARIBAUD 08 Jun '11

08 Jun '11

Hi Wolfgang, The following changes since commit 6f4dd40cddbd69c56fec1285fee02cbd5a3833d8: Prepare v2011.06-rc2 (2011-06-02 23:19:27 +0200) are available in the git repository at: git://git.denx.de/u-boot-arm.git master Fabio Estevam (4): mx31ads: Use the new relocation scheme mx31litekit: Fix boot with the new relocation scheme. imx31_litekit: Remove local config.mk imx27lite: Remove local config.mk Felix Radensky (1): mx31ads: Fix environment location on flash Minkyu Kang (1): SMDK6400: fix the compiler error board/freescale/mx31ads/config.mk | 1 - board/freescale/mx31ads/mx31ads.c | 19 +++++++++-- board/freescale/mx31ads/u-boot.lds | 42 +++++++++++++++++++++------ board/logicpd/imx27lite/config.mk | 5 --- board/logicpd/imx31_litekit/config.mk | 1 - board/logicpd/imx31_litekit/imx31_litekit.c | 17 +++++++---- board/samsung/smdk6400/u-boot-nand.lds | 2 + include/configs/imx27lite-common.h | 2 + include/configs/imx31_litekit.h | 3 ++ include/configs/mx31ads.h | 21 +++++++++---- 10 files changed, 80 insertions(+), 33 deletions(-) delete mode 100644 board/freescale/mx31ads/config.mk delete mode 100644 board/logicpd/imx27lite/config.mk delete mode 100644 board/logicpd/imx31_litekit/config.mk Amicalement, -- Albert.

2 1

[U-Boot] [PATCH 0/7] Blackfin fixes for 2011.06
by Mike Frysinger 08 Jun '11

08 Jun '11

Mostly a few simple fixes noticed after the 2011.06 merge window, or due to patches merged in that period. Harald Krapfenbauer (3): Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update embedded env settings Mike Frysinger (4): Blackfin: use common LDSCRIPT logic Blackfin: use on-chip reset func with newer parts Blackfin: bf548-ezkit/bf561-ezkit: update env location Blackfin: boards: build zlib dir with -O2 arch/blackfin/config.mk | 4 - arch/blackfin/cpu/reset.c | 70 ++++++++++---------- arch/blackfin/{lib/u-boot.lds.S => cpu/u-boot.lds} | 0 board/bct-brettl2/config.mk | 1 + board/bf518f-ezbrd/config.mk | 1 + board/bf526-ezbrd/config.mk | 1 + board/bf527-ad7160-eval/config.mk | 1 + board/bf527-ezkit/config.mk | 1 + board/bf527-sdp/config.mk | 1 + board/bf533-ezkit/config.mk | 1 + board/bf533-stamp/config.mk | 1 + board/bf537-stamp/config.mk | 1 + board/bf538f-ezkit/config.mk | 1 + board/bf548-ezkit/config.mk | 1 + board/bf561-acvilon/config.mk | 1 + board/bf561-ezkit/config.mk | 1 + board/cm-bf527/config.mk | 1 + board/cm-bf533/config.mk | 1 + board/cm-bf537e/cm-bf537e.c | 34 ++++++---- board/cm-bf537e/config.mk | 1 + board/cm-bf537u/cm-bf537u.c | 39 ++++++----- board/cm-bf537u/config.mk | 1 + board/cm-bf548/config.mk | 1 + board/cm-bf561/config.mk | 1 + board/ip04/config.mk | 1 + board/tcm-bf518/config.mk | 1 + board/tcm-bf537/config.mk | 1 + board/tcm-bf537/tcm-bf537.c | 34 ++++++---- include/configs/bf548-ezkit.h | 10 ++-- include/configs/bf561-ezkit.h | 23 +------ include/configs/cm-bf537e.h | 31 +++++++-- include/configs/cm-bf537u.h | 35 +++++++--- include/configs/tcm-bf537.h | 31 +++++++-- 33 files changed, 200 insertions(+), 133 deletions(-) rename arch/blackfin/{lib/u-boot.lds.S => cpu/u-boot.lds} (100%) -- 1.7.5.rc3

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[U-Boot] [PATCH 0/5] Add bitfields, clock and pinmux functions to simplify code
by Simon Glass 08 Jun '11

08 Jun '11

This patch series adds bitfield operations to the Tegra code and modifies the existing code to use them. These operations are highly desirable for many reasons which I attempt to explain here. U-Boot already has some basic macros for dealing with bitfields - setbits(), clrbits() and family. These used a supplied mask for setting and clearing bits. Bitfields done with masks are not the best since: 1. They require the manual creation of masks which is error-prone and pointless 2. They allow changing of non-contiguous bits which is seldom useful I believe we should take advantage of the fact that generally bitfields are contiguous groups of bits within a single word. If you look at clrsetbits_le32(), I would make these points: 1. Generally native endian is what is wanted, so putting le32() on the end seems unnecessary 2. It has three arguments: addr, clear, set. The last two are bitmasks which must be manually created 3. The clear and set arguments are dependent and yet no advantage is taken of the fact that they are presumably related to the same bitfield Here's a bit of code I found in U-Boot which illustrates this to some extent. The first parameter is the mask and the second is the value to set it to. It would be better to define the bitfield (as bits 31 to 24) and then have a macro to set the value to 0xa5. /* Trigger TIMER_0 by writing A5 to OCPW */ clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000); In fact I would go so far as to say that clrsetbits_le32() is for a different purpose than adjusting bitfield values. Clearly it is more powerful than we need, and yet harder to use for our common case. What could we do instead? I suggest we allow the definition of a bitfield as a high bit and a low bit, with the bitfield extended between these two, inclusive, values. This is nice and natural because the average SOC datasheet is full of things like this for example: Bit Meaning === ======= 8:7 UART type: 0 = something, 1 = something else, ... 6:2 UART word length 1:0 UART stop bits So a bitfield like 23:16 has hi=23 and lo=16. It is 8 bits long. This is easily converted into a: - shift (just use lo) - width (hi - lo + 1) - 'raw' mask (-1U >> (32 - width)) - 'cooked' mask: raw mask << shift We can use macros to make this easy, like this: #define UART_SPEED_HI 23 #define UART_SPEED_LO 16 then allow passing of just UART_SPEED to the macro, from which it gets the _LO and _HI parts automatically. We can actually go further if we don't mind a bit of macro magic and use something like: #define UART_SPEED_RANGE 23:16 from which we can extract these two values automatically. (would _BITS be a better suffix?). Either method allows us to pass UART_SPEED to the macros as a complete definition of the bitfield. We can then use the macros to set values, use enums and all the normal C things we like with less fear of complication or error. I need not dwell on the advantages of replacing all the ad-hoc bitfield manipulation with something common, tested and robust. What do compilers make of this? My examination with gcc on ARM at least shows that the compiler likes these macros and produces good code. Why not make these into inline functions? Some of the macros lend themselves to function calls more than others. The amount of code generated is typically small. The macros allow use to use the bitfield 'descriptor' directly in C code without things like bf_lo(UART_SPEED), bf_hi(UART_SPEED), for example. It doesn't seem like inline functions offer many advantages. Why not use C bitfields? They don't guarantee any particular read/write behaviour which makes them dangerous for I/O. The C standard doesn't talk much about endianness and ordering, and some claim that the generated code is worse than with bitfield macros. Also because they are evil http://yarchive.net/comp/linux/bitfields.html What does U-Boot do at the moment? Well, lots of things. Example 1: This from OMAP4: #define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20) #define DMM_LISA_MAP_SYS_SIZE_SHIFT 20 #define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24) section = __raw_readl(DMM_LISA_MAP_BASE + i*4); addr = section & DMM_LISA_MAP_SYS_ADDR_MASK; /* See if the address is valid */ if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) && (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) { size = ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >> DMM_LISA_MAP_SYS_SIZE_SHIFT); Example 2: This from netvia.c: /* some sane bit macros */ #define _BD(_b) (1U << (31-(_b))) #define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) #define _BW(_b) (1U << (15-(_b))) #define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) #define _BB(_b) (1U << (7-(_b))) #define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) #define _B(_b) _BD(_b) #define _BR(_l, _h) _BDR(_l, _h) #define PD_GP_INMASK 0 #define PD_GP_OUTMASK _BWR(3, 15) #define PD_SP_MASK 0 #define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15)) #define PD_SP_DIRVAL 0 ioport->iop_pddat = PD_GP_OUTVAL; ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; ioport->iop_pdpar = PD_SP_MASK; Example 3: This from bcm570x: #define BIT_NONE 0x00 #define BIT_0 0x01 #define BIT_1 0x02 #define BIT_2 0x04 #define BIT_3 0x08 #define BIT_4 0x10 #define BIT_5 0x20 #define BIT_6 0x40 #define BIT_7 0x80 #define BIT_8 0x0100 #define BIT_9 0x0200 #define BIT_10 0x0400 #define BIT_11 0x0800 (and so on) #define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11) #define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11) #define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9) switch (Value32 & BCM540X_AUX_SPEED_MASK) { case BCM540X_AUX_100BASETX_HD: Example 4: lxNpeA.h: /** set the rxBitField port */ #define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \ do { \ (rxbitfield) &= ~PORT_MASK; \ (rxbitfield) |= (((port) << 24) & PORT_MASK); \ } while(0) /** Mask to acess the rxBitField vcId */ #define VCID_MASK 0x00ff0000 /** return the rxBitField vcId */ #define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \ (((rxbitfield) & VCID_MASK) >> 16) (admittedly I struggled to find who uses this code...) Why make these Tegra-specific? Well, you have to start somewhere. If this patch series survives review then maybe we can look at expanding to other ARM SOCs, 64-bit CPUs and big-endian implementations. The attached patch series serves as a basic illustration of the definition and use of these macros. These macros could be expanded a little further to add more functionality and convenience, but simple is best. Also included is a basic test program which you can run with the native compiler like this: $ cd test $ make Simon Glass (5): Tegra2: Add bitfield access macros Tegra2: Add microsecond timer functions Tegra2: Add more clock support Tegra2: add additional pin multiplexing features Tegra2: Use clock and pinmux functions to simplify code arch/arm/cpu/armv7/tegra2/Makefile | 2 +- arch/arm/cpu/armv7/tegra2/ap20.c | 92 +++------- arch/arm/cpu/armv7/tegra2/clock.c | 163 +++++++++++++++++ arch/arm/cpu/armv7/tegra2/pinmux.c | 54 ++++++ arch/arm/cpu/armv7/tegra2/timer.c | 27 ++- arch/arm/include/asm/arch-tegra2/bitfield.h | 151 +++++++++++++++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 129 +++++-------- arch/arm/include/asm/arch-tegra2/clock.h | 264 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra2/pinmux.h | 156 +++++++++++++++- arch/arm/include/asm/arch-tegra2/timer.h | 34 ++++ board/nvidia/common/board.c | 65 +++---- test/Makefile | 36 ++++ test/bitfield.c | 230 +++++++++++++++++++++++ 13 files changed, 1204 insertions(+), 199 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/clock.c create mode 100644 arch/arm/cpu/armv7/tegra2/pinmux.c create mode 100644 arch/arm/include/asm/arch-tegra2/bitfield.h create mode 100644 arch/arm/include/asm/arch-tegra2/clock.h create mode 100644 arch/arm/include/asm/arch-tegra2/timer.h create mode 100644 test/Makefile create mode 100644 test/bitfield.c -- 1.7.3.1

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