June 2011 - U-Boot

[U-Boot] resend patches to replace previous 3/7, 6/7, 7/7
by York Sun 11 Jul '11

11 Jul '11

Kumar, These two patches replace previous 3/7, 6/7, 7/7 [PATCH 3/7] powerpc/mpc8xxx: Enable calculation for fixed DDR chips [PATCH 6/7] powerpc/mpc8xxx: Adding fallback to raw timing on supported boards [PATCH 7/7] powerpc/mpc8xxx: change raw timing function call parameters York

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[U-Boot] [PATCH] powerpc/corenet_ds: Fix RCW overriding for RDIMM
by York Sun 11 Jul '11

11 Jul '11

Allow overriding RCW for all RDIMM, not only quad-rank ones. Signed-off-by: York Sun <yorksun(a)freescale.com> --- board/freescale/corenet_ds/ddr.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 98024c7..f2b716d 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -219,7 +219,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->ddr_cdr1 = DDR_CDR1_DHC_EN; /* override SPD values. rcw_2 should vary at differnt speed */ - if (pdimm[0].n_ranks == 4) { + if (pdimm[0].registered_dimm == 1) { popts->rcw_override = 1; popts->rcw_1 = 0x000a5a00; if (ddr_freq <= 800) -- 1.7.0.4

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[U-Boot] [PATCH] powerpc/mpc85xx: Display a warning for unsupported DDR data rates
by York Sun 11 Jul '11

11 Jul '11

If DDR initialziation uses a speed table and the speed is not matched, print a warning message instead of silently ignoring. Signed-off-by: York Sun <yorksun(a)freescale.com> --- board/freescale/corenet_ds/ddr.c | 6 ++++++ board/freescale/mpc8572ds/ddr.c | 8 ++++---- board/freescale/mpc8641hpcn/ddr.c | 5 +++++ board/freescale/p2020ds/ddr.c | 6 ++++++ board/xes/xpedite550x/ddr.c | 6 ++++++ 5 files changed, 27 insertions(+), 4 deletions(-) diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index f2b716d..a184592 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -192,10 +192,16 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->twoT_en = pbsp->force_2T; + break; } pbsp++; } + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index ab471af..adcbd58 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -104,7 +104,6 @@ void fsl_ddr_board_options(memctl_options_t *popts, u32 num_params; u32 i; ulong ddr_freq; - int matched = 0; if (!pdimm->n_ranks) return; @@ -151,14 +150,15 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twoT_en = pbsp->force_2T; - matched = 1; break; } pbsp++; } - if (!matched) - printf("Warning: board specific timing not found!\n"); + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index bd0b299..4f2e853 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -127,6 +127,11 @@ void fsl_ddr_board_options(memctl_options_t *popts, } } + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + /* 2T timing enable */ popts->twoT_en = 1; } diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 9bf7d2f..926fd19 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -83,10 +83,16 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->twoT_en = pbsp->force_2T; + break; } pbsp++; } + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 3b6e08b..8031a34 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -125,10 +125,16 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->clk_adjust = pbsp->clk_adjust; popts->cpo_override = pbsp->cpo; popts->twoT_en = 0; + break; } pbsp++; } + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed -- 1.7.0.4

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[U-Boot] [PATCH] powerpc/mpc8xxx: fix DDR data width checking
by York Sun 11 Jul '11

11 Jul '11

Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data width and primary sdram width. The latter one has different meaning for DDR3. Signed-off-by: York Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 35 ++++++++++++++++++++++++------- 1 files changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 02efe58..bd9c466 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -423,14 +423,33 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * presuming all dimms are similar * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ - if (pdimm[0].primary_sdram_width == 64) - popts->data_bus_width = 0; - else if (pdimm[0].primary_sdram_width == 32) - popts->data_bus_width = 1; - else if (pdimm[0].primary_sdram_width == 16) - popts->data_bus_width = 2; - else - panic("Error: invalid primary sdram width!\n"); +#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2) + if (pdimm[0].n_ranks != 0) { + if ((pdimm[0].data_width >= 64) && \ + (pdimm[0].data_width <= 72)) + popts->data_bus_width = 0; + else if ((pdimm[0].data_width >= 32) || \ + (pdimm[0].data_width <= 40)) + popts->data_bus_width = 1; + else { + panic("Error: data width %u is invalid!\n", + pdimm[0].data_width); + } + } +#else + if (pdimm[0].n_ranks != 0) { + if (pdimm[0].primary_sdram_width == 64) + popts->data_bus_width = 0; + else if (pdimm[0].primary_sdram_width == 32) + popts->data_bus_width = 1; + else if (pdimm[0].primary_sdram_width == 16) + popts->data_bus_width = 2; + else { + panic("Error: primary sdram width %u is invalid!\n", + pdimm[0].primary_sdram_width); + } + } +#endif /* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) -- 1.7.0.4

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[U-Boot] [PATCH] powerpc/corenet_ds: add back buffer write for NOR flash
by York Sun 11 Jul '11

11 Jul '11

Enable buffer write for better performance. This platform uses a NOR flash chip which supports write buffer programming. CFI driver can query the buffer size and use it to program the flash for best performance. Signed-off-by: York Sun <yorksun(a)freescale.com> --- include/configs/corenet_ds.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f649147..28f8785 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -73,6 +73,7 @@ #else #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif #if defined(CONFIG_SPIFLASH) -- 1.7.0.4

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[U-Boot] [PATCH] powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time
by York Sun 11 Jul '11

11 Jul '11

Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: York Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +++ arch/powerpc/include/asm/fsl_ddr_sdram.h | 3 +++ 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 02d069c..3824aad 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -267,6 +267,9 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, tmrd_mclk = 2; #endif + if (popts->trwt_override) + trwt_mclk = popts->trwt; + ddr->timing_cfg_0 = (0 | ((trwt_mclk & 0x3) << 30) /* RWT */ | ((twrt_mclk & 0x3) << 28) /* WRT */ diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 1778cc5..bc063ea 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -271,6 +271,9 @@ typedef struct memctl_options_s { unsigned int rcw_2; /* control register 1 */ unsigned int ddr_cdr1; + + unsigned int trwt_override; + unsigned int trwt; /* read-to-write turnaround */ } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); -- 1.7.0.4

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[U-Boot] [PATCH] Add CONFIG_AT91FAMILY to AT91RM9200 arch
by Jens Scharsig 10 Jul '11

10 Jul '11

* Add CONFIG_AT91FAMILY to AT91RM9200 arch Signed-off-by: Jens Scharsig <js_at_ng(a)scharsoft.de> --- This will also fix brocken EB+CPUx9k2 board in Version 2011.03 arch/arm/include/asm/arch-at91/at91rm9200.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91rm9200.h b/arch/arm/include/asm/arch-at91/at91rm9200.h index 1bee6f2..6ec4503 100644 --- a/arch/arm/include/asm/arch-at91/at91rm9200.h +++ b/arch/arm/include/asm/arch-at91/at91rm9200.h @@ -131,5 +131,5 @@ #define AT91_PMX_CA_D16_31 0xFFFF0000 #define CONFIG_SYS_AT91_CPU_NAME "AT91RM9200" - +#define CONFIG_AT91FAMILY #endif -- 1.7.3.4

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[U-Boot] [Patch] MPC83XX: Fix PCI express clock setup
by Bill Cook 07 Jul '11

07 Jul '11

On a 8308 based board it was found that the PEX_GLK_RATIO register (programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This was tracked to the fact that the pci express clock frequency was not being assigned to the pciexp1_clk entry in the global data structure in file arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in 'do_clocks' command. Signed-off-by: Bill Cook <cook(a)isgchips.com> --- This also points to another problem. The description of the PEX_CLK_RATIO for the various SOCs in question (I checked the RMs for 8308, 8315, and 8378) shows a different maximum freqency for the PCIe core. So the divider in the equation on line 271 should reflect these differences. This seems to be the only mention of a maximum core frequency though, so I hesitate to patch pcie.c without feedback from Freescale. As I'm not a PCI expert, I would rather someone at Freescale look at this and provide appropriate patches. Also, if the max PCIe core frequency on the 8308 is really 125MHz, shouldn't the SCCR PCIEXPCM field of the SCCR be programmed with a 2 instead of 1, this is given by the definition of CONFIG_SYS_SCCR_PCIEXP1CM in the board config file. arch/powerpc/cpu/mpc83xx/speed.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 5e616dd..86d2e18 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -481,7 +481,8 @@ int get_clocks(void) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) gd->pciexp1_clk = pciexp1_clk; gd->pciexp2_clk = pciexp2_clk; #endif @@ -541,7 +542,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_MPC834x) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk)); #endif -- 1.7.2.3

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[U-Boot] powerpc/83xx: remove empty board_early_init_f()
by Timur Tabi 07 Jul '11

07 Jul '11

Remove an empty board_early_init_f() from the MPC8323ERD and MPC360ERDK boards. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- board/freescale/mpc8323erdb/mpc8323erdb.c | 5 ----- board/freescale/mpc8360erdk/mpc8360erdk.c | 5 ----- include/configs/MPC8323ERDB.h | 2 -- include/configs/MPC8360ERDK.h | 1 - 4 files changed, 0 insertions(+), 13 deletions(-) diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 7a0ff18..f29b2f4 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -66,11 +66,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; -int board_early_init_f(void) -{ - return 0; -} - int fixed_sdram(void); phys_size_t initdram(int board_type) diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index 2baa11a..99c0fbb 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -207,11 +207,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, }; -int board_early_init_f(void) -{ - return 0; -} - int board_early_init_r(void) { void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index e25d5ac..4d4c758 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -59,8 +59,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000 -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ - /* * IMMR new address */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a4f42cf..851872a 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -72,7 +72,6 @@ #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL 0x40000000 -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ #define CONFIG_BOARD_EARLY_INIT_R /* -- 1.7.3.4

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[U-Boot] [PATCH 0/4] MPC83xx: Add MergerBox support.
by Andre Schwarz 07 Jul '11

07 Jul '11

This patch adds support for Matrix Vision MergerBox. It is a Freescale MPC8377 based 3D image preocessing platform utilizing Altera Cyclone IV FPGA and Silicon Motion SM107 embedded graphics connected via PCI. See doc/README.mergerbox for details. MAKEALL -c mpc83xx shows no errors/warnings introduced by this patchset. Files have been checked using checkpatch. Andre Schwarz (4): MergerBox: Add board config file. MergerBox: add documentation. MergerBox: add maintainer and boards.cfg entries. MergerBox: add board specific files in vendor dir. MAINTAINERS | 1 + board/matrix_vision/mergerbox/Makefile | 51 +++ board/matrix_vision/mergerbox/fpga.c | 175 ++++++++ board/matrix_vision/mergerbox/fpga.h | 30 ++ board/matrix_vision/mergerbox/mergerbox.c | 241 +++++++++++ board/matrix_vision/mergerbox/mergerbox.h | 67 +++ board/matrix_vision/mergerbox/pci.c | 134 +++++++ board/matrix_vision/mergerbox/sm107.c | 126 ++++++ boards.cfg | 1 + doc/README.mergerbox | 59 +++ include/configs/MERGERBOX.h | 619 +++++++++++++++++++++++++++++ 11 files changed, 1504 insertions(+), 0 deletions(-) create mode 100644 board/matrix_vision/mergerbox/Makefile create mode 100644 board/matrix_vision/mergerbox/fpga.c create mode 100644 board/matrix_vision/mergerbox/fpga.h create mode 100644 board/matrix_vision/mergerbox/mergerbox.c create mode 100644 board/matrix_vision/mergerbox/mergerbox.h create mode 100644 board/matrix_vision/mergerbox/pci.c create mode 100644 board/matrix_vision/mergerbox/sm107.c create mode 100644 doc/README.mergerbox create mode 100644 include/configs/MERGERBOX.h

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