April 2011 - U-Boot

[U-Boot] DSN: failed (Returned mail: Data format error)
by Mailbot for etexusa.com 02 Apr '11

02 Apr '11

This is a Delivery Status Notification (DSN). I was unable to deliver your message to lord(a)netscape.com. I said RCPT TO:<lord(a)netscape.com> And they gave me the error; 550 Recipient Rejected: No account by that name here

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[U-Boot] [PATCH] USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor.
by Alexander Holler 02 Apr '11

02 Apr '11

Remove __attribute__ ((packed)) to prevent byte access to soc registers in some gcc versions. Having patches to enable ehci for the BeagleBoard lying around for several month, this one was the show-stopper. Credits have to go to Laine Walker-Avina <lwalkera(a)ieee.org> for finding the problem. Signed-off-by: Alexander Holler <holler(a)ahsoftware.de> --- drivers/usb/host/ehci.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 945ab64..df9f055 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -55,7 +55,7 @@ struct ehci_hccr { #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) uint32_t cr_hccparams; uint8_t cr_hcsp_portrt[8]; -} __attribute__ ((packed)); +}; struct ehci_hcor { uint32_t or_usbcmd; @@ -85,7 +85,7 @@ struct ehci_hcor { #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; uint32_t or_systune; -} __attribute__ ((packed)); +}; #define USBMODE 0x68 /* USB Device mode */ #define USBMODE_SDIS (1 << 3) /* Stream disable */ -- 1.7.3.4

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[U-Boot] CFI flash broken for 8-bit bus
by Aaron Williams 02 Apr '11

02 Apr '11

Hi, I am running into issues in that the CFI code is broken for flash with an 8- bit bus. The problem is that the CFI code uses the wrong addresses for 8-bits vs 16-bits. The CFI function flash_map incorrectly calculates the byte offset with Spansion flash. In our case, we have an 8-bit Spansion S29GL-N MirrorBit flash chip on an 8- bit bus. According to the data sheet, in 8-bit mode the first unlock address is 0xAAA and the second is 0x555. Basically all of the addresses are approximately double what they are in 16-bit mode. Most of the addresses in the CFI code are wrong for 8-bit mode. They should be as follows: unlock1: 0xAAA unlock2: 0x555 CFI Query: 0xAA Offset Device ID: 0x02, 0x1c, 0x1e Offset Silicon Sector Factory Protect: 0x6 Sector protect verify (sector address) + 4 The problem is that the dectection code detects (incorrectly) that we're an 8- bit device on a 16-bit bus when in fact it's an 8-bit bus. For 16-bits, it's: unlock1: 0x555 unlock2: 0x2aa CFI Query: 0x55 Offset Device ID: 0x1, 0x0e, 0x0f Now, in 16-bit mode these addresses should be effectively doubled so they should look to be the same to software as I understand it. This is all taken from the datasheet. Note that the CFI code works fine with the flash hooked up as 16-bit on a 16- bit bus. If it's an 8-bit flash on a 16-bit bus then the addresses should be doubled. flash detect cfi fwc addr 1ec00000 cmd f0 f0 8bit x 8 bit fwc addr 1ec00000 cmd ff ff 8bit x 8 bit fwc addr 1ec00055 cmd 98 98 8bit x 8 bit <== should be 0x1ec000AA is= cmd 51(Q) addr 1ec00010 is= 0 51 fwc addr 1ec00000 cmd f0 f0 8bit x 8 bit fwc addr 1ec00000 cmd ff ff 8bit x 8 bit fwc addr 1ec00555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr 1ec00010 is= 0 51 fwc addr 1ec00000 cmd f0 f0f0 16bit x 8 bit fwc addr 1ec00000 cmd ff ffff 16bit x 8 bit fwc addr 1ec000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr 1ec00020 is= 5151 5151 is= cmd 52(R) addr 1ec00022 is= 5252 5252 is= cmd 59(Y) addr 1ec00024 is= 5959 5959 device interface is 2 found port 2 chip 1 port 16 bits chip 8 bits 00 : 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 06 QRY..@.....'6... 10 : 06 09 13 03 05 03 02 18 02 00 06 00 01 7f 00 00 ................ 20 : 02 00 00 00 00 00 00 00 00 00 00 00 00 08 13 e8 ................ fwc addr 1ec00000 cmd f0 f0f0 16bit x 8 bit fwc addr 1ec01554 cmd aa aaaa 16bit x 8 bit fwc addr 1ec00aaa cmd 55 5555 16bit x 8 bit fwc addr 1ec01554 cmd 90 9090 16bit x 8 bit fwc addr 1ec00000 cmd f0 f0f0 16bit x 8 bit fwc addr 1ec000aa cmd 98 9898 16bit x 8 bit manufacturer is 2 manufacturer id is 0x0 device id is 0x3f device id2 is 0x0 cfi version is 0x3133 size_ratio 1 port 16 bits chip 8 bits found 1 erase regions erase region 0: 0x0200007f erase_region_count = 128 erase_region_size = 131072 fwc addr 1ec00000 cmd f0 f0 8bit x 8 bit fwc addr 1fbe0000 cmd 70 70 8bit x 8 bit flash_is_busy: 0 Flash: 16 MiB -Aaron

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by Benz Promo 02 Apr '11

02 Apr '11

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[U-Boot] [PATCH 1/3] OMAP3: Change some USB related MUX settings to values used by the kernel.
by Alexander Holler 02 Apr '11

02 Apr '11

Signed-off-by: Alexander Holler <holler(a)ahsoftware.de> --- board/ti/beagle/beagle.h | 27 ++++++++++++++------------- 1 files changed, 14 insertions(+), 13 deletions(-) diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index b22b653..abb69e7 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -273,18 +273,18 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ /* USB EHCI (port 2) */\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA4*/\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA5*/\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA6*/\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA3*/\ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA1*/\ /*Control and debug */\ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ @@ -383,7 +383,8 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN | M4)) /*GPIO_147*/ #define MUX_BEAGLE_XM() \ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\ -- 1.7.3.4

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[U-Boot] [PATCH] USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor.
by Alexander Holler 02 Apr '11

02 Apr '11

Remove __attribute__ ((packed)) to prevent byte access to soc registers in some gcc versions. Having patches to enable ehci for the BeagleBoard lying around for several month, this one was the show-stopper. Credits have to go to Laine Walker-Avina <lwalkera(a)ieee.org> for finding the problem. Signed-off-by: Alexander Holler <holler(a)ahsoftware.de> --- drivers/usb/host/ehci.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 945ab64..df9f055 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -55,7 +55,7 @@ struct ehci_hccr { #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) uint32_t cr_hccparams; uint8_t cr_hcsp_portrt[8]; -} __attribute__ ((packed)); +}; struct ehci_hcor { uint32_t or_usbcmd; @@ -85,7 +85,7 @@ struct ehci_hcor { #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; uint32_t or_systune; -} __attribute__ ((packed)); +}; #define USBMODE 0x68 /* USB Device mode */ #define USBMODE_SDIS (1 << 3) /* Stream disable */ -- 1.7.3.4

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[U-Boot] jffs2 & ubi rootfs in nor flash
by Charles Krinke 01 Apr '11

01 Apr '11

I have an MPC8323ERDB and I need to boot jffs2 and ubi root filesystem images and I am hung up a bit in mtdparts/mtdids and various u-boot and linux config settings. I *think* I have the correct config settings in both u-boot and linux, but cant quite get to the last step (that is, past the "no init found" step and to a bash login). I am searching for a little advice to help me bridge my slightly incomplete understanding of the boot process from flash. Flash Layout 0xFE000000 - 0xFE7FFFFF u-boot (4 sectors) 0xFE080000 - 0xFE09FFFF dtb (1 sector) 0xFE0A0000 - 0xFE2FFFFF uImage (19 sectors) 0xFE300000 - endOfFlash rootfs I have in the u-boot configuration CONFIG_MTD_DEVICE CONFIG_CMD_MTDPARTS CONFIG_MTD_PARTITIONS And in the linux configuration CONFIG_MTD CONFIG_MTD_PARTITIONS In the u-boot environment, I have mtdids=nor0=nor mtdparts=nor:3072k(u-boot),-(jffs2) bootargs=root=/dev/mtdblock1 rootfstype=jffs2 rw mtdparts=nor:3072k(u-boot),-(jffs2) rw console=ttyS0,115200 I must be missing something simple here, but I do not see what it is. As soon as I get the jffs2 partition booting, ubifs is the very next step. -- Charles Krinke

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[U-Boot] Pull request: nand flash
by Scott Wood 01 Apr '11

01 Apr '11

The following changes since commit 19b54a701811220221fc4d5089a2bb18892018ca: Prepare v2011.03 (2011-03-31 23:45:36 +0200) are available in the git repository at: git://git.denx.de/u-boot-nand-flash.git master Florian Fainelli (1): NAND: add support for reading ONFI page table Haiying Wang (1): Fix NAND_SPL and ONENAND_IPL in Makefile Scott Wood (1): NAND: add more watchdog resets michael (1): atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PIN Makefile | 30 +++---- drivers/mtd/nand/atmel_nand.c | 2 + drivers/mtd/nand/nand_base.c | 199 +++++++++++++++++++++++++++++++---------- drivers/mtd/nand/nand_util.c | 2 + include/linux/mtd/nand.h | 69 ++++++++++++++ 5 files changed, 237 insertions(+), 65 deletions(-)

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[U-Boot] [PATCH] Provide pr_debug() and pr_info().
by Alexander Holler 01 Apr '11

01 Apr '11

Those are usefull for compatibility with the kernel. Remove the locally defined pr_debug() in atmel_mci.c. Signed-off-by: Alexander Holler <holler(a)ahsoftware.de> --- drivers/mmc/atmel_mci.c | 6 ------ include/common.h | 4 ++++ 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/atmel_mci.c b/drivers/mmc/atmel_mci.c index 3946ffe..9d798ca 100644 --- a/drivers/mmc/atmel_mci.c +++ b/drivers/mmc/atmel_mci.c @@ -32,12 +32,6 @@ #include "atmel_mci.h" -#ifdef DEBUG -#define pr_debug(fmt, args...) printf(fmt, ##args) -#else -#define pr_debug(...) do { } while(0) -#endif - #ifndef CONFIG_SYS_MMC_CLK_OD #define CONFIG_SYS_MMC_CLK_OD 150000 #endif diff --git a/include/common.h b/include/common.h index 893af5c..a1fe8df 100644 --- a/include/common.h +++ b/include/common.h @@ -119,11 +119,15 @@ typedef volatile unsigned char vu_char; #ifdef DEBUG #define debug(fmt,args...) printf (fmt ,##args) #define debugX(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args); +#define pr_debug(fmt, args...) printf(fmt, ##args) #else #define debug(fmt,args...) #define debugX(level,fmt,args...) +#define pr_debug(fmt, args...) #endif /* DEBUG */ +#define pr_info(fmt, args...) printf (fmt, ##args) + #define error(fmt, args...) do { \ printf("ERROR: " fmt "\nat %s:%d/%s()\n", \ ##args, __FILE__, __LINE__, __func__); \ -- 1.7.3.4

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[U-Boot] [PATCH] serial: ns16550: fix different reg size access
by Lei Wen 01 Apr '11

01 Apr '11

Some hardware would dysfunctional if only access the register by byte. This patch is tend to recover original access the responding register according to CONFIG_SYS_NS16550_REG_SIZE. Signed-off-by: Lei Wen <leiwen(a)marvell.com> --- README | 5 ++++ drivers/serial/ns16550.c | 7 ------ include/ns16550.h | 51 +++++++++++++++++++++++++++++++++++++-------- 3 files changed, 47 insertions(+), 16 deletions(-) diff --git a/README b/README index 21cd71b..45bc7dd 100644 --- a/README +++ b/README @@ -2660,6 +2660,11 @@ use the "saveenv" command to store a valid environment. space for already greatly restricted images, including but not limited to NAND_SPL configurations. +- CONFIG_SYS_NS16550_MAX_REG_SIZE: + Define the ns16550 max register size, + if the CONFIG_SYS_NS16550_REG_SIZE is smaller than this value, + use padding to fill those gap. + Low Level (hardware related) configuration options: --------------------------------------------------- diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 8eeb48f..4956c7f 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -16,13 +16,6 @@ #define UART_FCRVAL (UART_FCR_FIFO_EN | \ UART_FCR_RXSR | \ UART_FCR_TXSR) /* Clear & enable FIFOs */ -#ifdef CONFIG_SYS_NS16550_PORT_MAPPED -#define serial_out(x,y) outb(x,(ulong)y) -#define serial_in(y) inb((ulong)y) -#else -#define serial_out(x,y) writeb(x,y) -#define serial_in(y) readb(y) -#endif #ifndef CONFIG_SYS_NS16550_IER #define CONFIG_SYS_NS16550_IER 0x00 diff --git a/include/ns16550.h b/include/ns16550.h index 9ea81e9..a51b6e6 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -20,17 +20,50 @@ * Note that the following macro magic uses the fact that the compiler * will not allocate storage for arrays of size 0 */ - -#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) +#if (CONFIG_SYS_NS16550_REG_SIZE == 4) || (CONFIG_SYS_NS16550_REG_SIZE == -4) +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED +#define serial_out(x, y) outl(x, y) +#define serial_in(y) inl(y) +#else +#define serial_out(x, y) writel(x, y) +#define serial_in(y) readl(y) +#endif +#define UART_REG_TYPE unsigned int +#elif (CONFIG_SYS_NS16550_REG_SIZE == 2) || (CONFIG_SYS_NS16550_REG_SIZE == -2) +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED +#define serial_out(x, y) outw(x, y) +#define serial_in(y) inw(y) +#else +#define serial_out(x, y) writew(x, y) +#define serial_in(y) readw(y) +#endif +#define UART_REG_TYPE unsigned short +#elif (CONFIG_SYS_NS16550_REG_SIZE == 1) || (CONFIG_SYS_NS16550_REG_SIZE == -1) +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED +#define serial_out(x, y) outb(x, y) +#define serial_in(y) inb(y) +#else +#define serial_out(x, y) writeb(x, y) +#define serial_in(y) readb(y) +#endif +#define UART_REG_TYPE unsigned char +#else #error "Please define NS16550 registers size." -#elif (CONFIG_SYS_NS16550_REG_SIZE > 0) -#define UART_REG(x) \ - unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ - unsigned char x; -#elif (CONFIG_SYS_NS16550_REG_SIZE < 0) +#endif + +#ifndef CONFIG_SYS_NS16550_MAX_REG_SIZE +#define CONFIG_SYS_NS16550_MAX_REG_SIZE 4 +#endif +#if (CONFIG_SYS_NS16550_REG_SIZE > 0) +#define UART_REG(x) \ + unsigned char prepad_##x[CONFIG_SYS_NS16550_MAX_REG_SIZE \ + - CONFIG_SYS_NS16550_REG_SIZE]; \ + UART_REG_TYPE x; +#else #define UART_REG(x) \ - unsigned char x; \ - unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; + UART_REG_TYPE x; \ + unsigned char prepad_##x[CONFIG_SYS_NS16550_MAX_REG_SIZE \ + + CONFIG_SYS_NS16550_REG_SIZE]; #endif struct NS16550 { -- 1.7.0.4

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