March 2011 - U-Boot

[U-Boot] [PATCH] powerpc/85xx: Fix pixis_reset altbank mask on MPC8536DS
by Kumar Gala 07 Mar '11

07 Mar '11

From: Matthew McClintock <msm(a)freescale.com> Currently, pixis_reset altbank does not work properly. This patch uses the correct mask to boot into the alternate bank. Signed-off-by: Matthew McClintock <msm(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/configs/MPC8536DS.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 11ee650..13300de 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -311,7 +311,7 @@ /* old pixis referenced names */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 +#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -- 1.7.2.3

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[U-Boot] [PATCH] powerpc/85xx: Fix plat_mp_up() disabling of BPTR for CoreNet Platforms
by Kumar Gala 07 Mar '11

07 Mar '11

From: Ed Swarthout <Ed.Swarthout(a)freescale.com> Copying directly from ECM/PQ3 is not correct for how CoreNet based platforms handle boot page translation. Signed-off-by: Ed Swarthout <Ed.Swarthout(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/mp.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index a019b1b..6c0da83 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -288,7 +288,7 @@ static void plat_mp_up(unsigned long bootpg) * unusable for normal operation but it does allow OSes to easily * reset a processor core to put it back into U-Boot's spinloop. */ - clrbits_be32(&ecm->bptr, 0x80000000); + clrbits_be32(&ccm->bstrar, LAW_EN); #endif } #else -- 1.7.2.3

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[U-Boot] [PATCH] corenet_ds: pick the middle value for all tested timing parameters
by Kumar Gala 07 Mar '11

07 Mar '11

From: York Sun <yorksun(a)freescale.com> For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent. The best values should be picked up from the middle of all working combinations. This patch updates the table with confirmed values tested on Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s, 900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s, 1200MT/s, 1000MT/s. Signed-off-by: York Sun <yorksun(a)freescale.com> --- board/freescale/corenet_ds/ddr.c | 58 ++++++++++++-------------------------- 1 files changed, 18 insertions(+), 40 deletions(-) diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 6660b01..f8df9d1 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -170,27 +170,16 @@ const board_specific_parameters_t board_specific_parameters[][30] = { * lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 0, 333, 4, 5, 7, 0xff, 2, 0}, - {334, 400, 4, 5, 7, 0xff, 2, 0}, - {401, 549, 4, 5, 7, 0xff, 2, 0}, - {550, 680, 4, 5, 7, 0xff, 2, 0}, - {681, 850, 4, 5, 7, 0xff, 2, 0}, - {851, 1050, 4, 5, 7, 0xff, 2, 0}, - {1051, 1250, 4, 5, 8, 0xff, 2, 0}, - {1251, 1350, 4, 5, 9, 0xff, 2, 0}, - { 0, 333, 2, 5, 7, 0xff, 2, 0}, - {334, 400, 2, 5, 7, 0xff, 2, 0}, - {401, 549, 2, 5, 7, 0xff, 2, 0}, - {550, 680, 2, 5, 7, 0xff, 2, 0}, - {681, 850, 2, 5, 7, 0xff, 2, 0}, - {851, 1050, 2, 5, 7, 0xff, 2, 0}, - {1051, 1250, 2, 5, 7, 0xff, 2, 0}, + { 0, 850, 4, 1, 5, 0xff, 2, 0}, + {851, 950, 4, 3, 5, 0xff, 2, 0}, + {951, 1050, 4, 5, 8, 0xff, 2, 0}, + {1051, 1250, 4, 5, 10, 0xff, 2, 0}, + {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + { 0, 850, 2, 5, 6, 0xff, 2, 0}, + {851, 950, 2, 5, 7, 0xff, 2, 0}, + {951, 1050, 2, 5, 7, 0xff, 2, 0}, + {1051, 1250, 2, 4, 6, 0xff, 2, 0}, {1251, 1350, 2, 5, 7, 0xff, 2, 0}, - { 0, 333, 1, 5, 7, 0xff, 2, 0}, - {334, 400, 1, 5, 7, 0xff, 2, 0}, - {401, 549, 1, 5, 7, 0xff, 2, 0}, - {550, 680, 1, 5, 7, 0xff, 2, 0}, - {681, 850, 1, 5, 7, 0xff, 2, 0} }, { @@ -199,27 +188,16 @@ const board_specific_parameters_t board_specific_parameters[][30] = { * lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 0, 333, 4, 5, 7, 0xff, 2, 0}, - {334, 400, 4, 5, 7, 0xff, 2, 0}, - {401, 549, 4, 5, 7, 0xff, 2, 0}, - {550, 680, 4, 5, 7, 0xff, 2, 0}, - {681, 850, 4, 5, 7, 0xff, 2, 0}, - {851, 1050, 4, 5, 7, 0xff, 2, 0}, - {1051, 1250, 4, 5, 8, 0xff, 2, 0}, - {1251, 1350, 4, 5, 9, 0xff, 2, 0}, - { 0, 333, 2, 5, 7, 0xff, 2, 0}, - {334, 400, 2, 5, 7, 0xff, 2, 0}, - {401, 549, 2, 5, 7, 0xff, 2, 0}, - {550, 680, 2, 5, 7, 0xff, 2, 0}, - {681, 850, 2, 5, 7, 0xff, 2, 0}, - {851, 1050, 2, 5, 7, 0xff, 2, 0}, - {1051, 1250, 2, 5, 7, 0xff, 2, 0}, + { 0, 850, 4, 1, 5, 0xff, 2, 0}, + {851, 950, 4, 3, 5, 0xff, 2, 0}, + {951, 1050, 4, 5, 8, 0xff, 2, 0}, + {1051, 1250, 4, 5, 10, 0xff, 2, 0}, + {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + { 0, 850, 2, 5, 6, 0xff, 2, 0}, + {851, 950, 2, 5, 7, 0xff, 2, 0}, + {951, 1050, 2, 5, 7, 0xff, 2, 0}, + {1051, 1250, 2, 4, 6, 0xff, 2, 0}, {1251, 1350, 2, 5, 7, 0xff, 2, 0}, - { 0, 333, 1, 5, 7, 0xff, 2, 0}, - {334, 400, 1, 5, 7, 0xff, 2, 0}, - {401, 549, 1, 5, 7, 0xff, 2, 0}, - {550, 680, 1, 5, 7, 0xff, 2, 0}, - {681, 850, 1, 5, 7, 0xff, 2, 0} } }; -- 1.7.2.3

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[U-Boot] [PATCH][v3] fsl_esdhc: Correcting esdhc timeout counter calculation
by Priyanka Jain 07 Mar '11

07 Mar '11

- Timeout counter value is set as DTOCV bits in SYSCTL register For counter value set as timeout, Timeout period = (2^(timeout + 13)) SD Clock cycles - As per 4.6.2.2 section of SD Card specification v2.00, host should cofigure timeout period value to minimum 0.25 sec. - Number of SD Clock cycles for 0.25sec should be minimum (SD Clock/sec * 0.25 sec) SD Clock cycles = (mmc->tran_speed * 1/4) SD Clock cycles - Calculating timeout based on (2^(timeout + 13)) >= mmc->tran_speed * 1/4 Taking log2 both the sides and rounding up to next power of 2 => timeout + 13 = log2(mmc->tran_speed/4) + 1 Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Andy Fleming <afleming(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> Acked-by: Mingkai Hu <Mingkai.Hu(a)freescale.com> --- Changes for v3: Including code changes of v1 as suggested by Stefano Babic Changes for v2: Added proper description as suggested by Wolfgang Denk drivers/mmc/fsl_esdhc.c | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a368fe6..359d939 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -207,7 +207,21 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize); /* Calculate the timeout period for data transactions */ - timeout = fls(mmc->tran_speed/10) - 1; + /* + * 1)Timeout period = (2^(timeout+13)) SD Clock cycles + * 2)Timeout period should be minimum 0.250sec as per SD Card spec + * So, Number of SD Clock cycles for 0.25sec should be minimum + * (SD Clock/sec * 0.25 sec) SD Clock cycles + * = (mmc->tran_speed * 1/4) SD Clock cycles + * As 1) >= 2) + * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 + * Taking log2 both the sides + * => timeout + 13 >= log2(mmc->tran_speed/4) + * Rounding up to next power of 2 + * => timeout + 13 = log2(mmc->tran_speed/4) + 1 + * => timeout + 13 = fls(mmc->tran_speed/4) + */ + timeout = fls(mmc->tran_speed/4); timeout -= 13; if (timeout > 14) -- 1.6.5.6

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[U-Boot] Microblaze: how to generate correct xparameters.h file
by llandre 07 Mar '11

07 Mar '11

Hi all, a colleague is facing the following problem. When using ISE/EDK 12.4 to build a microblaze-based system, the xparameters.h file that is generated do not match u-boot sources so I can't build U-Boot. In fact #defines included in this file are prefixed by XPAR_ while U-Boot sources expect them to be prefixed by XILINX_. So how to generate correct xparameter.h file? I suspect we have some misconfigured flag in ISE/EDK environment ... Any help would be appreciated. Thanks in advance, llandre -- DAVE - Simply Embedded web: www.dave.eu

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[U-Boot] CONFIG_WATCHDOG on MPC85XX and QorIQ P1/P2
by Felix Radensky 07 Mar '11

07 Mar '11

Hi, I'm trying to enable watchdog in u-boot on P1011 based platform. I've noticed that all 85XX platforms have CONFIG_WATCHDOG disabled. There's a definition of reset_85xx_watchdog() in cpu/mpc85xx/cpu.c but no code that actually enables the watchdog. What should be done to make this feature working on these platforms ? Thanks a lot. Felix.

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[U-Boot] Pull request: u-boot-x86/master
by Graeme Russ 07 Mar '11

07 Mar '11

Wolfgang, I believe I missed the 2011.03 merge window - I'm happy for these to go into 2011.06 The following changes since commit d1a79b71f7c5fd9e277e0feb35f049289df1ed0e: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2011-02-11 21:23:33 +0100) are available in the git repository at: git://git.denx.de/u-boot-x86.git master Graeme Russ (32): x86: Fix definition of global_data struct for asm-offsets.c x86: Align config.mk and linker scripts with other arches eNET: Create distinct board configurations x86: Parametize values used in linker script sc520: Sort Makefile x86: Fix mangled umlauts x86: Add stack dump to register dump x86: Move Global Descriptor Table defines to processor.h x86: Add processor flags header from linux x86: Call early_board_init when warm booting x86: Make cpu init functions weak sc520: Define MMCR address in include file sc520: Move board specific settings to board init function sc520: Remove printf calls from cpu_init_f eNET: Fix eNET Interrupt Setup for Linux eNET: Add RTC support to eNET eNET: Define MMCR values in config.h eNET: Rearrange PAR assignments eNET: General code cleanup x86: Move initial gd to fixed location x86: Use Cache-As-RAM for initial stack sc520: Move RAM sizing code from asm to C x86: Defer setup of final stack x86: Move call to dram_init_f into board_init_f x86: Move test for cold boot into init functions x86: Move console initialisation into board_init_f x86: Fix incorrect usage of relocation offset x86: Split board_init_f() into init_fnc_t compatible functions x86: Rearrange function calls in board_init_f x86: Convert board_init_f to use an init_sequence sc520: Release CAR and enable caching eNET: Move initial Global Data into CAR arch/i386/config.mk | 15 +- arch/i386/cpu/config.mk | 10 +- arch/i386/cpu/cpu.c | 35 +- arch/i386/cpu/interrupts.c | 19 +- arch/i386/cpu/sc520/Makefile | 5 +- arch/i386/cpu/sc520/sc520.c | 148 +------ arch/i386/cpu/sc520/sc520_asm.S | 615 --------------------------- arch/i386/cpu/sc520/sc520_car.S | 94 ++++ arch/i386/cpu/sc520/sc520_sdram.c | 532 +++++++++++++++++++++++ arch/i386/cpu/start.S | 107 +++--- arch/i386/cpu/start16.S | 5 +- {board/eNET => arch/i386/cpu}/u-boot.lds | 24 +- arch/i386/include/asm/global_data.h | 21 +- arch/i386/include/asm/ic/sc520.h | 93 ++++- arch/i386/include/asm/processor-flags.h | 100 +++++ arch/i386/include/asm/processor.h | 9 +- arch/i386/include/asm/u-boot-i386.h | 3 + arch/i386/lib/board.c | 146 ++++--- arch/i386/lib/realmode.c | 8 +- board/eNET/config.mk | 6 +- board/eNET/eNET.c | 192 +++++---- board/eNET/eNET_start.S | 7 - board/eNET/eNET_start16.S | 15 +- boards.cfg | 3 +- drivers/rtc/mc146818.c | 6 + include/configs/eNET.h | 679 ++++++++++++++++++++++------- 26 files changed, 1699 insertions(+), 1198 deletions(-) delete mode 100644 arch/i386/cpu/sc520/sc520_asm.S create mode 100644 arch/i386/cpu/sc520/sc520_car.S create mode 100644 arch/i386/cpu/sc520/sc520_sdram.c rename {board/eNET => arch/i386/cpu}/u-boot.lds (75%) create mode 100644 arch/i386/include/asm/processor-flags.h

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[U-Boot] Your message to CCIE_Wireless awaits moderator approval
by ccie_wireless-bounces＠onlinestudylist.com 07 Mar '11

07 Mar '11

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[U-Boot] LDFLAGs patch breaks NAND boot
by Kumar Gala 07 Mar '11

07 Mar '11

I haven't debugged this beyond the fact that the following patch: commit 8aba9dceebb14144e07d19593111ee3a999c37fc Author: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Date: Thu Jan 6 10:23:54 2011 +0900 Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS ... Breaks NAND boot on 85xx platforms. I'm guessing there might have been some discussion on this subject already, and I'm just late to the game. However it seems like its something we need to figure out before v2011.03 is released. - k

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[U-Boot] [PATCH] powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
by Kumar Gala 07 Mar '11

07 Mar '11

From: Prabhakar Kushwaha <prabhakar(a)freescale.com> The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/p1021_serdes.c | 49 ++++++++++++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 8 +++++ drivers/pci/fsl_pci_init.c | 7 ++++ include/pci.h | 1 + 4 files changed, 64 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c index 457ab5d..1849c16 100644 --- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -26,6 +26,24 @@ #include <asm/immap_85xx.h> #include <asm/fsl_serdes.h> +typedef struct serdes_85xx { + u32 srdscr0; /* 0x00 - SRDS Control Register 0 */ + u32 srdscr1; /* 0x04 - SRDS Control Register 1 */ + u32 srdscr2; /* 0x08 - SRDS Control Register 2 */ + u32 srdscr3; /* 0x0C - SRDS Control Register 3 */ + u32 srdscr4; /* 0x10 - SRDS Control Register 4 */ +} serdes_85xx_t; +#define FSL_SRDSCR3_EIC0(x) (((x) & 0x1f) << 8) +#define FSL_SRDSCR3_EIC0_MASK FSL_SRDSCR3_EIC0(0x1f) +#define FSL_SRDSCR3_EIC1(x) (((x) & 0x1f) << 0) +#define FSL_SRDSCR3_EIC1_MASK FSL_SRDSCR3_EIC1(0x1f) +#define FSL_SRDSCR4_EIC2(x) (((x) & 0x1f) << 8) +#define FSL_SRDSCR4_EIC2_MASK FSL_SRDSCR4_EIC2(0x1f) +#define FSL_SRDSCR4_EIC3(x) (((x) & 0x1f) << 0) +#define FSL_SRDSCR4_EIC3_MASK FSL_SRDSCR4_EIC3(0x1f) +#define EIC_PCIE 0x13 +#define EIC_SGMII 0x04 + #define SRDS1_MAX_LANES 4 static u32 serdes1_prtcl_map; @@ -45,10 +63,13 @@ int is_serdes_configured(enum srds_prtcl prtcl) void fsl_serdes_init(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + u32 mask, val; debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); @@ -61,4 +82,30 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Init SERDES Receiver electrical idle detection control for PCIe */ + + /* Lane 0 is always PCIe 1 */ + mask = FSL_SRDSCR3_EIC0_MASK; + val = FSL_SRDSCR3_EIC0(EIC_PCIE); + + /* Lane 1 */ + if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) || + (serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) { + mask |= FSL_SRDSCR3_EIC1_MASK; + val |= FSL_SRDSCR3_EIC1(EIC_PCIE); + } + + /* Handle lanes 0 & 1 */ + clrsetbits_be32(&serdes->srdscr3, mask, val); + + /* Handle lanes 2 & 3 */ + if (srds_cfg == 0x6) { + mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK; + val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE); + clrsetbits_be32(&serdes->srdscr4, mask, val); + } + + /* 100 ms delay */ + udelay(100000); } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index c32c469..0529632 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -101,6 +101,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -110,6 +111,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -139,6 +141,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -148,6 +151,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -168,6 +172,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -176,6 +181,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -205,6 +211,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -214,6 +221,7 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 7b98e95..ab461b4 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -325,6 +325,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); +#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + temp32 = 0; + pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); + temp32 &= ~0x03; /* Disable ASPM */ + pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); + udelay(1); +#endif if (pcie_cap == PCI_CAP_ID_EXP) { pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); enabled = ltssm >= PCI_LTSSM_L0; diff --git a/include/pci.h b/include/pci.h index c6b264b..1284c42 100644 --- a/include/pci.h +++ b/include/pci.h @@ -306,6 +306,7 @@ #define PCI_DCR 0x54 /* PCIe Device Control Register */ #define PCI_DSR 0x56 /* PCIe Device Status Register */ #define PCI_LSR 0x5e /* PCIe Link Status Register */ +#define PCI_LCR 0x5c /* PCIe Link Control Register */ #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ #define PCI_LTSSM_L0 0x16 /* L0 state */ -- 1.7.2.3

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