March 2011 - U-Boot

[U-Boot] A gripe about HOSTCC in tools/env
by Jon Povey 10 Mar '11

10 Mar '11

I tried updating and rebuilding U-Boot today, I see that since abd315a1357ab05e82f0d61ebad666bc0d5378c3 "tools/env: use host build flags" I now have a fw_printenv built to run on my build host. useless. I read the discussion on the list and I appreciate that Mike may find problems packaging for weird and wonderful systems. But I don't understand why a patch was allowed to go in, or stay in, that produces counterintuitive unhelpful results by default for most users. It's not like the concept of CROSS_COMPILE has been removed from the entirety of U-Boot. U-Boot itself is still correctly built for my target. If I'm not wrong, "HOSTCC" is the compiler that should be used to build things to run on your build host. I can't see how that is possibly appropriate for tools/env. fw_printenv can only ever run on the target; if that is the host, then CROSS_COMPILE would be empty and it would be build correctly. For my purposes I think I will just shake my head and revert the Makefile locally. But I hope somebody thinks carefuly before any more changes like this. Whatever the changes that get made, things like this should still be built for the correct targets by default. That seems like a no-brainer to me. Sorry this email is mostly a whine. Sometimes I send patches. -- Jon Povey jon.povey(a)racelogic.co.uk Racelogic is a limited company registered in England. Registered number 2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB . The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network

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[U-Boot] Flashing Uboot into Nand
by Sanjeeva Kumara 10 Mar '11

10 Mar '11

Hi, I am working on Marvell PXA processor. I want to flash Uboot into NAND. Please let me know where and all I need make changes. Thanks & Regards Sanjeev Kumar Larsen & Toubro Limited Integrated Engineering Services KIADB Industrial Area, Hebbal-Hootagalli, Mysore - 570018 Telephone 91-821-2409010 Extn: 9010 E-mail ID : sanjeeva.kumara(a)lnties.com<mailto:sanjeeva.kumara@lnties.com> Larsen & Toubro Limited www.larsentoubro.com This Email may contain confidential or privileged information for the intended recipient (s) If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

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[U-Boot] Get high quality leads for your business.
by samuel＠marketingproteam.com 10 Mar '11

10 Mar '11

-------------------------------------------------------------------------------- This email newsletter was sent to you in graphical HTML format. If you're seeing this version, your email program prefers plain text emails. You can read the original version online: http://ymlp199.net/zhpYlA -------------------------------------------------------------------------------- High Quality Leads For FREE! Hey! I've got some INCREDIBLE news! And it's all about you MAKING MORE MONEY FASTER! Over the last couple of months, John and Shannon have been looking into ways to put our businesses on auto-drive. They wanted to automate lead generation and create ongoing streams of automatic income. They brought in a number of online and marketing experts and did some serious closed-door masterminding. And, they did it! Seriously. They uncovered and perfected the fastest way to generate an AUTOMATIC ongoing stream of cash while at the same time generating free leads for your business. I'm a network marketer at heart and I'm always looking for ways to do it faster, quicker, easier and of course, richer! We're all in business to make money and lots of it. The key to accelerated growth is knowing how to get high quality, high-converting leads. And, to do it for the absolutely least outlay of cash. So, here's the "skinny". We've uncovered the fastest way to generate leads for FREE. Seriously...and these are the highest quality leads you can possible get. Not only will this help you make more money (A LOT MORE MONEY), but you're going to have more leads than you even know what to do with :) Sign up for the free webinar to find out everything you need to know about generating high quality leads for FREE. www.MarketingProTeam.com _____________________________ Unsubscribe / Change Profile: http://ymlp199.net/u.php?id=gmuwjywgsgjhhqgh Powered by YourMailingListProvider

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[U-Boot] [PATCH v4] ARM: S5P: pwm driver support
by Donghwa Lee 10 Mar '11

10 Mar '11

This is common pwm driver of S5P. Signed-off-by: Donghwa Lee <dh09.lee(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- Changes since v3: - fixed pwm register offset - move definitions of register to header file Changes since v2: - Timer4 was blocked to access compare buffer register - code clean arch/arm/cpu/armv7/s5p-common/Makefile | 1 + arch/arm/cpu/armv7/s5p-common/pwm.c | 189 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-s5pc1xx/pwm.h | 19 +++ arch/arm/include/asm/arch-s5pc2xx/pwm.h | 19 +++ include/pwm.h | 31 +++++ 5 files changed, 259 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/s5p-common/pwm.c create mode 100644 include/pwm.h diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index 922cd95..ce0a41e 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)libs5p-common.o COBJS-y += cpu_info.o COBJS-y += timer.o +COBJS-$(CONFIG_PWM) += pwm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c new file mode 100644 index 0000000..ff95b84 --- /dev/null +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * Donghwa Lee <dh09.lee(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <errno.h> +#include <pwm.h> +#include <asm/io.h> +#include <asm/arch/pwm.h> +#include <asm/arch/clk.h> + +int pwm_enable(int pwm_id) +{ + const struct s5p_timer *pwm = + (struct s5p_timer *)samsung_get_base_timer(); + unsigned long tcon; + + tcon = readl(&pwm->tcon); + tcon |= TCON_START(pwm_id); + + writel(tcon, &pwm->tcon); + + return 0; +} + +void pwm_disable(int pwm_id) +{ + const struct s5p_timer *pwm = + (struct s5p_timer *)samsung_get_base_timer(); + unsigned long tcon; + + tcon = readl(&pwm->tcon); + tcon &= ~TCON_START(pwm_id); + + writel(tcon, &pwm->tcon); +} + +static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) +{ + unsigned long tin_parent_rate; + unsigned int div; + + tin_parent_rate = get_pwm_clk(); + + for (div = 2; div <= 16; div *= 2) { + if ((tin_parent_rate / (div << 16)) < freq) + return tin_parent_rate / div; + } + + return tin_parent_rate / 16; +} + +#define NS_IN_HZ (1000000000UL) + +int pwm_config(int pwm_id, int duty_ns, int period_ns) +{ + const struct s5p_timer *pwm = + (struct s5p_timer *)samsung_get_base_timer(); + unsigned int offset; + unsigned long tin_rate; + unsigned long tin_ns; + unsigned long period; + unsigned long tcon; + unsigned long tcnt; + unsigned long timer_rate_hz; + unsigned long tcmp; + + /* + * We currently avoid using 64bit arithmetic by using the + * fact that anything faster than 1GHz is easily representable + * by 32bits. + */ + if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) + return -ERANGE; + + if (duty_ns > period_ns) + return -EINVAL; + + period = NS_IN_HZ / period_ns; + + /* Check to see if we are changing the clock rate of the PWM */ + tin_rate = pwm_calc_tin(pwm_id, period); + timer_rate_hz = tin_rate; + + tin_ns = NS_IN_HZ / tin_rate; + tcnt = period_ns / tin_ns; + + /* Note, counters count down */ + tcmp = duty_ns / tin_ns; + tcmp = tcnt - tcmp; + + /* + * the pwm hw only checks the compare register after a decrement, + * so the pin never toggles if tcmp = tcnt + */ + if (tcmp == tcnt) + tcmp--; + + if (tcmp < 0) + tcmp = 0; + + /* Update the PWM register block. */ + offset = pwm_id * 3; + if (pwm_id < 4) { + writel(tcnt, &pwm->tcntb0 + offset); + writel(tcmp, &pwm->tcmpb0 + offset); + } + + tcon = readl(&pwm->tcon); + tcon |= TCON_UPDATE(pwm_id); + if (pwm_id < 4) + tcon |= TCON_AUTO_RELOAD(pwm_id); + else + tcon |= TCON4_AUTO_RELOAD; + writel(tcon, &pwm->tcon); + + tcon &= ~TCON_UPDATE(pwm_id); + writel(tcon, &pwm->tcon); + + return 0; +} + +int pwm_init(int pwm_id, int div, int invert) +{ + u32 val; + const struct s5p_timer *pwm = + (struct s5p_timer *)samsung_get_base_timer(); + unsigned long timer_rate_hz; + unsigned int offset, prescaler; + + /* + * Timer Freq(HZ) = + * PWM_CLK / { (prescaler_value + 1) * (divider_value) } + */ + + val = readl(&pwm->tcfg0); + if (pwm_id < 2) { + prescaler = PRESCALER_0; + val &= ~0xff; + val |= (prescaler & 0xff); + } else { + prescaler = PRESCALER_1; + val &= ~(0xff << 8); + val |= (prescaler & 0xff) << 8; + } + writel(val, &pwm->tcfg0); + val = readl(&pwm->tcfg1); + val &= ~(0xf << MUX_DIV_SHIFT(pwm_id)); + val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id); + writel(val, &pwm->tcfg1); + + timer_rate_hz = get_pwm_clk() / ((prescaler + 1) * + (div + 1)); + + timer_rate_hz = timer_rate_hz / 100; + + /* set count value */ + offset = pwm_id * 3; + writel(timer_rate_hz, &pwm->tcntb0 + offset); + + val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id)); + if (invert && (pwm_id < 4)) + val |= TCON_INVERTER(pwm_id); + writel(val, &pwm->tcon); + + pwm_enable(pwm_id); + + return 0; +} diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/include/asm/arch-s5pc1xx/pwm.h index 0369968..de4dbce 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h +++ b/arch/arm/include/asm/arch-s5pc1xx/pwm.h @@ -22,6 +22,18 @@ #ifndef __ASM_ARM_ARCH_PWM_H_ #define __ASM_ARM_ARCH_PWM_H_ +#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */ +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ + +/* Divider MUX */ +#define MUX_DIV_1 0 /* 1/1 period */ +#define MUX_DIV_2 1 /* 1/2 period */ +#define MUX_DIV_4 2 /* 1/4 period */ +#define MUX_DIV_8 3 /* 1/8 period */ +#define MUX_DIV_16 4 /* 1/16 period */ + +#define MUX_DIV_SHIFT(x) (x * 4) + /* Interval mode(Auto Reload) of PWM Timer 4 */ #define TCON4_AUTO_RELOAD (1 << 22) /* Update TCNTB4 */ @@ -29,6 +41,13 @@ /* start bit of PWM Timer 4 */ #define TCON4_START (1 << 20) +#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2) + +#define TCON_START(x) (1 << TCON_OFFSET(x)) +#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) +#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) +#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) + #ifndef __ASSEMBLY__ struct s5p_timer { unsigned int tcfg0; diff --git a/arch/arm/include/asm/arch-s5pc2xx/pwm.h b/arch/arm/include/asm/arch-s5pc2xx/pwm.h index 0369968..de4dbce 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/pwm.h +++ b/arch/arm/include/asm/arch-s5pc2xx/pwm.h @@ -22,6 +22,18 @@ #ifndef __ASM_ARM_ARCH_PWM_H_ #define __ASM_ARM_ARCH_PWM_H_ +#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */ +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ + +/* Divider MUX */ +#define MUX_DIV_1 0 /* 1/1 period */ +#define MUX_DIV_2 1 /* 1/2 period */ +#define MUX_DIV_4 2 /* 1/4 period */ +#define MUX_DIV_8 3 /* 1/8 period */ +#define MUX_DIV_16 4 /* 1/16 period */ + +#define MUX_DIV_SHIFT(x) (x * 4) + /* Interval mode(Auto Reload) of PWM Timer 4 */ #define TCON4_AUTO_RELOAD (1 << 22) /* Update TCNTB4 */ @@ -29,6 +41,13 @@ /* start bit of PWM Timer 4 */ #define TCON4_START (1 << 20) +#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2) + +#define TCON_START(x) (1 << TCON_OFFSET(x)) +#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1)) +#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2)) +#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3)) + #ifndef __ASSEMBLY__ struct s5p_timer { unsigned int tcfg0; diff --git a/include/pwm.h b/include/pwm.h new file mode 100644 index 0000000..13acf85 --- /dev/null +++ b/include/pwm.h @@ -0,0 +1,31 @@ +/* + * header file for pwm driver. + * + * Copyright (c) 2011 samsung electronics + * Donghwa Lee <dh09.lee(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _pwm_h_ +#define _pwm_h_ + +int pwm_init (int pwm_id, int div, int invert); +int pwm_config (int pwm_id, int duty_ns, int period_ns); +int pwm_enable (int pwm_id); +void pwm_disable (int pwm_id); + +#endif /* _pwm_h_ */ -- 1.6.0.4

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[U-Boot] common/update.c ITB update code refactoring (no new file)
by Dvorkin Dmitry 10 Mar '11

10 Mar '11

common/update.c used to update flash with ITB image. With this patch it can also use any templated nash commands to load and save blobs. Also it adds nand as possible target for update. Usage example: // to load itb from usb mass-storage device and save it into nand using nash commands setenv updatefile updateimage.itb setenv loadaddr 0x72000000 setenv upditb_load_method cmd setenv upditb_cmd_load_pre usb start setenv upditb_cmd_load fatload usb 0:1 {load_to} {file} setenv upditb_save_method cmd setenv upditb_cmd_save nand write {addr_src} {addr_dst} {img_size} // better way to do the same task: setenv updatefile updateimage.itb setenv loadaddr 0x72000000 setenv upditb_load_method cmd setenv upditb_cmd_load_pre usb start setenv upditb_cmd_load fatload usb 0:1 {load_to} {file} setenv upditb_save_method nand it directly calls write_nand_skip_bad() to save blobs. Better because of kernel image usually is not nand-page aligned, end-of-kernel blob does not fit into nand page borders, "nand" method trying to fix it. diff -urN a/common/main.c b/common/main.c --- a/common/main.c 2010-09-29 01:20:55.000000000 +0400 +++ b/common/main.c 2011-03-02 23:34:12.000000000 +0300 @@ -56,9 +56,9 @@ extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -#if defined(CONFIG_UPDATE_TFTP) -void update_tftp (void); -#endif /* CONFIG_UPDATE_TFTP */ +#if defined(CONFIG_UPDATE) +void update_itb (void); +#endif /* CONFIG_UPDATE */ #define MAX_DELAY_STOP_STR 32 @@ -365,9 +365,9 @@ } #endif /* CONFIG_PREBOOT */ -#if defined(CONFIG_UPDATE_TFTP) - update_tftp (); -#endif /* CONFIG_UPDATE_TFTP */ +#if defined(CONFIG_UPDATE) + update_itb (); +#endif /* CONFIG_UPDATE */ #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) s = getenv ("bootdelay"); diff -urN a/common/Makefile b/common/Makefile --- a/common/Makefile 2010-09-29 01:20:55.000000000 +0400 +++ b/common/Makefile 2011-03-10 09:12:25.546803490 +0300 @@ -164,7 +164,7 @@ COBJS-$(CONFIG_LCD) += lcd.o COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o -COBJS-$(CONFIG_UPDATE_TFTP) += update.o +COBJS-$(CONFIG_UPDATE) += update.o COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o diff -urN a/common/update.c b/common/update.c --- a/common/update.c 2011-02-28 15:46:10.000000000 +0300 +++ b/common/update.c 2011-03-07 16:27:02.000000000 +0300 @@ -4,6 +4,10 @@ * Written by: Rafal Czubak <rcz(a)semihalf.com> * Bartlomiej Sieka <tur(a)semihalf.com> * + * (C) Copyright 2011 Tibbo Tech. + * Code refactoring, Cmd and Nand load/save features: + * Dvorkin Dmitry <dvorkin(a)tibbo.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -30,12 +34,13 @@ #error "CONFIG_FIT and CONFIG_OF_LIBFDT are required for auto-update feature" #endif -#if defined(CONFIG_SYS_NO_FLASH) -#error "CONFIG_SYS_NO_FLASH defined, but FLASH is required for auto-update feature" -#endif - #include <command.h> +#if !defined(CONFIG_SYS_NO_FLASH) #include <flash.h> +#endif +#if defined(CONFIG_CMD_NAND) +#include <nand.h> +#endif #include <net.h> #include <malloc.h> @@ -43,16 +48,16 @@ #define UPDATE_FILE_ENV "updatefile" /* set configuration defaults if needed */ -#ifndef CONFIG_UPDATE_LOAD_ADDR -#define CONFIG_UPDATE_LOAD_ADDR 0x100000 +#ifndef CONFIG_UPDITB_LOAD_ADDR +#define CONFIG_UPDITB_LOAD_ADDR 0x100000 #endif -#ifndef CONFIG_UPDATE_TFTP_MSEC_MAX -#define CONFIG_UPDATE_TFTP_MSEC_MAX 100 +#ifndef CONFIG_UPDITB_TFTP_MSEC_MAX +#define CONFIG_UPDITB_TFTP_MSEC_MAX 100 #endif -#ifndef CONFIG_UPDATE_TFTP_CNT_MAX -#define CONFIG_UPDATE_TFTP_CNT_MAX 0 +#ifndef CONFIG_UPDITB_TFTP_CNT_MAX +#define CONFIG_UPDITB_TFTP_CNT_MAX 0 #endif extern ulong TftpRRQTimeoutMSecs; @@ -60,11 +65,91 @@ extern flash_info_t flash_info[]; extern ulong load_addr; +extern int run_command (const char *cmd, int flag); + static uchar *saved_prot_info; -static int update_load(char *filename, ulong msec_max, int cnt_max, ulong addr) +enum XLAT_ST { + XLAT_ST_D, /* default */ + XLAT_ST_S, /* skip \ */ + XLAT_ST_B, /* begin attr name */ + XLAT_ST_A, /* in attr name */ + XLAT_ST_s, /* skip \} in attr name */ + XLAT_ST_E, /* end attr name */ +}; + +enum XLAT_CT { + XLAT_CT_DEF, + XLAT_CT_BKS, + XLAT_CT_BEG, + XLAT_CT_END, +}; + +enum XLAT_ST xlat_st_tbl[ 6][ 4] = { + // def \\ { } + { XLAT_ST_D, XLAT_ST_S, XLAT_ST_B, XLAT_ST_D }, // _ST_D + { XLAT_ST_D, XLAT_ST_D, XLAT_ST_D, XLAT_ST_D }, // _ST_S + { XLAT_ST_A, XLAT_ST_A, XLAT_ST_A, XLAT_ST_E }, // _ST_B + { XLAT_ST_A, XLAT_ST_s, XLAT_ST_A, XLAT_ST_E }, // _ST_A + { XLAT_ST_A, XLAT_ST_A, XLAT_ST_A, XLAT_ST_A }, // _ST_s + { XLAT_ST_D, XLAT_ST_S, XLAT_ST_B, XLAT_ST_D }, // _ST_E +}; + +typedef char *( *xlat_cfpt)( void *_data, char *_as, ulong _al, ulong *_rlen); + +static int Xlat_R( const char *_i, ulong _il, char *_o, ulong _ol, + xlat_cfpt _cfp, void *_data) { + ulong i = -1, oi = 0; + ulong rlen, ret = 0; + char *tks; + ulong tkl; + char *repl_av = NULL; + unsigned char c; + enum XLAT_CT ctype; + enum XLAT_ST curst = XLAT_ST_D; + + tks = NULL; tkl = 0; + while ( ++i < _il && ( c = _i[ i]) != '\0') { +//printf( "x:%d\n", i); + ctype = XLAT_CT_DEF; + if ( c == '\\') ctype = XLAT_CT_BKS; + if ( c == '{' ) ctype = XLAT_CT_BEG; + if ( c == '}' ) ctype = XLAT_CT_END; + curst = xlat_st_tbl[ curst][ ctype]; + switch ( curst) { + case XLAT_ST_s: + case XLAT_ST_S: break; + case XLAT_ST_D: if ( _o) _o[ oi++] = c; break; + case XLAT_ST_B: tks = ( _i + i + 1); tkl = 0; break; + case XLAT_ST_A: tkl++; break; + case XLAT_ST_E: +// printf( "AVP:%s\n", tmp_attr); + // macro name ended + ret++; + // if output buffer == NULL - return number of potential subs + if ( !_o) break; + repl_av = NULL; rlen = 0; + if ( _cfp) repl_av = _cfp( _data, tks, tkl, &rlen); + // actually replace + if ( repl_av != NULL) { memcpy( _o + oi, repl_av, rlen); oi += rlen; } + // if replace to NULL + if ( repl_av == NULL && rlen > 0) break; + // if no replace found - copy {text} to output - safe for future + if ( repl_av == NULL && rlen < 1) { + _o[ oi++] = '{'; + memcpy( _o + oi, tks, tkl); oi += tkl; + _o[ oi++] = '}'; } + break; + } // end of switch + if ( tkl >= _ol) return( ret); + } + return( ret); } + +static int update_load_tftp(char *filename, ulong addr) { int size, rv; + ulong msec_max = CONFIG_UPDITB_TFTP_MSEC_MAX; + int cnt_max = CONFIG_UPDITB_TFTP_CNT_MAX; ulong saved_timeout_msecs; int saved_timeout_count; char *saved_netretry, *saved_bootfile; @@ -109,6 +194,74 @@ return rv; } +typedef struct Xlate_load_T { + char *file; + ulong load_to; +} Xlate_load_t; + +char *Xlate_load( void *_data, char *_as, ulong _al, ulong *_rlen) { + Xlate_load_t *Xdp = ( Xlate_load_t *)_data; + char xs[ 64]; + memset( xs, 0, 64); + if ( _al == 4 && memcmp( _as, "file", 4) == 0) sprintf( xs, "%s", Xdp->file); + if ( _al == 7 && memcmp( _as, "load_to", 7) == 0) sprintf( xs, "0x%08x", Xdp->load_to); + *_rlen = strlen( xs); + return( xs); } + +static int update_load_cmd( char *_file, ulong _addr) { + char *cmd; + char cmdx[ 1024]; + Xlate_load_t Xd = { .file = _file, .load_to = _addr }; + if ( ( cmd = getenv( "upditb_cmd_load_pre")) != NULL) { + memset( cmdx, 0, 1024); + Xlat_R( cmd, strlen( cmd), cmdx, 1024, Xlate_load, &Xd); + printf( "Preload cmd template:%s\n", cmd); + printf( "Xlated to:%s\n", cmdx); + /* prepare for loading into RAM, 'usb start' for ex. */ + if ( run_command( cmdx, 0) == -1) return( 1); + } + /* load to RAM. 'fatload usb 0:1 <address> <file>' for ex. */ + if ( ( cmd = getenv( "upditb_cmd_load")) != NULL) { + memset( cmdx, 0, 1024); + Xlat_R( cmd, strlen( cmd), cmdx, 1024, Xlate_load, &Xd); + printf( "Load cmd template:%s\n", cmd); + printf( "Xlated to:%s\n", cmdx); + /* prepare for loading into RAM, 'usb start' for ex. */ + if ( run_command( cmdx, 0) == -1) return( 1); + } + return( 0); } + +typedef struct Xlate_flash_T { + ulong a_src; + ulong a_dst; + ulong size; +} Xlate_flash_t; + +char *Xlate_flash( void *_data, char *_as, ulong _al, ulong *_rlen) { + Xlate_flash_t *Xdp = ( Xlate_flash_t *)_data; + char xs[ 64]; + memset( xs, 0, 64); + if ( _al == 8 && memcmp( _as, "addr_src", 8) == 0) sprintf( xs, "0x%08x", Xdp->a_src); + if ( _al == 8 && memcmp( _as, "addr_dst", 8) == 0) sprintf( xs, "0x%08x", Xdp->a_dst); + if ( _al == 8 && memcmp( _as, "img_size", 8) == 0) sprintf( xs, "0x%08x", Xdp->size); + *_rlen = strlen( xs); + return( xs); } + +static int update_s_cmd( ulong _addr_source, ulong _addr_first, ulong _size) { + char *cmdc; + char cmdcx[ 1024]; + Xlate_flash_t Xd = { .a_src = _addr_source, .a_dst = _addr_first, .size = _size }; + printf( "%s()\n", __FUNCTION__); + if ( ( cmdc = getenv( "upditb_cmd_save")) == NULL) return( 1); + memset( cmdcx, 0, 1024); + Xlat_R( cmdc, strlen( cmdc), cmdcx, 1024, Xlate_flash, &Xd); + printf( "Save cmd template:%s\n", cmdc); + printf( "Xlated to:%s\n", cmdcx); + /* save to target, nand write {addr_src} {addr_dst} {img_size} for ex. */ + if ( run_command( cmdcx, 0) == -1) return( 1); + return( 0); } + +#if !defined(CONFIG_SYS_NO_FLASH) static int update_flash_protect(int prot, ulong addr_first, ulong addr_last) { uchar *sp_info_ptr; @@ -181,10 +334,11 @@ return 0; } -static int update_flash(ulong addr_source, ulong addr_first, ulong size) +static int update_s_flash(ulong addr_source, ulong addr_first, ulong size) { ulong addr_last = addr_first + size - 1; + printf( "%s()\n", __FUNCTION__); /* round last address to the sector boundary */ if (flash_sect_roundb(&addr_last) > 0) return 1; @@ -221,6 +375,25 @@ return 0; } +#endif + +#if defined(CONFIG_CMD_NAND) +static int update_s_nand( ulong _a_src, ulong _a_dst, size_t _size) +{ + int err; + size_t len = _size; + size_t tl; + tl = nand_info[ 0].writesize; + printf( "%s()\n", __FUNCTION__); + if ( ( _size % tl) != 0) { + printf( "padding %d with %d bytes\n", _size, ( tl - ( _size % tl))); + len = _size += ( tl - ( _size % tl)); + printf( "new size is %d bytes\n", _size); + } + err = nand_write_skip_bad( &nand_info[ 0], _a_dst, &len, _a_src); + if ( err != 0) return( 1); + return( 0); } +#endif static int update_fit_getparams(const void *fit, int noffset, ulong *addr, ulong *fladdr, ulong *size) @@ -238,15 +411,23 @@ return 0; } -void update_tftp(void) +void update_itb(void) { char *filename, *env_addr; + char *method_load, *method_save, *ts; int images_noffset, ndepth, noffset; ulong update_addr, update_fladdr, update_size; ulong addr; void *fit; + int err, sl; - printf("Auto-update from TFTP: "); + /* update method: tftp or something else */ + ts = method_load = getenv( "upditb_load_method"); + if ( method_load == NULL) method_load = "none"; + printf( "Auto-update ITB load method:%s\n", method_load); + if ( ts == NULL) return; + method_save = getenv( "upditb_save_method"); + if ( method_save == NULL) method_save = "flash"; /* get the file name of the update file */ filename = getenv(UPDATE_FILE_ENV); @@ -257,31 +438,68 @@ } printf("trying update file '%s'\n", filename); +#ifdef CONFIG_LCD + lcd_printf( "Loading auto-update file '%s'...", filename); +#endif /* get load address of downloaded update file */ if ((env_addr = getenv("loadaddr")) != NULL) addr = simple_strtoul(env_addr, NULL, 16); else - addr = CONFIG_UPDATE_LOAD_ADDR; - + addr = CONFIG_UPDITB_LOAD_ADDR; - if (update_load(filename, CONFIG_UPDATE_TFTP_MSEC_MAX, - CONFIG_UPDATE_TFTP_CNT_MAX, addr)) { - printf("Can't load update file, aborting auto-update\n"); - return; + err = -1; + sl = strlen( method_load); + if ( sl == 4 && strcmp( method_load, "tftp") == 0) err = update_load_tftp( filename, addr); + if ( sl == 3 && strcmp( method_load, "cmd" ) == 0) err = update_load_cmd( filename, addr); + switch ( err) { + case -1: +#ifdef CONFIG_LCD + lcd_printf( "ERR-1\n"); +#endif + printf( "No such method '%s', aborting auto-update\n", method_load); + return; + break; + case 0: /* it's OK */ +#ifdef CONFIG_LCD + lcd_printf( "OK\n"); +#endif + break; + default: +#ifdef CONFIG_LCD + lcd_printf( "ERR\n"); +#endif + printf( "Can't load update file, aborting auto-update\n"); + return; + break; } +#ifdef CONFIG_LCD + lcd_printf( "Auto-update file is loaded, checking..."); +#endif fit = (void *)addr; if (!fit_check_format((void *)fit)) { printf("Bad FIT format of the update file, aborting " "auto-update\n"); +#ifdef CONFIG_LCD + lcd_printf( "ERR\n"); +#endif return; } +#ifdef CONFIG_LCD + lcd_printf( "OK\n"); +#endif /* process updates */ images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); +#ifdef CONFIG_LCD + err = fit_get_desc( fit, 0, &ts); + if ( err) ts = "(no description)"; + lcd_printf( "Processing %s...\n", ts); +#endif +fit_print_contents( (void *)fit); ndepth = 0; noffset = fdt_next_node(fit, images_noffset, &ndepth); while (noffset >= 0 && ndepth > 0) { @@ -303,10 +521,33 @@ "aborting\n"); goto next_node; } - if (update_flash(update_addr, update_fladdr, update_size)) { +fit_image_print( fit, noffset, ""); +#ifdef CONFIG_LCD + err = fit_get_desc( fit, noffset, &ts); + if ( err) ts = "(no description)"; + lcd_printf( "Flashing %s...", ts); +#endif + sl = strlen( method_save); + err = -1; +#if !defined(CONFIG_SYS_NO_FLASH) + if ( sl == 5 && strcmp( method_save, "flash") == 0) err = update_s_flash(update_addr, update_fladdr, update_size); +#endif + if ( sl == 3 && strcmp( method_save, "cmd" ) == 0) err = update_s_cmd( update_addr, update_fladdr, update_size); +#if defined(CONFIG_CMD_NAND) + if ( sl == 4 && strcmp( method_save, "nand") == 0) err = update_s_nand(update_addr, update_fladdr, update_size); +#endif + /* fallback if method not found */ + if ( err == -1) err = update_s_flash(update_addr, update_fladdr, update_size); + if ( err) { printf("Error: can't flash update (%ld %ld %ld), aborting\n", update_addr, update_fladdr, update_size); +#ifdef CONFIG_LCD + lcd_printf( "ERR\n"); +#endif goto next_node; } +#ifdef CONFIG_LCD + lcd_printf( "OK\n"); +#endif next_node: noffset = fdt_next_node(fit, noffset, &ndepth); } diff -urN a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h --- a/include/configs/at91sam9m10g45ek.h 2011-02-28 15:46:10.000000000 +0300 +++ b/include/configs/at91sam9m10g45ek.h 2011-03-02 23:34:12.000000000 +0300 @@ -92,9 +92,11 @@ /* update feature */ #define CONFIG_FIT 1 #define CONFIG_OF_LIBFDT 1 -#define CONFIG_UPDATE_TFTP 1 -//#define CONFIG_UPDATE_CNT_MAX 0 -//#define CONFIG_UPDATE_MSEC_MAX 100 +#define CONFIG_UPDITB 1 +#define CONFIG_UPDITB_TFTP 1 +//#define CONFIG_UPDITB_CNT_MAX 0 +//#define CONFIG_UPDITB_MSEC_MAX 100 +#define CONFIG_UPDITB_LOAD_ADDR 0x72000000 /* * Command line configuration. diff -urN a/README b/README --- a/README 2010-09-29 01:20:55.000000000 +0400 +++ b/README 2011-03-02 23:34:12.000000000 +0300 @@ -2108,10 +2108,11 @@ -150 common/cmd_nand.c Incorrect FIT image format 151 common/cmd_nand.c FIT image format OK -- Automatic software updates via TFTP server - CONFIG_UPDATE_TFTP - CONFIG_UPDATE_TFTP_CNT_MAX - CONFIG_UPDATE_TFTP_MSEC_MAX +- Automatic software updates via ITB structure + CONFIG_UPDITB + CONFIG_UPDITB_TFTP + CONFIG_UPDITB_TFTP_CNT_MAX + CONFIG_UPDITB_TFTP_MSEC_MAX These options enable and control the auto-update feature; for a more detailed description refer to doc/README.update.

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[U-Boot] [RFC] mpc83xx/speed.c
by Andre Schwarz 09 Mar '11

09 Mar '11

I have an issue with i2c-1 bus speed not being calculated correctly on MPC8377. arch/powerpc/cpu/mpc83xx/speed.c lines 320+ are : #if defined(CONFIG_MPC834x) i2c1_clk = tsec2_clk; #elif defined(CONFIG_MPC8360) i2c1_clk = csb_clk; #elif defined(CONFIG_MPC832x) i2c1_clk = enc_clk; #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; #endif I don't have CONFIG_FSL_ESDHC set ... we're running SPI. i2c1_clk doesn't get set. According to the manual the i2c-1 clock source is somewhat ambiguous (MPC8379RM p.211) : a. I2C1 clock is tied to SDHCCM b. I2C1 clock is tied to ENCCM I have CSB=333MHz and ENCCM=3 resulting in 111MHz i2c1 clock. Would it be appropriate to add #elif defined(CONFIG_MPC837x) i2c1_clk = enc_clk; before the final #endif ? BTW: Does anybody know which clock setting (SDHCCM or ENCCM) has priority ? -- Regards, Andre MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

1 0

[U-Boot] [PATCH] net: axi_ethernet: Add driver to u-boot
by Michal Simek 09 Mar '11

09 Mar '11

Add the first axi_ethernet driver for little-endian Microblaze. Signed-off-by: Michal Simek <monstr(a)monstr.eu> --- .../xilinx/microblaze-generic/microblaze-generic.c | 4 + drivers/net/Makefile | 1 + drivers/net/xilinx_axi_emac.c | 529 ++++++++++++++++++++ include/configs/microblaze-generic.h | 3 + 4 files changed, 537 insertions(+), 0 deletions(-) create mode 100644 drivers/net/xilinx_axi_emac.c diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 0102c9e..b38cf3d 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -73,6 +73,10 @@ int board_eth_init(bd_t *bis) { int ret = 0; +#ifdef CONFIG_XILINX_AXIEMAC + ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, + XILINX_AXIDMA_BASEADDR); +#endif #ifdef CONFIG_XILINX_EMACLITE ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR); #endif diff --git a/drivers/net/Makefile b/drivers/net/Makefile index d720e27..4c77062 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -83,6 +83,7 @@ COBJS-$(CONFIG_TSEC_ENET) += tsec.o COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o +COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c new file mode 100644 index 0000000..75ebac7 --- /dev/null +++ b/drivers/net/xilinx_axi_emac.c @@ -0,0 +1,529 @@ +/* + * Copyright (C) 2011 Michal Simek <monstr(a)monstr.eu> + * Copyright (C) 2011 PetaLogix + * Copyright (C) 2010 Xilinx, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <net.h> +#include <malloc.h> +#include <asm/io.h> + +/* Axi Ethernet registers offset */ +#define XAE_IS_OFFSET 0x0000000C /* Interrupt status */ +#define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */ +#define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */ +#define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */ +#define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */ +#define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */ +#define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */ +#define XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */ + +/* Link setup */ +#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ +#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ +#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ +#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ + +/* Interrupt Status/Enable/Mask Registers bit definitions */ +#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ +#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ + +/* Receive Configuration Word 1 (RCW1) Register bit definitions */ +#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */ + +/* Transmitter Configuration (TC) Register bit definitions */ +#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */ + +/* + * Station address bits [47:32] + * Station address bits [31:0] are stored in register UAW0 + */ +#define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */ +#define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */ +#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF + +/* MDIO Management Configuration (MC) Register bit definitions */ +#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/ + +/* MDIO Management Control Register (MCR) Register bit definitions */ +#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */ +#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */ +#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */ +#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */ +#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */ +#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */ +#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */ +#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */ + +#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */ + +/* DMA macros */ +/* Bitmasks of XAXIDMA_CR_OFFSET register */ +#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */ +#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */ + +/* Bitmasks of XAXIDMA_SR_OFFSET register */ +#define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */ + +/* Bitmask for interrupts */ +#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */ +#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */ +#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */ + +/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */ +#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ +#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ + + +#define ENET_MAX_MTU PKTSIZE_ALIGN +#define DMAALIGN 128 + +static u8 RxFrame[ENET_MAX_MTU] __attribute((aligned(DMAALIGN))) ; + +/* reflect dma offsets */ +struct axidma_reg { + u32 control; /* DMACR */ + u32 status; /* DMASR */ + u32 current; /* CURDESC */ + u32 reserved; + u32 tail; /* TAILDESC */ +}; + +/* Private driver structures */ +struct axidma_priv { + struct axidma_reg *dmatx; + struct axidma_reg *dmarx; +}; + +/* BD descriptors */ +typedef struct axidma_bd { + u32 next; /* Next descriptor pointer */ + u32 reserved1; + u32 phys; /* Buffer address */ + u32 reserved2; + u32 reserved3; + u32 reserved4; + u32 cntrl; /* Control */ + u32 status; /* Status */ + u32 app0; + u32 app1; /* TX start << 16 | insert */ + u32 app2; /* TX csum seed */ + u32 app3; + u32 app4; + u32 sw_id_offset; + u32 reserved5; + u32 reserved6; +} axidma_bd __attribute((aligned(DMAALIGN))); + +/* Static BDs - driver uses only one BD */ +static axidma_bd tx_bd; +static axidma_bd rx_bd; + +/* Use MII register 1 (MII status register) to detect PHY */ +#define PHY_DETECT_REG 1 + +/* Mask used to verify certain PHY features (or register contents) + * in the register above: + * 0x1000: 10Mbps full duplex support + * 0x0800: 10Mbps half duplex support + * 0x0008: Auto-negotiation support + */ +#define PHY_DETECT_MASK 0x1808 + +static u16 phy_read(struct eth_device *dev, u32 PhyAddress, u32 RegisterNum) +{ + u32 MdioCtrlReg = 0; + + /* Wait till MDIO interface is ready to accept a new transaction. */ + while (!(in_be32(dev->iobase + XAE_MDIO_MCR_OFFSET) + & XAE_MDIO_MCR_READY_MASK)) + ; + + MdioCtrlReg = ((PhyAddress << XAE_MDIO_MCR_PHYAD_SHIFT) & + XAE_MDIO_MCR_PHYAD_MASK) | + ((RegisterNum << XAE_MDIO_MCR_REGAD_SHIFT) + & XAE_MDIO_MCR_REGAD_MASK) | + XAE_MDIO_MCR_INITIATE_MASK | + XAE_MDIO_MCR_OP_READ_MASK; + + out_be32(dev->iobase + XAE_MDIO_MCR_OFFSET, MdioCtrlReg); + + /* Wait till MDIO transaction is completed. */ + while (!(in_be32(dev->iobase + XAE_MDIO_MCR_OFFSET) + & XAE_MDIO_MCR_READY_MASK)) + ; + + /* Read data */ + return (u16) in_be32(dev->iobase + XAE_MDIO_MRD_OFFSET); +} + +/* setting axi emac and phy to proper setting */ +static void setup_phy(struct eth_device *dev) +{ + int i; + unsigned retries = 100; + u16 PhyReg; + u16 PhyReg2; + int PhyAddr = -1; + u32 emmc_reg; + + debug("detecting phy address\n"); + + /* detect the PHY address */ + for (PhyAddr = 31; PhyAddr >= 0; PhyAddr--) { + PhyReg = phy_read(dev, PhyAddr, PHY_DETECT_REG); + + if ((PhyReg != 0xFFFF) && + ((PhyReg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + + debug("Found valid phy address, %d\n", PhyReg); + break; + } + } + + debug("waiting for the phy to be up\n"); + + /* wait for link up and autonegotiation completed */ + while (retries-- > 0) { + if ((PhyReg & 0x24) == 0x24) + break; + } + + /* get PHY id */ + PhyReg = phy_read(dev, PhyAddr, 2); + PhyReg2 = phy_read(dev, PhyAddr, 2); + i = (PhyReg << 16) | PhyReg2; + debug("LL_TEMAC: Phy ID 0x%x\n", i); + + /* Marwell 88e1111 id - ml50x, 0x1410141 id - sp605 */ + if ((i == 0x1410cc2) || (i == 0x1410141)) { + debug("Marvell PHY recognized\n"); + + /* Setup the emac for the phy speed */ + emmc_reg = in_be32(dev->iobase + XAE_EMMC_OFFSET); + emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; + + PhyReg = phy_read(dev, PhyAddr, 17); + + if ((PhyReg & 0x8000) == 0x8000) { + emmc_reg |= XAE_EMMC_LINKSPD_1000; + printf("1000BASE-T\n"); + } else if ((PhyReg & 0x4000) == 0x4000) { + printf("100BASE-T\n"); + emmc_reg |= XAE_EMMC_LINKSPD_100; + } else { + printf("10BASE-T\n"); + emmc_reg |= XAE_EMMC_LINKSPD_10; + } + + /* Write new speed setting out to Axi Ethernet */ + out_be32(dev->iobase + XAE_EMMC_OFFSET, emmc_reg); + + /* + * Setting the operating speed of the MAC needs a delay. There + * doesn't seem to be register to poll, so please consider this + * during your application design. + */ + udelay(1); + } +} + +/* STOP DMA transfers */ +static void axiemac_halt(struct eth_device *dev) +{ + struct axidma_priv *dma = dev->priv; + + if (dev->state) { + /* Stop the hardware */ + dma->dmatx->control &= ~XAXIDMA_CR_RUNSTOP_MASK; + dma->dmarx->control &= ~XAXIDMA_CR_RUNSTOP_MASK; + dev->state = 0; + } + debug("axiemac halted\n"); +} + +static void axi_ethernet_init(struct eth_device *dev) +{ + /* + * Check the status of the MgtRdy bit in the interrupt status + * registers. This must be done to allow the MGT clock to become stable + * for the Sgmii and 1000BaseX PHY interfaces. No other register reads + * will be valid until this bit is valid. + * The bit is always a 1 for all other PHY interfaces. + */ + u32 timeout = 200; + while (timeout && + (!(in_be32(dev->iobase + XAE_IS_OFFSET) & XAE_INT_MGTRDY_MASK))) + timeout--; + + if (!timeout) + printf("%s: Timeout\n", __func__); + + /* Stop the device and reset HW */ + /* Disable interrupts */ + out_be32(dev->iobase + XAE_IE_OFFSET, 0); + + /* Disable the receiver */ + out_be32(dev->iobase + XAE_RCW1_OFFSET, + in_be32(dev->iobase + XAE_RCW1_OFFSET) & ~XAE_RCW1_RX_MASK); + + /* + * Stopping the receiver in mid-packet causes a dropped packet + * indication from HW. Clear it. + */ + /* set the interrupt status register to clear the interrupt */ + out_be32(dev->iobase + XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK); + + /* Setup HW */ + /* Set default MDIO divisor */ + out_be32(dev->iobase + XAE_MDIO_MC_OFFSET, + (u32) XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK); + + debug("XAxiEthernet InitHw: done\n"); +} + +static void setup_mac(struct eth_device *dev) +{ + /* Set the MAC address */ + int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) | + (dev->enetaddr[1] << 8) | (dev->enetaddr[0])); + out_be32(dev->iobase + XAE_UAW0_OFFSET, val); + + val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ; + val |= in_be32(dev->iobase + XAE_UAW1_OFFSET) + & ~XAE_UAW1_UNICASTADDR_MASK; + out_be32(dev->iobase + XAE_UAW1_OFFSET, val); +} + +/* Reset DMA engine */ +static void axi_dma_init(struct eth_device *dev) +{ + struct axidma_priv *dma = dev->priv; + + /* Reset the engine so the hardware starts from a known state */ + dma->dmatx->control = XAXIDMA_CR_RESET_MASK; + dma->dmarx->control = XAXIDMA_CR_RESET_MASK; + + /* At the initialization time, hardware should finish reset quickly */ + u32 timeout = 500; + while (timeout--) { + /* Check transmit/receive channel */ + /* Reset is done when the reset bit is low */ + if (!(dma->dmatx->control | dma->dmarx->control) + & XAXIDMA_CR_RESET_MASK) + break; + timeout -= 1; + } + + if (!timeout) + printf("%s: Timeout\n", __func__); +} + +static int axiemac_init(struct eth_device *dev, bd_t * bis) +{ + struct axidma_priv *dma = dev->priv; + debug("axi emac init started\n"); + + /* + * Initialize AXIDMA engine. AXIDMA engine must be initialized before + * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is + * reset, and since AXIDMA reset line is connected to AxiEthernet, this + * would ensure a reset of AxiEthernet. + */ + axi_dma_init(dev); + + /* Initialize AxiEthernet hardware. */ + axi_ethernet_init(dev); + setup_mac(dev); + + /* Start the hardware */ + dma->dmarx->control |= XAXIDMA_CR_RUNSTOP_MASK; + /* Start DMA RX channel. Now it's ready to receive data.*/ + dma->dmarx->current = (u32)&rx_bd; + + /* Disable all RX interrupts before RxBD space setup */ + dma->dmarx->control &= ~(XAXIDMA_IRQ_ALL_MASK & XAXIDMA_IRQ_ALL_MASK); + + /* Setup the BD. */ + memset((void *) &rx_bd, 0, sizeof(axidma_bd)); + rx_bd.next = (u32)&rx_bd; + rx_bd.phys = (u32)&RxFrame; + rx_bd.cntrl = sizeof(RxFrame); + /* Flush the last BD so DMA core could see the updates */ + flush_cache((u32)&rx_bd, sizeof(axidma_bd)); + + /* it is necessary to flush RxFrame because if you don't do it + * then cache can contain uninitialized data */ + flush_cache((u32)&RxFrame, sizeof(RxFrame)); + + /* Rx BD is ready - start */ + dma->dmarx->tail = (u32)&rx_bd; + + /* enable TX */ + out_be32(dev->iobase + XAE_TC_OFFSET, XAE_TC_TX_MASK); + /* enable RX */ + out_be32(dev->iobase + XAE_RCW1_OFFSET, XAE_RCW1_RX_MASK); + + /* PHY setup */ + setup_phy(dev); + dev->state = 1; + debug("axi emac init complete\n"); + return 1; +} + +static int axiemac_send(struct eth_device *dev, volatile void *ptr, int len) +{ + struct axidma_priv *dma = dev->priv; + + if (len > ENET_MAX_MTU) + len = ENET_MAX_MTU; + + /* Flush packet to main memory to be trasfered by DMA */ + flush_cache(ptr, len); + + /* Setup Tx BD */ + memset((void *) &tx_bd, 0, sizeof(axidma_bd)); + /* At the end of the ring, link the last BD back to the top */ + tx_bd.next = (u32)&tx_bd; + tx_bd.phys = (u32)ptr; + /* save len */ + tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK | + XAXIDMA_BD_CTRL_TXEOF_MASK; + + /* Flush the last BD so DMA core could see the updates */ + flush_cache((u32)&tx_bd, sizeof(axidma_bd)); + + if (dma->dmatx->status & XAXIDMA_HALTED_MASK) { + dma->dmatx->current = (u32)&tx_bd; + /* Start the hardware */ + dma->dmatx->control |= XAXIDMA_CR_RUNSTOP_MASK; + } + + /* start transfer */ + dma->dmatx->tail = (u32)&tx_bd; + + /* Wait for transmission to complete */ + debug("axi emac, waiting for tx to be done\n"); + while (!dma->dmatx->status & + (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)) + ; + + debug("axi emac send complete\n"); + return 1; +} + +static int IsRxReady(struct eth_device *dev) +{ + u32 status; + struct axidma_priv *dma = dev->priv; + + /* Read pending interrupts */ + status = dma->dmarx->status; + + /* Acknowledge pending interrupts */ + dma->dmarx->status &= XAXIDMA_IRQ_ALL_MASK; + + /* + * If Reception done interrupt is asserted, call RX call back function + * to handle the processed BDs and then raise the according flag. + */ + if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) + return 1; + + return 0; +} + +static int axiemac_recv(struct eth_device *dev) +{ + u32 length; + struct axidma_priv *dma = dev->priv; + + /* wait for an incoming packet */ + if (!IsRxReady(dev)) + return 0; + + debug("axi emac, rx data ready\n"); + + /* Disable IRQ for a moment till packet is handled */ + dma->dmarx->control &= ~(XAXIDMA_IRQ_ALL_MASK & XAXIDMA_IRQ_ALL_MASK); + + length = rx_bd.app4 & 0x0000FFFF; +#ifdef DEBUG + print_buffer(&RxFrame, &RxFrame[0], 1, length, 16); +#endif + /* pass the received frame up for processing */ + if (length) + NetReceive(RxFrame, length); + +#ifdef DEBUG + /* It is useful to clear buffer to be sure that it is consistent */ + memset(RxFrame, 0, sizeof(RxFrame)); +#endif + /* Setup RxBD */ + /* Clear the whole buffer and setup it again - all flags are cleared */ + memset((void *) &rx_bd, 0, sizeof(axidma_bd)); + rx_bd.next = (u32)&rx_bd; + rx_bd.phys = (u32)&RxFrame; + rx_bd.cntrl = sizeof(RxFrame); + + /* write bd to HW */ + flush_cache((u32)&rx_bd, sizeof(axidma_bd)); + + /* it is necessary to flush RxFrame because if you don't do it + * then cache will contain previous packet */ + flush_cache((u32)&RxFrame, sizeof(RxFrame)); + + /* Rx BD is ready - start again */ + dma->dmarx->tail = (u32)&rx_bd; + + debug("axi emac rx complete, framelength = %d\n", length); + + return length; +} + +int xilinx_axiemac_initialize(bd_t *bis, int base_addr, int dma_addr) +{ + struct eth_device *dev; + struct axidma_priv *dma; + + dev = malloc(sizeof(*dev)); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + sprintf(dev->name, "Xilinx_AxiEmac"); + + dev->iobase = base_addr; + dma = dev->priv; + dma->dmatx = dma_addr; + dma->dmarx = (u32)dma->dmatx + 0x30; /* rx channel offset */ + dev->init = axiemac_init; + dev->halt = axiemac_halt; + dev->send = axiemac_send; + dev->recv = axiemac_recv; + + eth_register(dev); + + return 0; +} diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index ce9d426..efa0c73 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -78,6 +78,9 @@ #elif XILINX_LLTEMAC_BASEADDR # define CONFIG_XILINX_LL_TEMAC 1 # define CONFIG_SYS_ENET +#elif defined(XILINX_AXIEMAC_BASEADDR) +# define CONFIG_XILINX_AXIEMAC 1 +# define CONFIG_SYS_ENET #endif #undef ET_DEBUG -- 1.5.5.6

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[U-Boot] problem with crossmaking
by mohd hamid khan 09 Mar '11

09 Mar '11

i m making crossmake on my host machine linux (x486/4.4.4) when i m in process of u boot compilation i found error given as bellow. root@hamid:/home/u-boot-1.1.6# crossmake for dir in tools examples post post/cpu ; do make -C $dir _depend ; done make[1]: Entering directory `/home/u-boot-1.1.6/tools' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/tools' make[1]: Entering directory `/home/u-boot-1.1.6/examples' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/examples' make[1]: Entering directory `/home/u-boot-1.1.6/post' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/post' make[1]: Entering directory `/home/u-boot-1.1.6/post/cpu' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/post/cpu' make -C tools all make[1]: Entering directory `/home/u-boot-1.1.6/tools' make[1]: *** No rule to make target `/usr/lib/gcc/i386-redhat-linux/4.1.2/include/stddef.h', needed by `img2srec.o'. Stop. make[1]: Leaving directory `/home/u-boot-1.1.6/tools' make: *** [tools] Error 2 -- MOHD HAMID KHAN NPL INDIA B TECH EC

2 1

[U-Boot] problem with crossmaking
by Mohd Hamid 09 Mar '11

09 Mar '11

i m making crossmake on my host machine linux (x486/4.4.4) when i m in process of u boot compilation i found error given as bellow. root@hamid:/home/u-boot-1.1.6# crossmake for dir in tools examples post post/cpu ; do make -C $dir _depend ; done make[1]: Entering directory `/home/u-boot-1.1.6/tools' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/tools' make[1]: Entering directory `/home/u-boot-1.1.6/examples' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/examples' make[1]: Entering directory `/home/u-boot-1.1.6/post' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/post' make[1]: Entering directory `/home/u-boot-1.1.6/post/cpu' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/u-boot-1.1.6/post/cpu' make -C tools all make[1]: Entering directory `/home/u-boot-1.1.6/tools' make[1]: *** No rule to make target `/usr/lib/gcc/i386-redhat-linux/4.1.2/include/stddef.h', needed by `img2srec.o'. Stop. make[1]: Leaving directory `/home/u-boot-1.1.6/tools' make: *** [tools] Error 2 -- Open WebMail Project (http://openwebmail.org)

1 0

[U-Boot] make fails for versatilepb_config
by william estrada 09 Mar '11

09 Mar '11

Using u-boot-marvell.git, doing a make all make[1]: Entering directory `/src/IConnect/src/U-boot/u-boot-marvell.git/arch/arm/lib' arm-gp2x-linux-gcc -g -Os -fno-common -ffixed-r8 -msoft-float -D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x01000000 -I/src/IConnect/src/U-boot/u-boot-marvell.git/include -fno-builtin -ffreestanding -nostdinc -isystem /usr/lib/gcc/arm-gp2x-linux/4.1.2/include -pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux -mno-thumb-interwork -march=armv5te -Wall -Wstrict-prototypes -fno-stack-protector -o board.o board.c -c board.c: In function '__dram_init_banksize': board.c:233: error: 'CONFIG_SYS_SDRAM_BASE' undeclared (first use in this function) board.c:233: error: (Each undeclared identifier is reported only once board.c:233: error: for each function it appears in.) board.c: In function 'board_init_f': board.c:279: error: 'CONFIG_SYS_INIT_SP_ADDR' undeclared (first use in this function) board.c:312: error: 'CONFIG_SYS_SDRAM_BASE' undeclared (first use in this function) make[1]: *** [board.o] Error 1 make[1]: Leaving directory `/src/IConnect/src/U-boot/u-boot-marvell.git/arch/arm/lib' make: *** [arch/arm/lib/libarm.o] Error 2 Has this been fixed yet?? -- William Estrada Mt Umunhum, CA, USA HTTP://64.124.13.3 ( Mt-Umunhum-Wireless.net ) Skype: MrUmunhum

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