March 2011 - U-Boot

[U-Boot] some question about fat file system
by loody 15 Mar '11

15 Mar '11

Dear all: I try to port the fat file system on my platform but i cannot figure out what and where the getfatent come from. The comment said it try to get the entry at index entry in a FAT table. Is there any formula in the white paper of Microsoft FAT mentioned about this? -- Thank you in advance, miloody

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[U-Boot] [PATCH AT91] Add watchdog reset to the at91samx SOC family
by Michael Trimarchi 15 Mar '11

15 Mar '11

This patch add the watchdog reset function to the atmel atsam9x architectures. Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> Cc: Reinhard Meyer <u-boot(a)emk-elektronik.de> --- diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index 82b8d7e..2e4ff02 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -26,6 +26,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/at91_pit.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_wdt.h> #include <asm/arch/clk.h> #include <asm/arch/io.h> #include <div64.h> @@ -139,3 +140,18 @@ ulong get_tbclk(void) { return gd->timer_rate_hz; } + +#if defined(CONFIG_WATCHDOG) + +void watchdog_reset(void) +{ + at91_wdt_t *wdt = (at91_wdt_t *) AT91_WDT_BASE; + int re_enable = disable_interrupts(); + + writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wdt->cr); + + if (re_enable) + enable_interrupts(); +} + +#endif

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Re: [U-Boot] Uboot- Nor flash
by Hebbar, Gururaja 15 Mar '11

15 Mar '11

On Tue, Mar 15, 2011 at 12:14:40, Sanjeeva Kumara wrote: > > Board - PXA168 from Marvell > Nor Flash - 64MB > Nand Flash - 2Gb > Clock - 1Ghz > RAM 128MB Don't top-post. Maintain cc list There are lot of pxa ports in u-boot. Kindly follow the nearest one. pxa u-boot starts execution from <u-boot-src>/arch/arm/cpu/pxa/start.S --> _start function regards Gururaja > -----Original Message----- > From: Hebbar, Gururaja [mailto:gururaja.hebbar@ti.com] > Sent: Tuesday, March 15, 2011 11:55 AM > To: Sanjeeva Kumara > Cc: u-boot(a)lists.denx.de > Subject: RE: Uboot- Nor flash > > Hi, > > On Tue, Mar 15, 2011 at 11:07:46, Sanjeeva Kumara wrote: > > Hi pls help me....... > > How the boot image is read into memory.... from where exactly execution starts... > > > > 1. what is your board configuration (memory, Processor, ram, etc..) 2. Is your board inside u-boot repository ?. what is the board config name > > Regards > Gururaja > > > > > > > > -----Original Message----- > > From: Hebbar, Gururaja [mailto:gururaja.hebbar@ti.com] > > Sent: Friday, March 11, 2011 6:14 PM > > To: Sanjeeva Kumara; u-boot(a)lists.denx.de > > Subject: RE: Uboot- Nor flash > > > > Hi, > > > > On Fri, Mar 11, 2011 at 14:02:20, Sanjeeva Kumara wrote: > > > Hi.... > > > My self Sanjeev. I'm working on marvell's processor ( PXA ). I'm using NOR flash to port Uboot. I want to do partition in NOR flash so that in one partition I can keep my master copy and provide Uboot upgrade option. Please suggest me how can I achieve this. > > > > > > > The quickest would be to use CONFIG_SYS_FLASH_AUTOPROTECT_LIST. Search for this config and this will help you setup autoprotect options for various partitions. > > > > > > Regards, > > Gururaja > > > > > > Larsen & Toubro Limited > > > > www.larsentoubro.com > > > > This Email may contain confidential or privileged information for the intended recipient (s) If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. > > > > > Regards, > Gururaja > > > Larsen & Toubro Limited > > www.larsentoubro.com > > This Email may contain confidential or privileged information for the intended recipient (s) If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. > Regards, Gururaja

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[U-Boot] [PATCH v5 0/3] Board support series for the eXMeritus HWW-1U-1A
by Kyle Moffett 15 Mar '11

15 Mar '11

This is the latest respin of the eXMeritus HWW-1U-1A board support patches. It's down to just a 3-patch series, with all of the other patches submitted separately. This series techncially depends on the reset rework, the "reset" command will not work properly on the HWW-1U-1A hardware without those patches. It will not cause a build failure however, as this board port simply defines an otherwise-unused __board_restart() function. I believe these 3 patches at least are ready to be merged, as all concerns presented so far have been resolved. Cheers, Kyle Moffett

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[U-Boot] [PATCH] powerpc/85xx: Fix synchronization of timebase on MP boot
by Kumar Gala 15 Mar '11

15 Mar '11

There is a small ordering issue in the master core in that we need to make sure the disabling of the timebase in the SoC is visible before we set the value to 0. We can simply just read back the value to synchronizatize the write, before we set TB to 0. Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/mp.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 6c0da83..758e6d7 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -276,8 +276,13 @@ static void plat_mp_up(unsigned long bootpg) /* enable time base at the platform */ out_be32(&rcpm->ctbenrl, 0); + + /* readback to sync write */ + in_be32(&rcpm->ctbenrl); + mtspr(SPRN_TBWU, 0); mtspr(SPRN_TBWL, 0); + out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1); #ifdef CONFIG_MPC8xxx_DISABLE_BPTR @@ -347,6 +352,10 @@ static void plat_mp_up(unsigned long bootpg) else devdisr |= MPC85xx_DEVDISR_TB0; out_be32(&gur->devdisr, devdisr); + + /* readback to sync write */ + in_be32(&gur->devdisr); + mtspr(SPRN_TBWU, 0); mtspr(SPRN_TBWL, 0); -- 1.7.2.3

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Re: [U-Boot] Uboot- Nor flash
by Hebbar, Gururaja 15 Mar '11

15 Mar '11

Hi, On Tue, Mar 15, 2011 at 11:07:46, Sanjeeva Kumara wrote: > Hi pls help me....... > How the boot image is read into memory.... from where exactly execution starts... > 1. what is your board configuration (memory, Processor, ram, etc..) 2. Is your board inside u-boot repository ?. what is the board config name Regards Gururaja > > -----Original Message----- > From: Hebbar, Gururaja [mailto:gururaja.hebbar@ti.com] > Sent: Friday, March 11, 2011 6:14 PM > To: Sanjeeva Kumara; u-boot(a)lists.denx.de > Subject: RE: Uboot- Nor flash > > Hi, > > On Fri, Mar 11, 2011 at 14:02:20, Sanjeeva Kumara wrote: > > Hi.... > > My self Sanjeev. I'm working on marvell's processor ( PXA ). I'm using NOR flash to port Uboot. I want to do partition in NOR flash so that in one partition I can keep my master copy and provide Uboot upgrade option. Please suggest me how can I achieve this. > > > > The quickest would be to use CONFIG_SYS_FLASH_AUTOPROTECT_LIST. Search for this config and this will help you setup autoprotect options for various partitions. > > > Regards, > Gururaja > > > Larsen & Toubro Limited > > www.larsentoubro.com > > This Email may contain confidential or privileged information for the intended recipient (s) If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. > Regards, Gururaja

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[U-Boot] [PATCH] sh: Add handling of CONFIG_SYS_NO_FLASH for board.c
by Nobuhiro Iwamatsu 15 Mar '11

15 Mar '11

Some board of SH does not have flash memoy. This revises it to initialize Flash when CONFIG_SYS_NO_FLASH is not defined. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/sh/lib/board.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 968566c..ed91643 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -43,6 +43,7 @@ const char version_string[] = U_BOOT_VERSION" ("U_BOOT_DATE" - "U_BOOT_TIME")"; unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; +#ifndef CONFIG_SYS_NO_FLASH static int sh_flash_init(void) { gd->bd->bi_flashsize = flash_init(); @@ -54,6 +55,7 @@ static int sh_flash_init(void) return 0; } +#endif /* CONFIG_SYS_NO_FLASH */ #if defined(CONFIG_CMD_NAND) # include <nand.h> @@ -125,7 +127,9 @@ init_fnc_t *init_sequence[] = dram_init, /* SDRAM init */ timer_init, /* SuperH Timer (TCNT0 only) init */ sh_mem_env_init, - sh_flash_init, /* Flash memory(NOR) init*/ +#ifndef CONFIG_SYS_NO_FLASH + sh_flash_init, /* Flash memory init*/ +#endif INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */ INIT_FUNC_PCI_INIT /* PCI init */ stdio_init, @@ -157,7 +161,9 @@ void sh_generic_init(void) bd = gd->bd; bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; +#ifndef CONFIG_SYS_NO_FLASH bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#endif #if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; -- 1.7.4.1

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[U-Boot] [RFC PATCH 0/6] Mips: Refactoring of CPU and SoC code
by daniel.schwierzeck＠googlemail.com 15 Mar '11

15 Mar '11

All current Mips CPUs and SoCs are based on Mips32 arch. The complete code resides in the global arch/mips/cpu directory. All SoC specific code resides in this directory too. This is not suitable if other Mips architectures like Mips64 or Octeon or new SoCs should be supported in the future. This patch series refactors the Mips CPU directory and put all current code into an own mips32 subdirectory. Furthermore the SoC specific code of IncaIP, Purple and Au1x00 is moved to separate SoC subdirectories. Daniel Schwierzeck (6): Mips: Move content of arch/mips/cpu to arch/mips/cpu/mips32 Mips: Purple: Adapt u-boot.lds to changed CPU directory layout Mips: IncaIP: Move all IncaIP specific code to separate subdirectory Mips: Purple: Move all Purple specific code to separate subdirectory Mips: Au1x00: Move all Au1x00 specific code to separate subdirectory Mips: Update setting of endianess and CPU optimization flags arch/mips/cpu/config.mk | 39 --------------- arch/mips/cpu/{ => mips32}/Makefile | 5 -- arch/mips/cpu/mips32/au1x00/Makefile | 45 +++++++++++++++++ arch/mips/cpu/{ => mips32/au1x00}/au1x00_eth.c | 0 arch/mips/cpu/{ => mips32/au1x00}/au1x00_serial.c | 0 .../mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.c | 0 .../mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.h | 0 arch/mips/cpu/mips32/au1x00/config.mk | 24 +++++++++ arch/mips/cpu/{ => mips32}/cache.S | 0 arch/mips/cpu/mips32/config.mk | 32 ++++++++++++ arch/mips/cpu/{ => mips32}/cpu.c | 0 arch/mips/cpu/mips32/incaip/Makefile | 46 +++++++++++++++++ arch/mips/cpu/{ => mips32/incaip}/asc_serial.c | 0 arch/mips/cpu/{ => mips32/incaip}/asc_serial.h | 0 arch/mips/cpu/mips32/incaip/config.mk | 24 +++++++++ arch/mips/cpu/{ => mips32/incaip}/incaip_clock.c | 0 arch/mips/cpu/{ => mips32/incaip}/incaip_wdt.S | 0 arch/mips/cpu/{ => mips32}/interrupts.c | 0 arch/mips/cpu/mips32/purple/Makefile | 45 +++++++++++++++++ arch/mips/cpu/{ => mips32/purple}/asc_serial.c | 0 arch/mips/cpu/{ => mips32/purple}/asc_serial.h | 0 arch/mips/cpu/mips32/purple/config.mk | 24 +++++++++ arch/mips/cpu/{ => mips32}/start.S | 0 board/purple/u-boot.lds | 2 +- boards.cfg | 52 ++++++++++---------- 25 files changed, 267 insertions(+), 71 deletions(-) delete mode 100644 arch/mips/cpu/config.mk rename arch/mips/cpu/{ => mips32}/Makefile (87%) create mode 100644 arch/mips/cpu/mips32/au1x00/Makefile rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_eth.c (100%) rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_serial.c (100%) rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.c (100%) rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.h (100%) create mode 100644 arch/mips/cpu/mips32/au1x00/config.mk rename arch/mips/cpu/{ => mips32}/cache.S (100%) create mode 100644 arch/mips/cpu/mips32/config.mk rename arch/mips/cpu/{ => mips32}/cpu.c (100%) create mode 100644 arch/mips/cpu/mips32/incaip/Makefile copy arch/mips/cpu/{ => mips32/incaip}/asc_serial.c (100%) copy arch/mips/cpu/{ => mips32/incaip}/asc_serial.h (100%) create mode 100644 arch/mips/cpu/mips32/incaip/config.mk rename arch/mips/cpu/{ => mips32/incaip}/incaip_clock.c (100%) rename arch/mips/cpu/{ => mips32/incaip}/incaip_wdt.S (100%) rename arch/mips/cpu/{ => mips32}/interrupts.c (100%) create mode 100644 arch/mips/cpu/mips32/purple/Makefile rename arch/mips/cpu/{ => mips32/purple}/asc_serial.c (100%) rename arch/mips/cpu/{ => mips32/purple}/asc_serial.h (100%) create mode 100644 arch/mips/cpu/mips32/purple/config.mk rename arch/mips/cpu/{ => mips32}/start.S (100%) -- 1.7.4.1

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[U-Boot] [RFC] I2C: change CONFIG_SYS_SPD_BUS_NUM to CONFIG_I2C_DEFAULT_BUS_NUM
by Matthew McClintock 15 Mar '11

15 Mar '11

The bus that the i2c api can access before relocating from flash is defined via CONFIG_SYS_SPD_BUS_NUM, however we want to use the i2c bus before relocating from flash for non-SPD related reasons. Therefore, we rename this define to something more appropriate --- We are trying to access the I2C bus before relocation from flash to read switch settings. Using the current CONFIG_SYS_SPD_BUS_NUM define to do this is fine for our needs however I would like to ask if we wanted to change this to a new more generic define CONFIG_I2C_DEFAULT_BUS_NUM README | 4 ++-- arch/powerpc/cpu/mpc5xxx/i2c.c | 2 +- arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 2 +- arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c | 2 +- board/freescale/common/sys_eeprom.c | 8 ++++---- drivers/i2c/fsl_i2c.c | 6 +++--- drivers/i2c/ppc4xx_i2c.c | 8 ++++---- include/configs/DU440.h | 2 +- include/configs/MPC8349ITX.h | 2 +- include/configs/MPC8536DS.h | 2 +- include/configs/MPC8572DS.h | 2 +- include/configs/P1022DS.h | 2 +- include/configs/P2020DS.h | 2 +- include/configs/corenet_ds.h | 2 +- include/configs/hcu4.h | 2 +- include/configs/hcu5.h | 2 +- include/configs/icon.h | 2 +- include/configs/katmai.h | 2 +- include/configs/mcu25.h | 2 +- include/configs/sbc8349.h | 2 +- include/configs/vme8349.h | 2 +- include/i2c.h | 4 ++-- 22 files changed, 32 insertions(+), 32 deletions(-) diff --git a/README b/README index 21cd71b..4284809 100644 --- a/README +++ b/README @@ -1576,7 +1576,7 @@ The following options need to be configured: will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - CONFIG_SYS_SPD_BUS_NUM + CONFIG_I2C_DEFAULT_BUS_NUM If defined, then this indicates the I2C bus number for DDR SPD. If not defined, then U-Boot assumes that SPD is on I2C bus 0. @@ -2834,7 +2834,7 @@ Low Level (hardware related) configuration options: SPD_EEPROM_ADDRESS I2C address of the SPD EEPROM -- CONFIG_SYS_SPD_BUS_NUM +- CONFIG_I2C_DEFAULT_BUS_NUM If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve to something your driver can deal with. diff --git a/arch/powerpc/cpu/mpc5xxx/i2c.c b/arch/powerpc/cpu/mpc5xxx/i2c.c index 9fb330f..65fb1f2 100644 --- a/arch/powerpc/cpu/mpc5xxx/i2c.c +++ b/arch/powerpc/cpu/mpc5xxx/i2c.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif #else static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = - CONFIG_SYS_SPD_BUS_NUM; + CONFIG_I2C_DEFAULT_BUS_NUM; static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 95df1d9..00984cd 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -475,7 +475,7 @@ phys_size_t initdram(int board_type) */ /* switch to correct I2C bus */ - I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); + I2C_SET_BUS(CONFIG_I2C_DEFAULT_BUS_NUM); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /*------------------------------------------------------------------ diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c index c35b113..1431056 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c @@ -1048,7 +1048,7 @@ phys_size_t initdram(int board_type) * before continuing. */ /* switch to correct I2C bus */ - I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); + I2C_SET_BUS(CONFIG_I2C_DEFAULT_BUS_NUM); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /*------------------------------------------------------------------ diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 3ecfb06..2c678d3 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -495,11 +495,11 @@ int mac_read_from_eeprom(void) * This function is called before relocation, so we need to read a private * copy of the EEPROM into a local variable on the stack. * - * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM. The global - * variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM, + * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_I2C_DEFAULT_BUS_NUM. The global + * variable i2c_bus_num must be compile-time initialized to CONFIG_I2C_DEFAULT_BUS_NUM, * so that the SPD code will work. This means that all pre-relocation I2C - * operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus. So if - * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when + * operations can only occur on the CONFIG_I2C_DEFAULT_BUS_NUM bus. So if + * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_I2C_DEFAULT_BUS_NUM, then we can't read the EEPROM when * this function is called. Oh well. */ unsigned int get_cpu_board_revision(void) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index cb13dee..e509993 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -52,10 +52,10 @@ DECLARE_GLOBAL_DATA_PTR; * runs from ROM, and we can't switch buses because we can't modify * the global variables. */ -#ifndef CONFIG_SYS_SPD_BUS_NUM -#define CONFIG_SYS_SPD_BUS_NUM 0 +#ifndef CONFIG_I2C_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUM 0 #endif -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM; +static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_I2C_DEFAULT_BUS_NUM; #if defined(CONFIG_I2C_MUX) static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; #endif diff --git a/drivers/i2c/ppc4xx_i2c.c b/drivers/i2c/ppc4xx_i2c.c index c1cbe55..7e43e7a 100644 --- a/drivers/i2c/ppc4xx_i2c.c +++ b/drivers/i2c/ppc4xx_i2c.c @@ -43,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR; * runs from ROM, and we can't switch buses because we can't modify * the global variables. */ -#ifndef CONFIG_SYS_SPD_BUS_NUM -#define CONFIG_SYS_SPD_BUS_NUM 0 +#ifndef CONFIG_I2C_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUM 0 #endif static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = - CONFIG_SYS_SPD_BUS_NUM; + CONFIG_I2C_DEFAULT_BUS_NUM; #endif /* CONFIG_I2C_MULTI_BUS */ static void _i2c_bus_reset(void) @@ -166,7 +166,7 @@ void i2c_init(int speed, int slaveaddr) } /* set to SPD bus as default bus upon powerup */ - I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); + I2C_SET_BUS(CONFIG_I2C_DEFAULT_BUS_NUM); } /* diff --git a/include/configs/DU440.h b/include/configs/DU440.h index ceab604..1bffe8e 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -178,7 +178,7 @@ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_I2C_DEFAULT_BUS_NUM 0 #define IIC1_MCP3021_ADDR 0x4d #define IIC1_USB2507_ADDR 0x2c #ifdef CONFIG_I2C_MULTI_BUS diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index de233ff..3193c6d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -103,7 +103,7 @@ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ +#define CONFIG_I2C_DEFAULT_BUS_NUM 1 /* The I2C bus for SPD */ #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 13300de..a5f2e79 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -163,7 +163,7 @@ /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ -#define CONFIG_SYS_SPD_BUS_NUM 1 +#define CONFIG_I2C_DEFAULT_BUS_NUM 1 /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index bf2fdd6..b7944da 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -148,7 +148,7 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ -#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ +#define CONFIG_I2C_DEFAULT_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index cb24041..fab193d 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -86,7 +86,7 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) /* I2C addresses of SPD EEPROMs */ -#define CONFIG_SYS_SPD_BUS_NUM 1 +#define CONFIG_I2C_DEFAULT_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ /* diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index b32a997..b0eb5ae 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -127,7 +127,7 @@ /* I2C addresses of SPD EEPROMs */ #define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ +#define CONFIG_I2C_DEFAULT_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index bff212e..1c93be0 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -137,7 +137,7 @@ #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 -#define CONFIG_SYS_SPD_BUS_NUM 1 +#define CONFIG_I2C_DEFAULT_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index c56efde..67b98c7 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -141,7 +141,7 @@ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the * the first internal I2C controller of the PPC440EPx *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_I2C_DEFAULT_BUS_NUM 0 #define CONFIG_IPADDR 172.25.1.14 diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 0c8fdf5..e7ecbeb 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -141,7 +141,7 @@ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the * the second internal I2C controller of the PPC440EPx *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SPD_BUS_NUM 1 +#define CONFIG_I2C_DEFAULT_BUS_NUM 1 /* Setup some board specific values for the default environment variables */ #define CONFIG_IPADDR 172.25.1.15 diff --git a/include/configs/icon.h b/include/configs/icon.h index 2fac0ef..ab34fe3 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -123,7 +123,7 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ +#define CONFIG_I2C_DEFAULT_BUS_NUM 0 /* The I2C bus for SPD */ #define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 3ed8dc7..dfdc739 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -122,7 +122,7 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ +#define CONFIG_I2C_DEFAULT_BUS_NUM 0 /* The I2C bus for SPD */ #define IIC0_BOOTPROM_ADDR 0x50 #define IIC0_ALT_BOOTPROM_ADDR 0x54 diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h index a162291..73df878 100644 --- a/include/configs/mcu25.h +++ b/include/configs/mcu25.h @@ -141,7 +141,7 @@ * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the * the first internal I2C controller of the PPC440EPx *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_I2C_DEFAULT_BUS_NUM 0 /* Setup some board specific values for the default environment variables */ #define CONFIG_IPADDR 172.25.1.25 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index b418cf2..588c500 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -290,7 +290,7 @@ #define CONFIG_SYS_I2C1_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_I2C_DEFAULT_BUS_NUM... */ /* TSEC */ #define CONFIG_SYS_TSEC1_OFFSET 0x24000 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index d153762..b400988 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -221,7 +221,7 @@ #define CONFIG_SYS_I2C1_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_I2C_DEFAULT_BUS_NUM... */ #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ diff --git a/include/i2c.h b/include/i2c.h index cd23c8a..452cffa 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -65,8 +65,8 @@ #if !defined(CONFIG_SYS_DTT_BUS_NUM) #define CONFIG_SYS_DTT_BUS_NUM 0 #endif -#if !defined(CONFIG_SYS_SPD_BUS_NUM) -#define CONFIG_SYS_SPD_BUS_NUM 0 +#if !defined(CONFIG_I2C_DEFAULT_BUS_NUM) +#define CONFIG_I2C_DEFAULT_BUS_NUM 0 #endif #ifndef I2C_SOFT_DECLARATIONS -- 1.6.6.1

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[U-Boot] Can you help me?
by Jamila Abunura 14 Mar '11

14 Mar '11

Dear respected one, I am Jamila by name, and please forgive me if I am disturbing you through this media. I really need your help if you can. I have a secret to tell you about my life, but I am afraid to just open up like that through this media, because it is a long story. Please kindly give me your confidential EMAIL ID / MOBILE No ; so I can express my self in details if it may interest you. Hoping to hear from you soon, Thanks, Jamila.

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