March 2011 - U-Boot

[U-Boot] [PATCH 1/5] powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb
by Kumar Gala 25 Mar '11

25 Mar '11

From: Priyanka Jain <Priyanka.Jain(a)freescale.com> Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal(a)freescale.com> Signed-off-by: Dipen Dudhat <Dipen.Dudhat(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/p1_p2_rdb/ddr.c | 15 +++++++++++---- board/freescale/p1_p2_rdb/tlb.c | 13 ++++--------- include/configs/P1_P2_RDB.h | 8 ++++---- 3 files changed, 19 insertions(+), 17 deletions(-) diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 44faec3..853044e 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -202,6 +202,17 @@ phys_size_t fixed_sdram (void) struct cpu_type *cpu; ulong ddr_freq, ddr_freq_mhz; + cpu = gd->cpu; + /* P1020 and it's derivatives support max 32bit DDR width */ + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); + } else { + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + } +#if defined(CONFIG_SYS_RAMBOOT) + return ddr_size; +#endif ddr_freq = get_ddr_freq(0); ddr_freq_mhz = ddr_freq / 1000000; @@ -220,16 +231,12 @@ phys_size_t fixed_sdram (void) panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, ddr_freq)); - cpu = gd->cpu; /* P1020 and it's derivatives support max 32bit DDR width */ if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.cs[0].bnds = 0x0000001F; - ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } - else - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index b85c268..e54defb 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -80,15 +80,10 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256K, 1), +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_1G, 1) #endif }; diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 651dc76..23b8afa 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -57,14 +57,14 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif #ifndef CONFIG_SYS_TEXT_BASE -- 1.7.2.3

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[U-Boot] [PATCH] powerpc/8xxx: Reduce NAND-SPL build size
by Kumar Gala 25 Mar '11

25 Mar '11

We don't use disable_law in the SPL code so only build it if !CONFIG_NAND_SPL. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- drivers/misc/fsl_law.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 3233ff2..9b25ddc 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -79,6 +79,7 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) in_be32(LAWAR_ADDR(idx)); } +#ifndef CONFIG_NAND_SPL void disable_law(u8 idx) { gd->used_laws &= ~(1 << idx); @@ -92,7 +93,6 @@ void disable_law(u8 idx) return; } -#ifndef CONFIG_NAND_SPL static int get_law_entry(u8 i, struct law_entry *e) { u32 lawar; -- 1.7.2.3

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[U-Boot] [PATCH] fsl: obsolete NXID v0 EEPROMs, automatically upgrade them to NXID v1
by Kumar Gala 25 Mar '11

25 Mar '11

From: Timur Tabi <timur(a)freescale.com> The NXID EEPROM format comes in two versions, v0 and v1. The only difference is in the number of MAC addresses that can be stored. NXID v0 supports eight addresses, and NXID v1 supports 23. Rather than allow a board to choose which version to support, NXID v0 is now considered deprecated. The EEPROM code is updated to support only NXID v1, but it can still read EEPROMs formatted with v0. In these cases, the EEPROM data is loaded and the CRC is verified, but the data is stored into a v1 data structure. If the EEPROM data is written back, it is written in v1 format. This allows existing v0-formatted EEPROMs to continue providing MAC addresses, but any changes to the data will force an upgrade to the v1 format, while retaining all data. Signed-off-by: Timur Tabi <timur(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/common/sys_eeprom.c | 48 ++++++++++++++++++++++++++++------ 1 files changed, 39 insertions(+), 9 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 3ecfb06..4e18d57 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -34,12 +34,6 @@ #endif #ifdef CONFIG_SYS_I2C_EEPROM_NXID -#define MAX_NUM_PORTS 8 -#define NXID_VERSION 0 -#endif - -#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1 -#define CONFIG_SYS_I2C_EEPROM_NXID #define MAX_NUM_PORTS 23 #define NXID_VERSION 1 #endif @@ -428,11 +422,16 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * This ensures that any user-saved variables are never overwritten. * * This function must be called after relocation. + * + * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0 + * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is + * located at a different offset. */ int mac_read_from_eeprom(void) { unsigned int i; - u32 crc; + u32 crc, crc_offset = offsetof(struct eeprom, crc); + u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ puts("EEPROM: "); @@ -447,12 +446,32 @@ int mac_read_from_eeprom(void) return -1; } - crc = crc32(0, (void *)&e, sizeof(e) - 4); - if (crc != be32_to_cpu(e.crc)) { +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + /* + * If we've read an NXID v0 EEPROM, then we need to set the CRC offset + * to where it is in v0. + */ + if (e.version == 0) + crc_offset = 0x72; +#endif + + crc = crc32(0, (void *)&e, crc_offset); + crcp = (void *)&e + crc_offset; + if (crc != be32_to_cpu(*crcp)) { printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc)); return -1; } +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + /* + * MAC address #9 in v1 occupies the same position as the CRC in v0. + * Erase it so that it's not mistaken for a MAC address. We'll + * update the CRC later. + */ + if (e.version == 0) + memset(e.mac[8], 0xff, 6); +#endif + for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) { if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { @@ -482,6 +501,17 @@ int mac_read_from_eeprom(void) printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + /* + * Now we need to upconvert the data into v1 format. We do this last so + * that at boot time, U-Boot will still say "NXID v0". + */ + if (e.version == 0) { + e.version = NXID_VERSION; + update_crc(); + } +#endif + return 0; } -- 1.7.2.3

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[U-Boot] [PATCH] powerpc/85xx: Enable various errata on P1022/P1013 SoCs
by Kumar Gala 25 Mar '11

25 Mar '11

From: Jiang Yutang <b14898(a)freescale.com> Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on P1022/P1013 SoCs. Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2. Signed-off-by: Jiang Yutang <b14898(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ include/configs/P1022DS.h | 1 + 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 18327fd..5bdb11b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -109,6 +109,9 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_FSL_SATA_ERRATUM_A001 #elif defined(CONFIG_P1014) #define CONFIG_MAX_CPUS 1 @@ -143,6 +146,9 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_FSL_SATA_ERRATUM_A001 #elif defined(CONFIG_P1023) #define CONFIG_MAX_CPUS 2 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index f672b3d..5f47d1a 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -279,6 +279,7 @@ /* SATA */ #define CONFIG_LIBATA #define CONFIG_FSL_SATA +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 -- 1.7.2.3

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[U-Boot] [PATCH] powerpc/85xx: Fix PCI memory map setup on P1_P2_RDB
by Kumar Gala 25 Mar '11

25 Mar '11

From: Prabhakar Kushwaha <prabhakar(a)freescale.com> Update the PCIe address map to match standard FSL memory map. Additionally, fix the TLBs so the cover the PCIe address space properly so cards plugged in like an e1000 work correctly. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/p1_p2_rdb/tlb.c | 4 ++-- include/configs/P1_P2_RDB.h | 24 ++++++++++++------------ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index b85c268..a46b1b5 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -60,12 +60,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_PCI) /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 982cdd5..95b85e3 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -177,8 +177,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Memory map * * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen - * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable * * Localbus cacheable (TBD) * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable @@ -368,27 +368,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Memory space is mapped 1-1, but I/O space must start from 0. */ -/* controller 2, Slot 2, tgtid 2, Base address 9000 */ #if defined(CONFIG_PCI) +/* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_NAME "Slot 2" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ -- 1.7.3.4

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Re: [U-Boot] [PATCH v6 01/13] nds32: add header files support for nds32
by Macpaul Lin 25 Mar '11

25 Mar '11

Hi Wolfgang, 2011/3/25 Wolfgang Denk <wd(a)denx.de>: > Dear Macpaul Lin, > > please keep the list on Cc: > >> I did run checkpatch, >> However, "some of these files" comes from Linux kernel header. > > Well, the checkpatch comes from Linux, so your files violate the Linux > kernel coding style in the first place. The should have never been > accepted there. > >> And those files in Linux Kernel comes from arm's assembly headers. > > Well, that's not exactly a recommendation, if you ask me. > >> If I cleaned up these headers, it might cause some diffculty when those header >> has been update in the kernel. After I disscussed with my colledgue >> (Linux Kernel Team). >> They wish me to send the headers with Linux kernel compatibilty. > > I suggect you clean up the header files in the Linux kernel as well. > As it is a clear code cleanup (making the code match the Linux > CodingStyle requirements) this should go in easily. > >> However it might require your confirmation so that I can let my boss >> aware the headers will be different from those in Linux Kernel. > > I don't ask that they are different. On contrary, they should be > identical if possible. Here that means that the cleaned up versions > should be used both in Linux and in U-Boot. > > Note: this also and especially applies to the "volatile" and "using > I/O accessors instead of pointer acesses" issues. [If not yet, you > would probably soon run into issues when switching to GCC 4.5.x or > even GCC 4.6.] > > Best regards, > > Wolfgang Denk Thanks for your suggestions. I've forward it to the OS team of my company and inform them the possible problem in the future. Thanks a lot. -- Best regards, Macpaul Lin

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[U-Boot] (no subject)
by Robert Pasquantonio 25 Mar '11

25 Mar '11

I have a foundation/Estate uncompleted {valued at USD 2,142,728.00} and need you to help me finish it because of my health, Everything is available. Please contact me for more details thank you.(elizabeth.stevens(a)admin.in.th<mailto:elizabeth.stevens@admin.in.th>). E-MAIL CONFIDENTIALITY NOTICE: The information transmitted in this electronic message may be legally privileged and confidential under applicable law, including the Family Educational Rights and Privacy Act (FERPA) and the Health Insurance Portability and Accountability Act (HIPAA), and is intended only for the person or entity to which it is addressed. If the recipient of this message is not the above named intended recipient, you are hereby notified that any review, retransmission, dissemination, copy, disclosure or other use of, or taking any action in reliance upon, this information by persons or entities other than the intended recipient is prohibited. If you received this electronic transmission in error, please notify the Bethel Park School District at (412) 854-8402, and purge the communication immediately from any computers, storage devices, paper or other media without making any copy or distribution thereof. Thank you for your cooperation.

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[U-Boot] OpenRD-{Client,Ultimate}
by Clint Adams 25 Mar '11

25 Mar '11

What is the status of the OpenRD-Ultimate support discussed last summer? Is there no way to detect the board type and use a single U-Boot image for all three variants?

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[U-Boot] [PATCH] mx53loco: set mmc env to MMC slot1
by Jason Liu 25 Mar '11

25 Mar '11

mx53loco board has two MMC slots, one is for MicroSD, the other one is for normal SD, but the final board design is to only boot from MicroSD. So, make the mmc env default to slot1(MicroSD slot) Signed-off-by: Jason Liu <jason.hui(a)linaro.org> --- include/configs/mx53loco.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 8c30012..585e8c8 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -191,6 +191,6 @@ #define CONFIG_ENV_OFFSET (6 * 64 * 1024) #define CONFIG_ENV_SIZE (8 * 1024) #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #endif /* __CONFIG_H */ -- 1.7.1

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[U-Boot] Changing USB speed from slow to fast
by Nikhilesh Dwivedi 25 Mar '11

25 Mar '11

Hi, I am working on ARM at91sam9g20ek. I am copying my Kernel image and rootfilesystem (jffs2) from USB to nand memory in UBOOT. Currently copying files from USB to RAM takes more time and I figured out from the code that USB Speed is low (1.5Mb/s). How can I change it to Fast speed in Uboot? Thanks for help. Regards, Nikhilesh Dwivedi

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