March 2011 - U-Boot

[U-Boot] Business Offer !!!?
by Dr.Anderson Mark 25 Mar '11

25 Mar '11

Compliments, I got your contact from our British Chambers of Commerce and Industry and I decided to contact you directly for an investment with you in my company if you can understand English and India Language (Hindi).Our company is into production of Pharmaceutical products and Animal Vaccines.There are some materials that my company needs from India for the production of our Animal Vaccines and Anti-viral drugs. We have been purchasing the materials from Pakistan but it is very scarce now and we got information that somebody has it in India but we are having problem with the owner of the products due to language barrier. Please take out a moment of your very busy schedule to respond back by email: Dr-Anderson-Mark(a)live.co.uk For more details. Regards, Dr.Anderson Mark ---------------------------------------------------------------- This message was sent using IMP, the Internet Messaging Program.

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[U-Boot] [PATCH] fat32 root directory handling
by Erik Hansen 25 Mar '11

25 Mar '11

Fat directory handling didn't check reaching the end of the root directory. It relied on a stop condition based on a directory entry with a name starting with a '\0' character. This check in itself is wrong ('\0' indicates free entry, not end_of_directory) but outside the scope of this fix. For FAT32, the end of the rootdir is reached when the end of the cluster chain is reached. The code didn't check this condition and started to read an incorrect cluster. This caused a subsequent read request of a sector outside the range of the usb stick in use. On its turn, the usb stick protested with a stall handshake. Both FAT32 and non-FAT32 (FAT16/FAT12) end or rootdir checks have been put in. Signed-off-by: Erik Hansen <erik(a)makarta.com> --- fs/fat/fat.c | 38 ++++++++++++++++++++++++-------------- 1 files changed, 24 insertions(+), 14 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index a75e4f2..2a3414f 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -31,6 +31,7 @@ #include <asm/byteorder.h> #include <part.h> + /* * Convert a string to lowercase. */ @@ -209,7 +210,7 @@ static __u32 get_fatent (fsdata *mydata, __u32 entry) /* Read a new block of FAT entries into the cache. */ if (bufnum != mydata->fatbufnum) { - int getsize = FATBUFSIZE / FS_BLOCK_SIZE; + __u32 getsize = FATBUFSIZE / FS_BLOCK_SIZE; __u8 *bufptr = mydata->fatbuf; __u32 fatlength = mydata->fatlength; __u32 startblock = bufnum * FATBUFBLOCKS; @@ -279,7 +280,7 @@ static int get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) { - int idx = 0; + __u32 idx = 0; __u32 startsect; if (clustnum > 0) { @@ -767,12 +768,13 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize, dir_entry *dentptr; __u16 prevcksum = 0xffff; char *subname = ""; - int cursect; + __u32 cursect; int idx, isdir = 0; int files = 0, dirs = 0; long ret = 0; int firsttime; - int root_cluster; + __u32 root_cluster; + int rootdir_size = 0; int j; if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) { @@ -798,8 +800,6 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize, mydata->data_begin = mydata->rootdir_sect - (mydata->clust_size * 2); } else { - int rootdir_size; - rootdir_size = ((bs.dir_entries[1] * (int)256 + bs.dir_entries[0]) * sizeof(dir_entry)) / @@ -1006,20 +1006,18 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize, * root directory clusters when a cluster has been * completely processed. */ - if ((mydata->fatsize == 32) && (++j == mydata->clust_size)) { - int nxtsect; - int nxt_clust; + ++j; + int fat32_end = 0; + if ((mydata->fatsize == 32) && (j == mydata->clust_size)) { + int nxtsect = 0; + int nxt_clust = 0; nxt_clust = get_fatent(mydata, root_cluster); + fat32_end = CHECK_CLUST(nxt_clust, 32); nxtsect = mydata->data_begin + (nxt_clust * mydata->clust_size); - debug("END LOOP: sect=%d, root_clust=%d, " - "n_sect=%d, n_clust=%d\n", - cursect, root_cluster, - nxtsect, nxt_clust); - root_cluster = nxt_clust; cursect = nxtsect; @@ -1027,6 +1025,18 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize, } else { cursect++; } + + /* If end of rootdir reached */ + if ((mydata->fatsize == 32 && fat32_end) || + (mydata->fatsize != 32 && j == rootdir_size)) { + if (dols == LS_ROOT) { + printf("\n%d file(s), %d dir(s)\n\n", + files, dirs); + return 0; + } else { + return -1; + } + } } rootdir_done: -- 1.7.0.4

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[U-Boot] [PATCH] Remove unnecessary reset in usb_stor_get_info
by Erik Hansen 25 Mar '11

25 Mar '11

The reset request in usb_stor_get_info is causing issues with some usb sticks. Some of these sticks vendor_id/product_id have been hardcoded to not reset but better is to remove the reset altogether. It is not needed. Signed-off-by: Erik Hansen <erik(a)makarta.com> --- common/usb_storage.c | 25 ------------------------- 1 files changed, 0 insertions(+), 25 deletions(-) diff --git a/common/usb_storage.c b/common/usb_storage.c index 1e6cd6a..6963e6d 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -1346,31 +1346,6 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, unsigned long *capacity, *blksz; ccb *pccb = &usb_ccb; - /* for some reasons a couple of devices would not survive this reset */ - if ( - /* Sony USM256E */ - (dev->descriptor.idVendor == 0x054c && - dev->descriptor.idProduct == 0x019e) - || - /* USB007 Mini-USB2 Flash Drive */ - (dev->descriptor.idVendor == 0x066f && - dev->descriptor.idProduct == 0x2010) - || - /* SanDisk Corporation Cruzer Micro 20044318410546613953 */ - (dev->descriptor.idVendor == 0x0781 && - dev->descriptor.idProduct == 0x5151) - || - /* - * SanDisk Corporation U3 Cruzer Micro 1/4GB - * Flash Drive 000016244373FFB4 - */ - (dev->descriptor.idVendor == 0x0781 && - dev->descriptor.idProduct == 0x5406) - ) - USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n"); - else - ss->transport_reset(ss); - pccb->pdata = usb_stor_buf; dev_desc->target = dev->devnum; -- 1.7.0.4

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[U-Boot] [PATCH 1/2] usb: musb: blackfin: make clkin configurable
by Mike Frysinger 25 Mar '11

25 Mar '11

Not everyone has a 24MHz clkin to the USB, so let board porters override. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/usb/musb/blackfin_usb.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/drivers/usb/musb/blackfin_usb.c b/drivers/usb/musb/blackfin_usb.c index 38aceb2..0eb19a0 100644 --- a/drivers/usb/musb/blackfin_usb.c +++ b/drivers/usb/musb/blackfin_usb.c @@ -15,6 +15,10 @@ #include "musb_core.h" +#ifndef CONFIG_USB_BLACKFIN_CLKIN +#define CONFIG_USB_BLACKFIN_CLKIN 24 +#endif + /* MUSB platform configuration */ struct musb_config musb_cfg = { .regs = (struct musb_regs *)USB_FADDR, @@ -109,7 +113,8 @@ int musb_platform_init(void) } /* Configure PLL oscillator register */ - bfin_write_USB_PLLOSC_CTRL(0x30a8); + bfin_write_USB_PLLOSC_CTRL(0x3080 | + ((480 / CONFIG_USB_BLACKFIN_CLKIN) << 1)); SSYNC(); bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1); -- 1.7.4.1

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[U-Boot] [PATCH V3] arm: Tegra2: add support for A9 CPU init
by Tom Warren 25 Mar '11

25 Mar '11

Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- Changes for V2: - Remove returns in void functions - Move inline assembly code to .S file - Simplify some if/else code, break out common code - Minimize the use of local vars - Inline some single-instance functions - Remove TRUE/FALSE define, use 1/0 instead - Replace memset of mem-mapped regs w/loop of writel's Changes for V3: - Fix C-style comments in lowlevel_init.S cache_configure arch/arm/cpu/armv7/start.S | 12 + arch/arm/cpu/armv7/tegra2/Makefile | 2 +- arch/arm/cpu/armv7/tegra2/ap20.c | 366 ++++++++++++++++++++++++++++ arch/arm/cpu/armv7/tegra2/ap20.h | 105 ++++++++ arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 70 ++++++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 27 ++ arch/arm/include/asm/arch-tegra2/pmc.h | 8 + arch/arm/include/asm/arch-tegra2/scu.h | 43 ++++ arch/arm/include/asm/arch-tegra2/tegra2.h | 5 + board/nvidia/common/board.c | 10 + board/nvidia/common/board.h | 29 +++ include/configs/harmony.h | 1 + include/configs/seaboard.h | 3 +- include/configs/tegra2-common.h | 2 + 14 files changed, 681 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.c create mode 100644 arch/arm/cpu/armv7/tegra2/ap20.h create mode 100644 arch/arm/include/asm/arch-tegra2/scu.h create mode 100644 board/nvidia/common/board.h diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index cb4f92f..4b36693 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -70,6 +70,18 @@ _end_vect: _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_TEGRA2 +/* + * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). + * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, + * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU + * to pick up its reset vector, which points here. + */ +.globl _armboot_start +_armboot_start: + .word _start +#endif + /* * These are defined in the board-specific linker script. */ diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index 687c887..f1ea915 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := board.o sys_info.o timer.o +COBJS := ap20.o board.o sys_info.o timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c new file mode 100644 index 0000000..d0ad41f --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -0,0 +1,366 @@ +/* +* (C) Copyright 2010-2011 +* NVIDIA Corporation <www.nvidia.com> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include "ap20.h" +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/pmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/scu.h> +#include <common.h> + +u32 s_first_boot = 1; + +static void enable_cpu_clock(int enable) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg, clk; + + /* + * NOTE: + * Regardless of whether the request is to enable or disable the CPU + * clock, every processor in the CPU complex except the master (CPU 0) + * will have it's clock stopped because the AVP only talks to the + * master. The AVP does not know (nor does it need to know) that there + * are multiple processors in the CPU complex. + */ + + if (enable) { + /* Wait until all clocks are stable */ + udelay(PLL_STABILIZATION_DELAY); + + writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); + writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); + } + + /* Fetch the register containing the main CPU complex clock enable */ + reg = readl(&clkrst->crc_clk_out_enb_l); + reg |= CLK_ENB_CPU; + + /* + * Read the register containing the individual CPU clock enables and + * always stop the clock to CPU 1. + */ + clk = readl(&clkrst->crc_clk_cpu_cmplx); + clk |= CPU1_CLK_STP; + + if (enable) { + /* Unstop the CPU clock */ + clk &= ~CPU0_CLK_STP; + } else { + /* Stop the CPU clock */ + clk |= CPU0_CLK_STP; + } + + writel(clk, &clkrst->crc_clk_cpu_cmplx); + writel(reg, &clkrst->crc_clk_out_enb_l); +} + +static int is_cpu_powered(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; +} + +static void remove_cpu_io_clamps(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + + /* Remove the clamps on the CPU I/O signals */ + reg = readl(&pmc->pmc_remove_clamping); + reg |= CPU_CLMP; + writel(reg, &pmc->pmc_remove_clamping); + + /* Give I/O signals time to stabilize */ + udelay(IO_STABILIZATION_DELAY); +} + +static void powerup_cpu(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + + if (!is_cpu_powered()) { + /* Toggle the CPU power state (OFF -> ON) */ + reg = readl(&pmc->pmc_pwrgate_toggle); + reg &= PARTID_CP; + reg |= START_CP; + writel(reg, &pmc->pmc_pwrgate_toggle); + + /* Wait for the power to come up */ + while (!is_cpu_powered()) + ; /* Do nothing */ + + /* + * Remove the I/O clamps from CPU power partition. + * Recommended only on a Warm boot, if the CPU partition gets + * power gated. Shouldn't cause any harm when called after a + * cold boot according to HW, probably just redundant. + */ + remove_cpu_io_clamps(); + } +} + +static void enable_cpu_power_rail(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + + reg = readl(&pmc->pmc_cntrl); + reg |= CPUPWRREQ_OE; + writel(reg, &pmc->pmc_cntrl); + + /* + * The TI PMU65861C needs a 3.75ms delay between enabling + * the power rail and enabling the CPU clock. This delay + * between SM1EN and SM1 is for switching time + the ramp + * up of the voltage to the CPU (VDD_CPU from PMU). + */ + udelay(3750); +} + +static void reset_A9_cpu(int reset) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg, cpu; + + /* + * NOTE: Regardless of whether the request is to hold the CPU in reset + * or take it out of reset, every processor in the CPU complex + * except the master (CPU 0) will be held in reset because the + * AVP only talks to the master. The AVP does not know that there + * are multiple processors in the CPU complex. + */ + + /* Hold CPU 1 in reset */ + cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1; + writel(cpu, &clkrst->crc_cpu_cmplx_set); + + reg = readl(&clkrst->crc_rst_dev_l); + if (reset) { + /* Now place CPU0 into reset */ + cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0; + writel(cpu, &clkrst->crc_cpu_cmplx_set); + + /* Enable master CPU reset */ + reg |= SWR_CPU_RST; + } else { + /* Take CPU0 out of reset */ + cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0; + writel(cpu, &clkrst->crc_cpu_cmplx_clr); + + /* Disable master CPU reset */ + reg &= ~SWR_CPU_RST; + } + + writel(reg, &clkrst->crc_rst_dev_l); +} + +static void clock_enable_coresight(int enable) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 rst, clk, src; + + rst = readl(&clkrst->crc_rst_dev_u); + clk = readl(&clkrst->crc_clk_out_enb_u); + + if (enable) { + rst &= ~SWR_CSITE_RST; + clk |= CLK_ENB_CSITE; + } else { + rst |= SWR_CSITE_RST; + clk &= ~CLK_ENB_CSITE; + } + + writel(clk, &clkrst->crc_clk_out_enb_u); + writel(rst, &clkrst->crc_rst_dev_u); + + if (enable) { + /* + * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by + * 1.5, giving an effective frequency of 144MHz. + * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor + * (bits 7:0), so 00000001b == 1.5 (n+1 + .5) + */ + src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); + writel(src, &clkrst->crc_clk_src_csite); + + /* Unlock the CPU CoreSight interfaces */ + rst = 0xC5ACCE55; + writel(rst, CSITE_CPU_DBG0_LAR); + writel(rst, CSITE_CPU_DBG1_LAR); + } +} + +void start_cpu(u32 reset_vector) +{ + /* Enable VDD_CPU */ + enable_cpu_power_rail(); + + /* Hold the CPUs in reset */ + reset_A9_cpu(1); + + /* Disable the CPU clock */ + enable_cpu_clock(0); + + /* Enable CoreSight */ + clock_enable_coresight(1); + + /* + * Set the entry point for CPU execution from reset, + * if it's a non-zero value. + */ + if (reset_vector) + writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); + + /* Enable the CPU clock */ + enable_cpu_clock(1); + + /* If the CPU doesn't already have power, power it up */ + if (!is_cpu_powered()) + powerup_cpu(); + + /* Take the CPU out of reset */ + reset_A9_cpu(0); +} + + +void halt_avp(void) +{ + for (;;) { + writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \ + | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)), + FLOW_CTLR_HALT_COP_EVENTS); + } +} + +void enable_scu(void) +{ + struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; + u32 reg; + + /* If SCU already setup/enabled, return */ + if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) + return; + + /* Invalidate all ways for all processors */ + writel(0xFFFF, &scu->scu_inv_all); + + /* Enable SCU - bit 0 */ + reg = readl(&scu->scu_ctrl); + reg |= SCU_CTRL_ENABLE; + writel(reg, &scu->scu_ctrl); +} + +void init_pmc_scratch(void) +{ + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + int i; + + /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ + for (i = 0; i < 23; i++) + writel(0, &pmc->pmc_scratch1+i); + + /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ + writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); +} + +void cpu_start(void) +{ + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + + /* enable JTAG */ + writel(0xC0, &pmt->pmt_cfg_ctl); + + if (s_first_boot) { + /* + * Need to set this before cold-booting, + * otherwise we'll end up in an infinite loop. + */ + s_first_boot = 0; + cold_boot(); + } +} + +void tegra2_start() +{ + if (s_first_boot) { + /* Init Debug UART Port (115200 8n1) */ + uart_init(); + + /* Init PMC scratch memory */ + init_pmc_scratch(); + } + +#ifdef CONFIG_ENABLE_CORTEXA9 + /* take the mpcore out of reset */ + cpu_start(); + + /* configure cache */ + cache_configure(); +#endif +} + +extern ulong _armboot_start; +u32 cpu_boot_stack = CPU_EARLY_BOOT_STACK_LIMIT; +u32 avp_boot_stack = AVP_EARLY_BOOT_STACK_LIMIT; +u32 proc_tag = PG_UP_TAG_0_PID_CPU & 0xFF; + +/* + * TBD: Move cold_boot() to assembly file. + * Values/offsets of the table vars make this difficult. + */ + +void cold_boot(void) +{ + asm volatile( + "msr cpsr_c, #0xD3 \n" + /* + * Check current processor: CPU or AVP? + * If CPU, go to CPU boot code, else continue on AVP path. + */ + "mov r0, %0 \n" + "ldrb r2, [r0, %1] \n" + /* are we the CPU? */ + "cmp r2, %2 \n" + "mov sp, %3 \n" + /* yep, we are the CPU */ + "bxeq %4 \n" + + /* AVP initialization follows this path */ + "mov sp, %5 \n" + /* Init and start CPU */ + "b startup_cpu \n" + : + : "i"(NV_PA_PG_UP_BASE), + "i"(PG_UP_TAG_0), + "r"(proc_tag), + "r"(cpu_boot_stack), + "r"(_armboot_start), + "r"(avp_boot_stack) + : "r0", "r2", "cc", "lr" + ); +} diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/cpu/armv7/tegra2/ap20.h new file mode 100644 index 0000000..e463d68 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/ap20.h @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2010-2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <asm/types.h> + +/* Stabilization delays, in usec */ +#define PLL_STABILIZATION_DELAY (300) +#define IO_STABILIZATION_DELAY (1000) + +#define NVBL_PLLP_KHZ (216000) + +#define PLLX_ENABLED (1 << 30) +#define CCLK_BURST_POLICY 0x20008888 +#define SUPER_CCLK_DIVIDER 0x80000000 + +/* Calculate clock fractional divider value from ref and target frequencies */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) + +/* Calculate clock frequency value from reference and clock divider value */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) + +/* AVP/CPU ID */ +#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ +#define PG_UP_TAG_0 0x0 + +#define CORESIGHT_UNLOCK 0xC5ACCE55; + +/* AP20-Specific Base Addresses */ + +/* AP20 Base physical address of SDRAM. */ +#define AP20_BASE_PA_SDRAM 0x00000000 +/* AP20 Base physical address of internal SRAM. */ +#define AP20_BASE_PA_SRAM 0x40000000 +/* AP20 Size of internal SRAM (256KB). */ +#define AP20_BASE_PA_SRAM_SIZE 0x00040000 +/* AP20 Base physical address of flash. */ +#define AP20_BASE_PA_NOR_FLASH 0xD0000000 +/* AP20 Base physical address of boot information table. */ +#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM + +/* + * Super-temporary stacks for EXTREMELY early startup. The values chosen for + * these addresses must be valid on ALL SOCs because this value is used before + * we are able to differentiate between the SOC types. + * + * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its + * stack is placed below the AVP stack. Once the CPU stack has been moved, + * the AVP is free to use the IRAM the CPU stack previously occupied if + * it should need to do so. + * + * NOTE: In multi-processor CPU complex configurations, each processor will have + * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a + * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a + * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous + * CPU. + */ + +/* Common AVP early boot stack limit */ +#define AVP_EARLY_BOOT_STACK_LIMIT \ + (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2)) +/* Common AVP early boot stack size */ +#define AVP_EARLY_BOOT_STACK_SIZE 0x1000 +/* Common CPU early boot stack limit */ +#define CPU_EARLY_BOOT_STACK_LIMIT \ + (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE) +/* Common CPU early boot stack size */ +#define CPU_EARLY_BOOT_STACK_SIZE 0x1000 + +#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) +#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) +#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) + +#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) +#define FLOW_MODE_STOP 2 +#define HALT_COP_EVENT_JTAG (1 << 28) +#define HALT_COP_EVENT_IRQ_1 (1 << 11) +#define HALT_COP_EVENT_FIQ_1 (1 << 9) + +/* Prototypes */ + +void tegra2_start(void); +void uart_init(void); +void udelay(unsigned long); +void cold_boot(void); +void cache_configure(void); + diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S index 7f15746..83127b5 100644 --- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S +++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S @@ -26,6 +26,7 @@ #include <config.h> #include <version.h> + _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file @@ -58,6 +59,75 @@ lowlevel_init: mov pc, lr @ back to arch calling code + +.globl startup_cpu +startup_cpu: + @ Initialize the AVP, clocks, and memory controller + @ SDRAM is guaranteed to be on at this point + + ldr r0, =cold_boot @ R0 = reset vector for CPU + bl start_cpu @ start the CPU + + @ Transfer control to the AVP code + bl halt_avp + + @ Should never get here +_loop_forever2: + b _loop_forever2 + +.globl cache_configure +cache_configure: + stmdb r13!,{r14} + @ invalidate instruction cache + mov r1, #0 + mcr p15, 0, r1, c7, c5, 0 + + @ invalidate the i&d tlb entries + mcr p15, 0, r1, c8, c5, 0 + mcr p15, 0, r1, c8, c6, 0 + + @ enable instruction cache + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #(1<<12) + mcr p15, 0, r1, c1, c0, 0 + + bl enable_scu + + @ enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x41 + mcr p15, 0, r0, c1, c0, 1 + + @ Now flush the Dcache + mov r0, #0 + @ 256 cache lines + mov r1, #256 + +invalidate_loop: + add r1, r1, #-1 + mov r0, r1, lsl #5 + @ invalidate d-cache using line (way0) + mcr p15, 0, r0, c7, c6, 2 + + orr r2, r0, #(1<<30) + @ invalidate d-cache using line (way1) + mcr p15, 0, r2, c7, c6, 2 + + orr r2, r0, #(2<<30) + @ invalidate d-cache using line (way2) + mcr p15, 0, r2, c7, c6, 2 + + orr r2, r0, #(3<<30) + @ invalidate d-cache using line (way3) + mcr p15, 0, r2, c7, c6, 2 + cmp r1, #0 + bne invalidate_loop + + @ FIXME: should have ap20's L2 disabled too? +invalidate_done: + ldmia r13!,{pc} + + @ the literal pools origin .ltorg diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index 6d573bf..d67a5d7 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -149,6 +149,9 @@ struct clk_rst_ctlr { uint crc_clk_src_csite; /*_CSITE_0, 0x1D4 */ uint crc_reserved19[9]; /* 0x1D8-1F8 */ uint crc_clk_src_osc; /*_OSC_0, 0x1FC */ + uint crc_reserved20[80]; /* 0x200-33C */ + uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */ + uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */ }; #define PLL_BYPASS (1 << 31) @@ -162,4 +165,28 @@ struct clk_rst_ctlr { #define SWR_UARTA_RST (1 << 6) #define CLK_ENB_UARTA (1 << 6) +#define SWR_CPU_RST (1 << 0) +#define CLK_ENB_CPU (1 << 0) +#define SWR_CSITE_RST (1 << 9) +#define CLK_ENB_CSITE (1 << 9) + +#define SET_CPURESET0 (1 << 0) +#define SET_DERESET0 (1 << 4) +#define SET_DBGRESET0 (1 << 12) + +#define SET_CPURESET1 (1 << 1) +#define SET_DERESET1 (1 << 5) +#define SET_DBGRESET1 (1 << 13) + +#define CLR_CPURESET0 (1 << 0) +#define CLR_DERESET0 (1 << 4) +#define CLR_DBGRESET0 (1 << 12) + +#define CLR_CPURESET1 (1 << 1) +#define CLR_DERESET1 (1 << 5) +#define CLR_DBGRESET1 (1 << 13) + +#define CPU0_CLK_STP (1 << 8) +#define CPU1_CLK_STP (1 << 9) + #endif /* CLK_RST_H */ diff --git a/arch/arm/include/asm/arch-tegra2/pmc.h b/arch/arm/include/asm/arch-tegra2/pmc.h index 7ec9eeb..b1d47cd 100644 --- a/arch/arm/include/asm/arch-tegra2/pmc.h +++ b/arch/arm/include/asm/arch-tegra2/pmc.h @@ -121,4 +121,12 @@ struct pmc_ctlr { uint pmc_gate; /* _GATE_0, offset 15C */ }; +#define CPU_PWRED 1 +#define CPU_CLMP 1 + +#define PARTID_CP 0xFFFFFFF8 +#define START_CP (1 << 8) + +#define CPUPWRREQ_OE (1 << 16) + #endif /* PMC_H */ diff --git a/arch/arm/include/asm/arch-tegra2/scu.h b/arch/arm/include/asm/arch-tegra2/scu.h new file mode 100644 index 0000000..787ded0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/scu.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SCU_H_ +#define _SCU_H_ + +/* ARM Snoop Control Unit (SCU) registers */ +struct scu_ctlr { + uint scu_ctrl; /* SCU Control Register, offset 00 */ + uint scu_cfg; /* SCU Config Register, offset 04 */ + uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ + uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ + uint scu_reserved0[12]; /* reserved, offset 10-3C */ + uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ + uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ + uint scu_reserved1[2]; /* reserved, offset 48-4C */ + uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ + uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ +}; + +#define SCU_CTRL_ENABLE (1 << 0) + +#endif /* SCU_H */ diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index 9001b68..5813cd9 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -25,8 +25,12 @@ #define _TEGRA2_H_ #define NV_PA_SDRAM_BASE 0x00000000 +#define NV_PA_ARM_PERIPHBASE 0x50040000 +#define NV_PA_PG_UP_BASE 0x60000000 #define NV_PA_TMRUS_BASE 0x60005010 #define NV_PA_CLK_RST_BASE 0x60006000 +#define NV_PA_FLOW_BASE 0x60007000 +#define NV_PA_EVP_BASE 0x6000F000 #define NV_PA_APB_MISC_BASE 0x70000000 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) @@ -34,6 +38,7 @@ #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) #define NV_PA_PMC_BASE 0x7000E400 +#define NV_PA_CSITE_BASE 0x70040000 #define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index b2c412c..078547b 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -30,6 +30,7 @@ #include <asm/arch/clk_rst.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart.h> +#include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -37,6 +38,15 @@ const struct tegra2_sysinfo sysinfo = { CONFIG_TEGRA2_BOARD_STRING }; +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + debug("Board Early Init\n"); + tegra2_start(); + return 0; +} +#endif /* EARLY_INIT */ + /* * Routine: timer_init * Description: init the timestamp and lastinc value diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h new file mode 100644 index 0000000..47c7885 --- /dev/null +++ b/board/nvidia/common/board.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void tegra2_start(void); + +#endif /* BOARD_H */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index d004f31..34bd899 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -46,4 +46,5 @@ #define CONFIG_MACH_TYPE MACH_TYPE_HARMONY #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ +#define CONFIG_BOARD_EARLY_INIT_F #endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index fd87560..06ce3e2 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -37,7 +37,8 @@ #define CONFIG_TEGRA2_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_TEGRA_SEABOARD +#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ +#define CONFIG_BOARD_EARLY_INIT_F #endif /* __CONFIG_H */ diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 4f4374a..2924325 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -33,6 +33,8 @@ #define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */ #define CONFIG_L2_OFF /* No L2 cache */ +#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */ + #include <asm/arch/tegra2.h> /* get chip and board defs */ /* -- 1.7.4.1

2 1

[U-Boot] Kan dette brevet røre ved ditt hjerte / fra Miss.Engel
by Engel 25 Mar '11

25 Mar '11

Kjæreste Love Kan dette brevet røre ved ditt hjerte og kommer til å redde min Vennligst ikke være overraskende eller blir fornærmet når du får denne meldingen fra meg, det bare det at jeg har vært nødt til å stole på deg på grunn av min situasjon her i leiren flyktninger, La meg først av alt presentere meg selv til deg, og jeg vil kreve det beste av din ærlighet etter å vite om hvem som jeg er, vil jeg virkelig at vi skal ha et godt forhold til tross for noe fordi jeg har denne følelsen av at du er den personen jeg har vært i bønn og håper å ha som en venn og jeg tror dere vil vurdere min situasjon og indre ønske om å møte deg en dag, tror jeg at du svarer ja til denne meldingen vil være begynnelsen på en lengter etter varig forhold uten forråde, MIN PROFIL Jeg bestemte meg for å kontakte deg på grunn av alvoret i min situasjon her og etter å ha lest din profil som vil tiltrekke seg alle rimelige kvinne. Mitt navn er Miss.Engel Lemi Milla. Jeg er 28 år gammel jente fra et land som heter republikken SUDAN, i Afrika, er jeg den eneste datter av sen Mr.Jimmy Lemi Milla. den tidligere ministeren for Co-operatives og distriktsutvikling i SUDAN republikk under ledelse av president Omar al-Bashir, Min far ble drept av regjeringen til president Omar al-Bashir, fordi han drepte min far for ledende (Sudan People's Liberation Movement) (SPLM) min avdøde far ble drept den 9. februar 2011 Skuddsår, Du kan lese nettsiden nedenfor: http://www.bbc.co.uk/news/world-africa-12403620 Jeg er tvunget til å kontakte deg på grunn av mishandling jeg, jeg mottar fra min mor trinn. Hun planla å ta bort all min avdøde fars egne og egenskaper fra meg siden det uventede dødsfallet til min kjære far. Samtidig jeg ønsket å flykte fra Afrika til hvor som helst i verden, men hun gjemmer bort mine internasjonale pass og andre verdifulle dokumenter reise. Heldigvis har hun ikke oppdaget hvor jeg holdt min Fars fil som inneholder viktige dokumenter. Så jeg bestemte meg for å løpe til flyktningleiren hvor jeg er i dag søker asyl under private veldedige organisasjon for flyktninger i Ouagadougou, i et vest-afrikanske landet kaller republikken Burkina Faso. Jeg ønsker å kontakte deg personlig for et langvarig forhold som kan føre oss inn i et sterkt partnerskap om vi arbeider med oppriktige mening på denne transaksjonen, Min far i salig minne deponert summen av (US $ 3, 700, 000,00) (Three Million Syv hundre tusen dollar) i en Bank med mitt navn som pårørende. Men, skal jeg frem til dere alle nødvendige dokumenter om bekreftelse på at du aksepterer å hjelpe meg for overføring og investeringer i fondet. Som du vil hjelpe meg å investere pengene fordi jeg vil like å fullføre mine studier, før krigen var jeg i mitt første år på universitetet, da krisen startet. Etter transaksjonen vil du ordne for min tur til å bli med over i ditt land etter transaksjonen for å aktivere dele våre følelser for hverandre, Vi vil investere i fondet meg og deg, eller hvis du ikke skal bo med meg da Det vil være en glede for meg å kompensere deg med 15% av det totale penger for dine tjenester og balansen skal være min investeringskapital. Dette er grunnen til at jeg bestemte meg for å kontakte deg. Vennligst all kommunikasjon skal gjennom denne e-postadressen kun for konfidensielle formål. Så snart jeg mottar positive responsen viser din interesse vil jeg sette ting i handling umiddelbart. I lys av ovennevnte, vil jeg sette pris på et hurtig svar som indikerer din evne og vilje til å håndtere denne transaksjonen forholdet og oppriktig. Jeg venter din påtrengende og positiv respons. Vennligst hold dette bare til deg selv du Jeg ber dere ikke å avsløre denne informasjonen til noe kroppen før jeg kommer over til ditt land etter transaksjonen, Jeg har lagt min bilde og et annet bilde av min avdøde far, Svar umiddelbart slik at jeg vil gi deg flere detaljer om transaksjonen, Med vennlig hilsen, Engel Dearest Love May this letter touch your heart and come to my rescue Please Do not be surprise or get offended when you will receive this message from me, It just that I have been obliged to trust you due to my situation here in the refugees camp, Let me first of all introduce my self to you, and I will require the best of your honesty after knowing about whom that I am, I will really like us to have a good relationship in spite of anything because I have this feeling that you are the person I have been praying and hoping to have as a friend and I believe you will consider my situation and inner desire to meet you some day, I believe that your replying yes to this message will be the beginning of a longs lasting relationship without a betray, MY PROFILE I decided to contact you because of the urgency of my situation here and after reading your profile which will attract every reasonable woman. My name is Miss.Engel Lemi Milla . I am 28 years old girl from a country called republic of SUDAN, in Africa, I am the only daughter of Late Mr.Jimmy Lemi Milla. the former Minister of Co-operatives and Rural Development of SUDAN republic under the leadership of president Omar al-Bashir, My father was killed by the government of President Omar al-Bashir, because he killed my father for leading ( Sudan People's Liberation Movement ) (SPLM) my late father was killed on 9 February 2011 by Gun shot, You can read the website below : http://www.bbc.co.uk/news/world-africa-12403620 I am constrained to contact you because of the maltreatment I, am receiving from my step mother. She planned to take away all my late father's treasury and properties from me since the unexpected death of my beloved Father. Meanwhile I wanted to escape from Africa to any where in the world but she hide away my international passport and other valuable traveling documents. Luckily she did not discover where I kept my Fathers File which contains important documents. So I decided to run to the refugee camp where I am presently seeking asylum under the Private charity organization for the Refugees in Ouagadougou , in a west African country call republic of BURKINA FASO . I wish to contact you personally for a long term relationship that may lead us into a strong partnership if we work with sincere mind in this transaction , My father of blessed memory deposited the sum of (US$3, 700, 000.00) ( Three Million Seven Hundred Thousand Dollars) in a Bank with my name as the next of kin. However, I shall forward to you all the necessary documents on confirmation of your acceptance to assist me for the transfer and investment of the fund. As you will help me to invest the money because I will like to complete my studies, before the war I was in my 1st year in the university, when the crisis started. After the transaction you will arrange for my trip to join you over in your country after the transaction to enable share our feeling for each other , We will invest the fund me and you, or if you don't intend staying with me then It will be my pleasure to compensate you with 15% of the total money for your services and the balance shall be my investment capital. This is the reason why I decided to contact you. Please all communications should be through this email address only for confidential purposes. As soon as I receive your positive response showing your interest I will put things into action immediately. In the light of the above, I will appreciate an urgent reply indicating your ability and willingness to handle this transaction relationship and sincerely. I await your urgent and positive response. Please do keep this only to your self please I beg you not to disclose this information to any body until I come over to your country after the transaction , I have attached my picture and another picture of my late father, Reply immediately so that I will give you more details concerning the transaction , Yours Sincerely, Engel

1 0

[U-Boot] Update Your E-Webmail Account ! ! ! Withing The Next {3 Days}
by E-MAIL(WEB-UPDATE) 25 Mar '11

25 Mar '11

Dear, "Webmail Users" Email Account Owner, This message is from ""E-Webmail "" messaging center to all "Client & Other Webmails" email account owners. We are currently upgrading our data base and e-mail account center. We are deleting all non responding email accounts due to congestion just to create more space for new accounts. To prevent your account from being deleted you will have to update it by providing the below informations so that we will know that it's a present and its being current used at this time. We have been sending this notice to all our "Client & Webmail" email account owners and this is the last notice/verification exercise. CONFIRM YOUR EMAIL IDENTITY BELOW UserID: 88094 Full Name: Staff/StudentNumber: Email: Password: Secret Question: Answer: Warning!!! Account owner that refuses to update his or her account within three days of receiving this warning will lose his or her account permanently.Thank you for using webmail account. Warning to UserID: 88094 Code:VX2G99AAJ Thanks, Customer Care. World Wide Web Admin Electronic Advance Web System

1 0

[U-Boot] Update Your E-Webmail Account ! ! ! Withing The Next {3 Days}
by E-MAIL(WEB-UPDATE) 25 Mar '11

25 Mar '11

Dear, "Webmail Users" Email Account Owner, This message is from ""E-Webmail "" messaging center to all "Client & Other Webmails" email account owners. We are currently upgrading our data base and e-mail account center. We are deleting all non responding email accounts due to congestion just to create more space for new accounts. To prevent your account from being deleted you will have to update it by providing the below informations so that we will know that it's a present and its being current used at this time. We have been sending this notice to all our "Client & Webmail" email account owners and this is the last notice/verification exercise. CONFIRM YOUR EMAIL IDENTITY BELOW UserID: 88094 Full Name: Staff/StudentNumber: Email: Password: Secret Question: Answer: Warning!!! Account owner that refuses to update his or her account within three days of receiving this warning will lose his or her account permanently.Thank you for using webmail account. Warning to UserID: 88094 Code:VX2G99AAJ Thanks, Customer Care. World Wide Web Admin Electronic Advance Web System

1 0

[U-Boot] [PATCH] powerpc/85xx: Fixup determining PME, FMan freq
by Kumar Gala 25 Mar '11

25 Mar '11

On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some additional rules to determining the various frequencies that PME & FMan IP blocks run at. We need to take into account: * Reduced number of Core Complex PLL clusters * HWA_ASYNC_DIV (allows for /2 or /4 options) On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs the PME & FMan blocks utilize the second Core Complex PLL. On SoCs like p4080 with 4 Core Complex PLLs we utilize the third Core Complex PLL for PME & FMan blocks. On P2040/P3041/P5020 we have the added feature that we can divide the PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080 this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be set to 0 and this gets a backward compatiable /2 behavior. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/speed.c | 38 ++++++++++++++++++++++------- arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++ 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e762269..2caff4b 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -108,25 +108,45 @@ void get_sys_info (sys_info_t * sysInfo) #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 #define FM2_CLK_SEL 0x20000000 +#define HWA_ASYNC_DIV 0x04000000 +#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) +#define HWA_CC_PLL 1 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) +#define HWA_CC_PLL 2 +#else +#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case +#endif rcw_tmp = in_be32(&gur->rcwsr[7]); #ifdef CONFIG_SYS_DPAA_PME - if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = freqCC_PLL[2] / 2; - else + if (rcw_tmp & PME_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqPME = sysInfo->freqSystemBus / 2; + } #endif #ifdef CONFIG_SYS_DPAA_FMAN - if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM1_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + } #if (CONFIG_SYS_NUM_FMAN) == 2 - if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM2_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + } #endif #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1f4dee4..41fd86c 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -257,6 +257,7 @@ #elif defined(CONFIG_PPC_P2040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -266,6 +267,7 @@ #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -276,12 +278,14 @@ #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 @@ -304,6 +308,7 @@ /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 @@ -314,6 +319,7 @@ #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 -- 1.7.2.3

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[U-Boot] [PATCH] powerpc/85xx: Fix determining Fman freq on P1023
by Kumar Gala 25 Mar '11

25 Mar '11

On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2 of it. Also we only have one Fman so no need for the code to deal with a second. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/speed.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 2caff4b..c4c156d 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -196,10 +196,7 @@ void get_sys_info (sys_info_t * sysInfo) #endif #ifdef CONFIG_SYS_DPAA_FMAN - sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; -#if (CONFIG_SYS_NUM_FMAN) == 2 - sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; -#endif + sysInfo->freqFMan[0] = sysInfo->freqSystemBus; #endif #endif /* CONFIG_FSL_CORENET */ -- 1.7.2.3

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