March 2011 - U-Boot

[U-Boot] [PATCH v2] ftsmc020: enhanced features and unnested structures
by Macpaul Lin 31 Mar '11

31 Mar '11

1. Enhance ftsmc020 according to datasheets. 2. Fix relocation related declaration. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Changes for v2: - Remove assembly register offsets for support lowlevel_init.S. - The nested structure of register offsets has been rewrote. - Fix relocation related declaration. Note: This patch should be applied after patch "[U-Boot,v2,4/4] ftsmc020: move ftsmc020 static mem controller to driver/mtd" (/patch/87862/) is applied. drivers/mtd/ftsmc020.c | 7 +++---- include/faraday/ftsmc020.h | 19 +++++++++++++------ 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/ftsmc020.c b/drivers/mtd/ftsmc020.c index b027685..ddeb3a4 100644 --- a/drivers/mtd/ftsmc020.c +++ b/drivers/mtd/ftsmc020.c @@ -27,12 +27,10 @@ struct ftsmc020_config { unsigned int timing; }; -static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; - -static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; - static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg) { + struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; + if (bank > 3) { printf("bank # %u invalid\n", bank); return; @@ -44,6 +42,7 @@ static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg) void ftsmc020_init(void) { + struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; int i; for (i = 0; i < ARRAY_SIZE(config); i++) diff --git a/include/faraday/ftsmc020.h b/include/faraday/ftsmc020.h index 95d9500..59c6f8e 100644 --- a/include/faraday/ftsmc020.h +++ b/include/faraday/ftsmc020.h @@ -25,13 +25,15 @@ #ifndef __ASSEMBLY__ +struct ftsmc020_bank { + unsigned int cr; + unsigned int tpr; +}; + struct ftsmc020 { - struct { - unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ - unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ - } bank[4]; - unsigned int pad[8]; /* 0x20 - 0x3c */ - unsigned int ssr; /* 0x40 */ + struct ftsmc020_bank bank[4]; /* 0x00 - 0x1c */ + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ }; void ftsmc020_init(void); @@ -46,6 +48,10 @@ void ftsmc020_init(void); #define FTSMC020_BANK_WPROT (1 << 11) +#define FTSMC020_BANK_TYPE1 (1 << 10) +#define FTSMC020_BANK_TYPE2 (1 << 9) +#define FTSMC020_BANK_TYPE3 (1 << 8) + #define FTSMC020_BANK_SIZE_32K (0xb << 4) #define FTSMC020_BANK_SIZE_64K (0xc << 4) #define FTSMC020_BANK_SIZE_128K (0xd << 4) @@ -57,6 +63,7 @@ void ftsmc020_init(void); #define FTSMC020_BANK_SIZE_8M (0x3 << 4) #define FTSMC020_BANK_SIZE_16M (0x4 << 4) #define FTSMC020_BANK_SIZE_32M (0x5 << 4) +#define FTSMC020_BANK_SIZE_64M (0x6 << 4) #define FTSMC020_BANK_MBW_8 (0x0 << 0) #define FTSMC020_BANK_MBW_16 (0x1 << 0) -- 1.7.3.5

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[U-Boot] [PATCH 1/2] p4080ds: add README.p4080ds which documents the "serdes" hwconfig option
by Kumar Gala 31 Mar '11

31 Mar '11

From: Timur Tabi <timur(a)freescale.com> Add documentation for the "serdes" hwconfig option, which is used to specify the status of SerDes banks two and three for the SERDES8 erratum work-around. Signed-off-by: Timur Tabi <timur(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- doc/README.p4080ds | 32 ++++++++++++++++++++++++++++++++ 1 files changed, 32 insertions(+), 0 deletions(-) create mode 100644 doc/README.p4080ds diff --git a/doc/README.p4080ds b/doc/README.p4080ds new file mode 100644 index 0000000..3ed59a8 --- /dev/null +++ b/doc/README.p4080ds @@ -0,0 +1,32 @@ +Overview +-------- +The P4080DS is a Freescale reference board that hosts the eight-core P4080 SOC. + +SerDes hwconfig configuration +----------------------------- +The P4080 RCW includes three sets of bits the specify which SerDes lanes +should be powered down: SRDS_LPD_B1 (for bank one), SRDS_LPD_B2 (for bank two), +and SRDS_LPD_B3 (for bank three). Each of these contains four bits, one for +each lane in the bank. SerDes Erratum SERDES8 requires that SRDS_LPD_B2 and +SRDS_LPD_B3 be set to 0b1111. This forces banks two and three to be powered +down at reset. + +To re-enable these banks in U-Boot, two hwconfig are available: +"fsl_srds_lpd_b2" and "fsl_srds_lpd_b3". The value passed via fsl_srds_lpd_b2 +is written into SRDS_LPD_B2, and the value passed via fsl_srds_lpd_b3 is into +SRDS_LPD_B3. Each bit represents one of each bank, and a value of '1' +indicates that the lane should be powered down. + +For example, to indicate that both SerDes banks 2 and 3 are powered down, add +the following to hwconfig: + + serdes:fsl_srds_lpd_b2=0xf,fsl_srds_lpd_b3=0xf + +The "0xf" is a mask that corresponds to the 4 lanes A-D. The most significant +bit corresponds to lane A. To indicate that just lane A of bank 3 is to be +powered down, use: + + serdes:fsl_srds_lpd_b3=8 + +These options should be specified only if U-Boot does not automatically power +on the correct lanes. -- 1.7.3.4

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[U-Boot] [PATCH] powerpc/8xxx: Fix typo for address hashing message
by Kumar Gala 31 Mar '11

31 Mar '11

Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index ee7ef0f..02d069c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1305,7 +1305,7 @@ static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) { if (popts->addr_hash) { ddr->ddr_eor = 0x40000000; /* address hash enable */ - puts("Addess hashing enabled.\n"); + puts("Address hashing enabled.\n"); } } -- 1.7.3.4

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[U-Boot] [PATCH v6 0/4] Board support series for the eXMeritus HWW-1U-1A
by Kyle Moffett 31 Mar '11

31 Mar '11

This is the latest respin of the eXMeritus HWW-1U-1A board support patches, rebased onto the 'next' branch of git://git.denx.de/u-boot-mpc85xx.git As Wolfgang NAKed the more involved reset rework, I've moved the patch for a simple board-specific restart hook back into this series. I believe these 4 patches are ready to be merged, as all concerns presented so far have been addressed. Cheers, Kyle Moffett

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Re: [U-Boot] [PATCH] ftsmc020: enhance for features and asm support.
by macpaul＠andestech.com 31 Mar '11

31 Mar '11

Hi Wolfgnag > In message > <1300965924-20508-1-git-send-email-macpaul(a)andestech.com> you wrote: > > 1. Enhance ftsmc020 according to datasheets. > > 2. Add assembly register offsets for support lowlevel_init.S. > > NAK. Such register offsets should be automatically generated from the > respective C structs using make-asm-offsets; see the > generic-asm-offsets.h / asm-offsets.s build rules in the top level > Makefile. > Neither I ran the command "tools/scripts/make-asm-offsets include/faraday/ftsmc020.h include/faraday/ftsmc020-genasm.h" nor I ran sed -ne "/^->/{s:->#$.*$:/* \1 */:; \ s:^->$[^ ]*$ [\$#]*$[-0-9]*$ $.*$:#define \1 (\2) /* \3 */:; \ s:^->$[^ ]*$ [\$#]*$[^ ]*$ $.*$:#define \1 \2 /* \3 */:; \ s:->::; p;}" include/faraday/ftsmc020-genasm.h could be work. I also tested file faraday/ftpmu010.h. It get the same output with output 'sed: -e expression #1, char 47: unknown command: `['.' Did I execute the script in wrong method? Is there a problem about this script? Moreover, the structure of ftsmc020 was nested like struct ftsmc020 { struct { unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ } bank[4]; unsigned int pad[8]; /* 0x20 - 0x3c */ unsigned int ssr; /* 0x40 */ }; I didn't see the sed script could support this kind of nested structure declaration. I guess the sed script could be applied to plain structure declareation. Maybe I have a diffcult here. If the script is needed to be rewrote to adapt nested declaration, It might need have some complicaticity about parse difference kind of nested structure and array. It seems I need to rewrite the structure to be adaptable to the sed script. Any suggestion? Best regards, Macpaul Lin CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

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[U-Boot] [PATCH] powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020
by Kumar Gala 31 Mar '11

31 Mar '11

From: Laurentiu TUDOR <Laurentiu.Tudor(a)freescale.com> We utilize the compatible string to find the node to add fsl,liodn property to. However P3041 & P5020 don't have "fsl,p4080-pcie" compatible for their PCIe controllers as they aren't backwards compatible. Allow the macro's to specify the PCIe compatible to use to allow SoC uniqueness. On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the PCIe controllers. Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/p3041_ids.c | 10 +++++----- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 8 ++++---- arch/powerpc/cpu/mpc85xx/p5020_ids.c | 10 +++++----- arch/powerpc/include/asm/fsl_liodn.h | 4 ++-- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index febbee9..1255898 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), - SET_PCI_LIODN(4, 196), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index df25048..fd155c8 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -44,9 +44,9 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 156), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), + SET_PCI_LIODN("fsl,p4080-pcie", 1, 193), + SET_PCI_LIODN("fsl,p4080-pcie", 2, 194), + SET_PCI_LIODN("fsl,p4080-pcie", 3, 195), SET_DMA_LIODN(1, 196), SET_DMA_LIODN(2, 197), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index febbee9..1255898 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), - SET_PCI_LIODN(4, 196), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index f76676c..0ec5c0a 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -70,8 +70,8 @@ extern void fdt_fixup_liodn(void *blob); SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\ CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET) -#define SET_PCI_LIODN(pciNum, liodn) \ - SET_GUTS_LIODN("fsl,p4080-pcie", liodn, pex##pciNum##liodnr,\ +#define SET_PCI_LIODN(compat, pciNum, liodn) \ + SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) /* reg nodes for DMA start @ 0x300 */ -- 1.7.2.3

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[U-Boot] Please pull u-boot-mpc85xx.git (updated)
by Kumar Gala 31 Mar '11

31 Mar '11

[ Pull in one other HW / SoC related fix in for v2011.03 ] The following changes since commit cb815e5ff979e36d68df130a810d34de4bf93289: Prepare v (2011-03-27 21:50:07 +0200) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master Jiang Yutang (1): powerpc/85xx: Enable various errata on P1022/P1013 SoCs Prabhakar Kushwaha (1): powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs arch/powerpc/cpu/mpc85xx/p1021_serdes.c | 49 ++++++++++++++++++++++++++++- arch/powerpc/include/asm/config_mpc85xx.h | 10 ++++++ drivers/pci/fsl_pci_init.c | 7 ++++ include/configs/P1022DS.h | 1 + include/pci.h | 1 + 5 files changed, 67 insertions(+), 1 deletions(-)

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[U-Boot] Please pull u-boot-cfi-flash/master
by Stefan Roese 31 Mar '11

31 Mar '11

Hi Wolfgang, please pull this CFI fix: The following changes since commit cb815e5ff979e36d68df130a810d34de4bf93289: Prepare v (2011-03-27 21:50:07 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-cfi-flash.git master Martin Krause (1): cfi_flash: fix bug with flash banks with different sector numbers drivers/mtd/cfi_flash.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)

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[U-Boot] current head don;t compile for mpc52xx based boards
by Heiko Schocher 31 Mar '11

31 Mar '11

Hello, actual head doesn;t longer compile for the mpc52xx based digsy_mtc_rev5 board (and a fast check, it seems it is for mp52xx, 8xx, ppc4xx based boards): [hs@pollux u-boot]$ ./MAKEALL digsy_mtc_rev5 Configuring for digsy_mtc_rev5 - Board: digsy_mtc, Options: DIGSY_REV5 libstubs.o: In function `app_startup': /home/hs/charon/u-boot/examples/standalone/stubs.c:197: undefined reference to `__bss_end__' /home/hs/charon/u-boot/examples/standalone/stubs.c:197: undefined reference to `__bss_end__' make[1]: *** [hello_world] Fehler 1 make: *** [examples/standalone] Fehler 2 make: *** Warte auf noch nicht beendete Prozesse... ppc_6xx-size: './u-boot': No such file --------------------- SUMMARY ---------------------------- Boards compiled: 1 Boards with warnings or errors: 1 ( digsy_mtc_rev5 ) ---------------------------------------------------------- [hs@pollux u-boot]$ bisection it a bit shows: [hs@pollux u-boot]$ git bisect good 44c6e6591cb451ae606f8bde71dd5fb7b4002544 is the first bad commit commit 44c6e6591cb451ae606f8bde71dd5fb7b4002544 Author: Po-Yu Chuang <ratbert(a)faraday-tech.com> Date: Tue Mar 1 22:59:59 2011 +0000 rename _end to __bss_end__ Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> :040000 040000 9c41e6ba008d29cdb82ecfadea40f224a9c4771e 05f2d7e2e04bef1988ef537f47e7026e4a88a2a8 M arch :040000 040000 e8a97103de34f63145918cc1f119616c5deb8f22 c81f1ef95f863d263f8da1e80a97fdb8361cfe90 M board :040000 040000 29dc021a9988488c841b89c6bf6fab915584ce22 f6db95bc3432104adc5c993aafd7e410dd8f5d9b M examples :040000 040000 96fa70b40a37090b75e4b66df7d1fb61d120f198 faa9863deb077cfca92d31ec93c4b84a2e3f2e1d M nand_spl :040000 040000 927f744a35280f707a9b03059839e0dca45fecb5 6d7771394e8eb1f184dcb24a96453eadc9306c12 M onenand_ipl [hs@pollux u-boot]$ If I find time, I look in it, but if somebody has an idea, it would be great! bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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31 Mar '11

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