March 2011 - U-Boot

[U-Boot] [PATCHv2] powerpc: Minimal private libgcc to build on Debian
by Kyle Moffett 14 Apr '11

14 Apr '11

Standard Debian powerpc and powerpcspe systems only include hard-float libgcc in their native compilers, which causes scary build warnings when building U-Boot. Debian and other PowerPC-supporting distributions used to provide libgcc and other libraries in a "nof" (soft-float) form in the "multilib" packages. As they were completely unused by the distribution and therefore tended to be very buggy it was decided to save some time on the part of the maintainers and build-servers by removing them. Admittedly, right now the linker warnings do not indicate any problems, as the included routines do not use any floating point at all. The concern is that if floating-point code were ever added it might cause hard-float code to be unexpectedly included in U-Boot without generating a hard error. This would cause unexplained crashes or indeterminate results at runtime. The easiest way to resolve this is to borrow the routines that U-Boot needs from the Linux kernel, which has the same issue. Specifically, the routines are: _ashldi3(), _ashrdi3(), and _lshrdi3(). They were borrowed from arch/powerpc/kernel/misc_32.S as of v2.6.38-rc5, commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, and are GPLv2+. The Makefile framework was copied from the U-Boot ARM port. Signed-off-by: Kyle Moffett <Kyle.D.Moffett(a)boeing.com> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Kim Phillips <kim.phillips(a)freescale.com> Cc: Andy Fleming <afleming(a)gmail.com> Cc: Kumar Gala <kumar.gala(a)freescale.com> Cc: Stefan Roese <sr(a)denx.de> --- Changelog: v2: Resubmitted separately from the other HWW-1U-1A patches arch/powerpc/lib/Makefile | 23 ++++++++++++++++++++- arch/powerpc/lib/_ashldi3.S | 45 +++++++++++++++++++++++++++++++++++++++++ arch/powerpc/lib/_ashrdi3.S | 47 +++++++++++++++++++++++++++++++++++++++++++ arch/powerpc/lib/_lshrdi3.S | 45 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 159 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/lib/_ashldi3.S create mode 100644 arch/powerpc/lib/_ashrdi3.S create mode 100644 arch/powerpc/lib/_lshrdi3.S diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 724d8ee..cdd62a2 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -23,6 +23,19 @@ include $(TOPDIR)/config.mk +## Build a couple of necessary functions into a private libgcc +LIBGCC = $(obj)libgcc.o +GLSOBJS += _ashldi3.o +GLSOBJS += _ashrdi3.o +GLSOBJS += _lshrdi3.o +LGOBJS := $(addprefix $(obj),$(GLSOBJS)) \ + $(addprefix $(obj),$(GLCOBJS)) + +## But only build it if the user asked for it +ifdef USE_PRIVATE_LIBGCC +TARGETS += $(LIBGCC) +endif + LIB = $(obj)lib$(ARCH).o SOBJS-y += ppccache.o @@ -53,9 +66,14 @@ endif COBJS += $(sort $(COBJS-y)) -SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ + $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +TARGETS += $(LIB) + +all: $(TARGETS) + $(LIB): $(obj).depend $(OBJS) @if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\ then \ @@ -65,6 +83,9 @@ $(LIB): $(obj).depend $(OBJS) fi; $(call cmd_link_o_target, $(OBJS)) +$(LIBGCC): $(obj).depend $(LGOBJS) + $(call cmd_link_o_target, $(LGOBJS)) + ######################################################################### # defines $(obj).depend target diff --git a/arch/powerpc/lib/_ashldi3.S b/arch/powerpc/lib/_ashldi3.S new file mode 100644 index 0000000..e452f56 --- /dev/null +++ b/arch/powerpc/lib/_ashldi3.S @@ -0,0 +1,45 @@ +/* + * This code was copied from arch/powerpc/kernel/misc_32.S in the Linux + * kernel sources (commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, also + * known as 2.6.38-rc5). The source file copyrights are as follows: + * + * (C) Copyright 1995-1996 Gary Thomas (gdt(a)linuxppc.org) + * + * Largely rewritten by Cort Dougan (cort(a)cs.nmt.edu) + * and Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <config.h> + +/* + * Extended precision shifts. + * + * Updated to be valid for shift counts from 0 to 63 inclusive. + * -- Gabriel + * + * R3/R4 has 64 bit value + * R5 has shift count + * result in R3/R4 + * + * ashrdi3: arithmetic right shift (sign propagation) + * lshrdi3: logical right shift + * ashldi3: left shift + */ + .globl __ashldi3 +__ashldi3: + subfic r6,r5,32 + slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count + addi r7,r5,32 # could be xori, or addi with -32 + srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) + slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) + or r3,r3,r6 # MSW |= t1 + slw r4,r4,r5 # LSW = LSW << count + or r3,r3,r7 # MSW |= t2 + blr diff --git a/arch/powerpc/lib/_ashrdi3.S b/arch/powerpc/lib/_ashrdi3.S new file mode 100644 index 0000000..f28ab49 --- /dev/null +++ b/arch/powerpc/lib/_ashrdi3.S @@ -0,0 +1,47 @@ +/* + * This code was copied from arch/powerpc/kernel/misc_32.S in the Linux + * kernel sources (commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, also + * known as 2.6.38-rc5). The source file copyrights are as follows: + * + * (C) Copyright 1995-1996 Gary Thomas (gdt(a)linuxppc.org) + * + * Largely rewritten by Cort Dougan (cort(a)cs.nmt.edu) + * and Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <config.h> + +/* + * Extended precision shifts. + * + * Updated to be valid for shift counts from 0 to 63 inclusive. + * -- Gabriel + * + * R3/R4 has 64 bit value + * R5 has shift count + * result in R3/R4 + * + * ashrdi3: arithmetic right shift (sign propagation) + * lshrdi3: logical right shift + * ashldi3: left shift + */ + .globl __ashrdi3 +__ashrdi3: + subfic r6,r5,32 + srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count + addi r7,r5,32 # could be xori, or addi with -32 + slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) + rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 + sraw r7,r3,r7 # t2 = MSW >> (count-32) + or r4,r4,r6 # LSW |= t1 + slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 + sraw r3,r3,r5 # MSW = MSW >> count + or r4,r4,r7 # LSW |= t2 + blr diff --git a/arch/powerpc/lib/_lshrdi3.S b/arch/powerpc/lib/_lshrdi3.S new file mode 100644 index 0000000..c1bbe7b --- /dev/null +++ b/arch/powerpc/lib/_lshrdi3.S @@ -0,0 +1,45 @@ +/* + * This code was copied from arch/powerpc/kernel/misc_32.S in the Linux + * kernel sources (commit 85e2efbb1db9a18d218006706d6e4fbeb0216213, also + * known as 2.6.38-rc5). The source file copyrights are as follows: + * + * (C) Copyright 1995-1996 Gary Thomas (gdt(a)linuxppc.org) + * + * Largely rewritten by Cort Dougan (cort(a)cs.nmt.edu) + * and Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <config.h> + +/* + * Extended precision shifts. + * + * Updated to be valid for shift counts from 0 to 63 inclusive. + * -- Gabriel + * + * R3/R4 has 64 bit value + * R5 has shift count + * result in R3/R4 + * + * ashrdi3: arithmetic right shift (sign propagation) + * lshrdi3: logical right shift + * ashldi3: left shift + */ + .globl __lshrdi3 +__lshrdi3: + subfic r6,r5,32 + srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count + addi r7,r5,32 # could be xori, or addi with -32 + slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) + srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) + or r4,r4,r6 # LSW |= t1 + srw r3,r3,r5 # MSW = MSW >> count + or r4,r4,r7 # LSW |= t2 + blr -- 1.7.2.3

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[U-Boot] [PATCH v2 1/2] fttmr010: move fttmr010 header to include/faraday
by Macpaul Lin 14 Apr '11

14 Apr '11

Move the header file and definitions of fttmr010 power control unit from a320 SoC folder to "include/faraday" folder. This change will let other SoC which also use fttmr010 could share the same header file. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Changes for v2: - Fix patch according to the dependent patches of a320evb in u-boot-arm.git "next" branch. - V1 patches of fttmr010 as "/patch/71952/" marked as "superseded" in patchworks. - Move files into "include/faraday" instead of "drivers/timer". arch/arm/include/asm/arch-a320/fttmr010.h | 73 ----------------------------- include/faraday/fttmr010.h | 73 +++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+), 73 deletions(-) delete mode 100644 arch/arm/include/asm/arch-a320/fttmr010.h create mode 100644 include/faraday/fttmr010.h diff --git a/arch/arm/include/asm/arch-a320/fttmr010.h b/arch/arm/include/asm/arch-a320/fttmr010.h deleted file mode 100644 index 72abcb3..0000000 --- a/arch/arm/include/asm/arch-a320/fttmr010.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert(a)faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Timer - */ -#ifndef __FTTMR010_H -#define __FTTMR010_H - -struct fttmr010 { - unsigned int timer1_counter; /* 0x00 */ - unsigned int timer1_load; /* 0x04 */ - unsigned int timer1_match1; /* 0x08 */ - unsigned int timer1_match2; /* 0x0c */ - unsigned int timer2_counter; /* 0x10 */ - unsigned int timer2_load; /* 0x14 */ - unsigned int timer2_match1; /* 0x18 */ - unsigned int timer2_match2; /* 0x1c */ - unsigned int timer3_counter; /* 0x20 */ - unsigned int timer3_load; /* 0x24 */ - unsigned int timer3_match1; /* 0x28 */ - unsigned int timer3_match2; /* 0x2c */ - unsigned int cr; /* 0x30 */ - unsigned int interrupt_state; /* 0x34 */ - unsigned int interrupt_mask; /* 0x38 */ -}; - -/* - * Timer Control Register - */ -#define FTTMR010_TM3_UPDOWN (1 << 11) -#define FTTMR010_TM2_UPDOWN (1 << 10) -#define FTTMR010_TM1_UPDOWN (1 << 9) -#define FTTMR010_TM3_OFENABLE (1 << 8) -#define FTTMR010_TM3_CLOCK (1 << 7) -#define FTTMR010_TM3_ENABLE (1 << 6) -#define FTTMR010_TM2_OFENABLE (1 << 5) -#define FTTMR010_TM2_CLOCK (1 << 4) -#define FTTMR010_TM2_ENABLE (1 << 3) -#define FTTMR010_TM1_OFENABLE (1 << 2) -#define FTTMR010_TM1_CLOCK (1 << 1) -#define FTTMR010_TM1_ENABLE (1 << 0) - -/* - * Timer Interrupt State & Mask Registers - */ -#define FTTMR010_TM3_OVERFLOW (1 << 8) -#define FTTMR010_TM3_MATCH2 (1 << 7) -#define FTTMR010_TM3_MATCH1 (1 << 6) -#define FTTMR010_TM2_OVERFLOW (1 << 5) -#define FTTMR010_TM2_MATCH2 (1 << 4) -#define FTTMR010_TM2_MATCH1 (1 << 3) -#define FTTMR010_TM1_OVERFLOW (1 << 2) -#define FTTMR010_TM1_MATCH2 (1 << 1) -#define FTTMR010_TM1_MATCH1 (1 << 0) - -#endif /* __FTTMR010_H */ diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h new file mode 100644 index 0000000..72abcb3 --- /dev/null +++ b/include/faraday/fttmr010.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Timer + */ +#ifndef __FTTMR010_H +#define __FTTMR010_H + +struct fttmr010 { + unsigned int timer1_counter; /* 0x00 */ + unsigned int timer1_load; /* 0x04 */ + unsigned int timer1_match1; /* 0x08 */ + unsigned int timer1_match2; /* 0x0c */ + unsigned int timer2_counter; /* 0x10 */ + unsigned int timer2_load; /* 0x14 */ + unsigned int timer2_match1; /* 0x18 */ + unsigned int timer2_match2; /* 0x1c */ + unsigned int timer3_counter; /* 0x20 */ + unsigned int timer3_load; /* 0x24 */ + unsigned int timer3_match1; /* 0x28 */ + unsigned int timer3_match2; /* 0x2c */ + unsigned int cr; /* 0x30 */ + unsigned int interrupt_state; /* 0x34 */ + unsigned int interrupt_mask; /* 0x38 */ +}; + +/* + * Timer Control Register + */ +#define FTTMR010_TM3_UPDOWN (1 << 11) +#define FTTMR010_TM2_UPDOWN (1 << 10) +#define FTTMR010_TM1_UPDOWN (1 << 9) +#define FTTMR010_TM3_OFENABLE (1 << 8) +#define FTTMR010_TM3_CLOCK (1 << 7) +#define FTTMR010_TM3_ENABLE (1 << 6) +#define FTTMR010_TM2_OFENABLE (1 << 5) +#define FTTMR010_TM2_CLOCK (1 << 4) +#define FTTMR010_TM2_ENABLE (1 << 3) +#define FTTMR010_TM1_OFENABLE (1 << 2) +#define FTTMR010_TM1_CLOCK (1 << 1) +#define FTTMR010_TM1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define FTTMR010_TM3_OVERFLOW (1 << 8) +#define FTTMR010_TM3_MATCH2 (1 << 7) +#define FTTMR010_TM3_MATCH1 (1 << 6) +#define FTTMR010_TM2_OVERFLOW (1 << 5) +#define FTTMR010_TM2_MATCH2 (1 << 4) +#define FTTMR010_TM2_MATCH1 (1 << 3) +#define FTTMR010_TM1_OVERFLOW (1 << 2) +#define FTTMR010_TM1_MATCH2 (1 << 1) +#define FTTMR010_TM1_MATCH1 (1 << 0) + +#endif /* __FTTMR010_H */ -- 1.7.3.5 CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

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[U-Boot] [PATCH v2 1/2] ftpmu010: fix relocation and enhance features
by Macpaul Lin 14 Apr '11

14 Apr '11

1. ftpmu010.h: fix and add definitions Enhanced for more features and asm related support according to datasheet. Note: - FTPMU010_PDLLCR0_HCLKOUTDIS is "incorrect" in datasheet. - FTPMU010_PDLLCR0_DLLFRANG is only 1 bit at bit #19. (not 20-19) - FTPMU010_PDLLCR0_HCLKOUTDIS is 4 bits at bit #20. (not 24-21) 2. ftpmu010.c: enhance features and fix relocation - The following functions is added for pmu features. ftpmu010_mfpsr_select_dev() ftpmu010_sdramhtc_set() - This patch also fix the declare statement for relocation. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Changes for v2: - Fix patch according to the dependent patches of ftpmu010 in u-boot-arm.git "next" branch. - V1 patches of ftpmu010 as "/patch/77704/" marked as "superseded" in patchworks. drivers/power/ftpmu010.c | 39 +++++++++++++++++++++++++++++++++++++-- include/faraday/ftpmu010.h | 38 +++++++++++++++++++++++++++++++++++--- 2 files changed, 72 insertions(+), 5 deletions(-) diff --git a/drivers/power/ftpmu010.c b/drivers/power/ftpmu010.c index c6a8cda..df99dfa 100644 --- a/drivers/power/ftpmu010.c +++ b/drivers/power/ftpmu010.c @@ -25,10 +25,10 @@ #include <asm/io.h> #include <faraday/ftpmu010.h> -static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - +/* OSCC: OSC Control Register */ void ftpmu010_32768osc_enable(void) { + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; unsigned int oscc; /* enable the 32768Hz oscillator */ @@ -46,8 +46,31 @@ void ftpmu010_32768osc_enable(void) writel(oscc, &pmu->OSCC); } +/* MFPSR: Multi-Function Port Setting Register */ +void ftpmu010_mfpsr_select_dev(unsigned int dev) +{ + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + unsigned int mfpsr; + + mfpsr = readl(&pmu->MFPSR); + mfpsr |= dev; + writel(mfpsr, &pmu->MFPSR); +} + +void ftpmu010_mfpsr_diselect_dev(unsigned int dev) +{ + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + unsigned int mfpsr; + + mfpsr = readl(&pmu->MFPSR); + mfpsr &= ~dev; + writel(mfpsr, &pmu->MFPSR); +} + +/* PDLLCR0: PLL/DLL Control Register 0 */ void ftpmu010_dlldis_disable(void) { + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; unsigned int pdllcr0; pdllcr0 = readl(&pmu->PDLLCR0); @@ -57,9 +80,21 @@ void ftpmu010_dlldis_disable(void) void ftpmu010_sdram_clk_disable(unsigned int cr0) { + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; unsigned int pdllcr0; pdllcr0 = readl(&pmu->PDLLCR0); pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0); writel(pdllcr0, &pmu->PDLLCR0); } + +/* SDRAMHTC: SDRAM Signal Hold Time Control */ +void ftpmu010_sdramhtc_set(unsigned int val) +{ + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + unsigned int sdramhtc; + + sdramhtc = readl(&pmu->SDRAMHTC); + sdramhtc |= val; + writel(sdramhtc, &pmu->SDRAMHTC); +} diff --git a/include/faraday/ftpmu010.h b/include/faraday/ftpmu010.h index 640f056..bd40c53 100644 --- a/include/faraday/ftpmu010.h +++ b/include/faraday/ftpmu010.h @@ -126,23 +126,55 @@ struct ftpmu010 { /* * Multi-Function Port Setting Register */ +#define FTPMU010_MFPSR_DEBUGSEL (1 << 17) +#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) +#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) #define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) #define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) +#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) +#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) +#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) +#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) +#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) +#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) #define FTPMU010_MFPSR_AC97PINSEL (1 << 3) +#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) +#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) /* * PLL/DLL Control Register 0 + * Note: + * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: + * Datasheet indicated it starts at bit #21 which was wrong. + * 2. FTPMU010_PDLLCR0_DLLFRAG: + * Datasheet indicated it has 2 bit which was wrong. */ -#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf) -#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19) +#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) +#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) #define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) #define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) #define FTPMU010_PDLLCR0_DLLDIS (1 << 16) -#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff) +#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) +#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) #define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) #define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) #define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) +/* + * SDRAM Signal Hold Time Control Register + */ +#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) +#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) +#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) +#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) +#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) +#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) +#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) +#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) +#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) +#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) + void ftpmu010_32768osc_enable(void); void ftpmu010_dlldis_disable(void); void ftpmu010_sdram_clk_disable(unsigned int cr0); -- 1.7.3.5 CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

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[U-Boot] [PATCH] Env. vars fix for lite5200
by Karim Yaghmour 13 Apr '11

13 Apr '11

I still have a few older lite5200 boards around and when I recently tried to upgrade U-Boot I ran into weird problems where "saveenv" would fry the bootloader. Attached is a fix. It seems that somewhere along the way the image size grew larger than 256K and the address for the env vars overlapped with the code. P.S.: Apologies for not putting the patch inline, the email provider I use has a brain-dead policy of enforcing line-wraps on text emails :/ -- Karim Yaghmour CEO - Opersys inc. / www.opersys.com http://twitter.com/karimyaghmour

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[U-Boot] [PATCH] MAINTAINERS: fix email address case
by Fabio Estevam 13 Apr '11

13 Apr '11

Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- MAINTAINERS | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 07541bd..7e987b3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -624,7 +624,7 @@ Kristoffer Ericson <kristoffer.ericson(a)gmail.com> jornada SA1110 -Fabio Estevam <Fabio.Estevam(a)freescale.com> +Fabio Estevam <fabio.estevam(a)freescale.com> mx31pdk i.MX31 -- 1.6.0.4

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[U-Boot] [PATCH 1/1] MX53: drop config.mk from mx53evk
by Jason Liu 13 Apr '11

13 Apr '11

The config.mk file in board directory is now obsolete and should be removed. Add option for the IMX image into boards.cfg Signed-off-by: Jason Liu <r64343(a)freescale.com> --- board/freescale/mx53evk/config.mk | 24 ------------------------ boards.cfg | 2 +- 2 files changed, 1 insertions(+), 25 deletions(-) diff --git a/board/freescale/mx53evk/config.mk b/board/freescale/mx53evk/config.mk deleted file mode 100644 index 0e60454..0000000 --- a/board/freescale/mx53evk/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg -ALL += $(obj)u-boot.imx diff --git a/boards.cfg b/boards.cfg index abb66d9..b85ad35 100644 --- a/boards.cfg +++ b/boards.cfg @@ -108,7 +108,7 @@ edminiv2 arm arm926ejs - LaCie ca9x4_ct_vxp arm armv7 vexpress armltd efikamx arm armv7 efikamx - mx5 mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg -mx53evk arm armv7 mx53evk freescale mx5 +mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg vision2 arm armv7 vision2 ttcontrol mx5 cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 -- 1.7.0.4

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[U-Boot] [PATCH] Fix bad padding of bootp request packet
by Simon Glass 13 Apr '11

13 Apr '11

This seems to pad to one byte longer than required Change-Id: I86a888a9f5f27356e260c0457d92468d5923a756 Signed-off-by: Simon Glass <sjg(a)chromium.org> --- net/bootp.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/net/bootp.c b/net/bootp.c index 1a71786..87b027e 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -464,7 +464,7 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R /* Pad to minimal length */ #ifdef CONFIG_DHCP_MIN_EXT_LEN - while ((e - start) <= CONFIG_DHCP_MIN_EXT_LEN) + while ((e - start) < CONFIG_DHCP_MIN_EXT_LEN) *e++ = 0; #endif -- 1.7.3.1

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[U-Boot] e1000: Driver additions for eXMeritus HWW-1U-1A
by Kyle Moffett 13 Apr '11

13 Apr '11

Sorry for taking so long to update and re-post these; I've had a lot of other things on my plate for the last several months. I've re-based them against the latest U-Boot master branch as of today. The following 5 patches are a series to provide the necessary support for the onboard Intel 82571 E1000E chips on our eXMeritus HWW-1U-1A boards. There are a few incidental fixups for dual-port NICs, but the main body of these patches is an SPI driver and "e1000 eeprom" commands for programming the configuration EEPROM attached to the 82571 chips. Our manufacturing process directly attaches the unprogrammed EEPROMs to the boards. We then use this code to load the Intel EEPROM and update the MAC address. The overall diffstat is: drivers/net/e1000.c | 848 ++++++++++++++++++++++++++++++++++++++++++++------- drivers/net/e1000.h | 18 +- 2 files changed, 751 insertions(+), 115 deletions(-) Most of the new code is hidden behind a couple of config options, so it won't affect other users of e1000 chips unless they explicitly request it. Cheers, Kyle Moffett

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[U-Boot] [PATCH] mvgbe: enable the reception of packets with an odd number of preamble nibbles
by Klaus Flittner 13 Apr '11

13 Apr '11

With the current hardware initialisation of the driver all packets with an odd number of preamble nibbles are dropped. Some switches seem to send all packets with such an preamble. According to the functional specifications of the marvell 88F6180, 6190, 6192 and 6281 the reception of such packets can be enabled by setting bit 22 in register PSC1. Signed-off-by: Klaus Flittner <klaus(a)flittner.org> --- drivers/net/mvgbe.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index c701f43..f1081a2 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -446,6 +446,9 @@ static int mvgbe_init(struct eth_device *dev) MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); + /* Receive packets with odd number of preamble nibbles */ + MVGBE_REG_BITS_SET(regs->psc1, 1 << 22); + /* Enable port initially */ MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);

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[U-Boot] [PATCH]: add canyonlands RAM-boot target
by Fawaz 13 Apr '11

13 Apr '11

This Patch adds another build target for the AMCC Canyonlands [PPC460Ex] eval board, this target can be used to do NAND flash or NOR flash programming in a virgin board using u-boot commands. Using JTAG debugger(e.g. BDI2000/3000) configured to setup the SDRAM. here are TLB entries required to load RAM-u-boot (for BDI2000/3000): WTLB 0x00000095 0x0000003F ;SDRAM 256MB @ 0x00000000 WTLB 0xE1000005 0x4E10001B do SDRAM configuration. Then do the following usin JTAG emulator: 460EX>load 0x01000000 u-boot.bin bin 460EX>go Back to serial session that connected to canyonlands's serial port. Signed-off-by: Fawaz Gaili <fwazgai(a)gmail.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Felix Radensky <felix(a)embedded-sol.com> --- arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 11 ++- arch/powerpc/cpu/ppc4xx/Makefile | 2 + board/amcc/canyonlands/canyonlands.c | 3 +- board/amcc/canyonlands/init.S | 6 ++ board/amcc/canyonlands/u-boot-ram.lds | 96 ++++++++++++++++++++ boards.cfg | 1 + include/configs/canyonlands.h | 31 +++++-- 7 files changed, 137 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 95df1d9..2660cd2 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -66,7 +66,8 @@ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ } while (0) -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#if (!defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_SYS_RAMBOOT)) \ + || defined(CONFIG_NAND_SPL) static void update_rdcc(void) { u32 val; @@ -2896,7 +2897,8 @@ phys_size_t initdram(int board_type) * mustn't be reconfigured again since we're already running * from SDRAM. */ -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#if (!defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_SYS_RAMBOOT)) \ + || defined(CONFIG_NAND_SPL) unsigned long val; #if defined(CONFIG_440) @@ -3013,12 +3015,13 @@ phys_size_t initdram(int board_type) #endif #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_SYS_RAMBOOT) \ + && !defined(CONFIG_NAND_SPL) /*------------------------------------------------------------------ | DQS calibration. +-----------------------------------------------------------------*/ DQS_autocalibration(); -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ +#endif /* !defined(CONFIG_NAND_U_BOOT && CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_SPL) */ #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ /* diff --git a/arch/powerpc/cpu/ppc4xx/Makefile b/arch/powerpc/cpu/ppc4xx/Makefile index d97ca20..02a48f9 100644 --- a/arch/powerpc/cpu/ppc4xx/Makefile +++ b/arch/powerpc/cpu/ppc4xx/Makefile @@ -36,9 +36,11 @@ COBJS := 40x_spd_sdram.o ifndef CONFIG_NAND_SPL ifndef CONFIG_NAND_U_BOOT +ifndef CONFIG_SYS_RAMBOOT COBJS += 44x_spd_ddr.o endif endif +endif COBJS-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o COBJS-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o COBJS += 4xx_pci.o diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 80e2739..d1f5e4f 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -390,8 +390,8 @@ int board_early_init_r (void) */ /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) \ + || defined(CONFIG_SYS_RAMBOOT) mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); #else mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); #endif diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index 8b7bfce..526d8bd 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -66,6 +66,13 @@ tlbtab: tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) #endif +#ifdef CONFIG_SYS_RAMBOOT +#if CONFIG_SYS_MBYTES_SDRAM >= 512 + tlbentry(0x10000000, SZ_256M, 0x10000000, 0x0, AC_R|AC_W|SA_G|SA_I|AC_X) + /*additional entry required*/ +#endif +#endif + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG) tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) diff --git a/board/amcc/canyonlands/u-boot-ram.lds b/board/amcc/canyonlands/u-boot-ram.lds new file mode 100644 index 0000000..e98d947 --- /dev/null +++ b/board/amcc/canyonlands/u-boot-ram.lds @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2011 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * Fawaz Giali, Nile Center for Technology Research, fwazgai(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .text : + { + arch/powerpc/cpu/ppc4xx/start.o (.text*) + board/amcc/canyonlands/init.o (.text*) + + *(.text*) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + KEEP(*(.got)) + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/boards.cfg b/boards.cfg index c3b164e..1f7f4dd 100644 --- a/boards.cfg +++ b/boards.cfg @@ -647,6 +647,7 @@ bluestone powerpc ppc4xx - amcc bubinga powerpc ppc4xx - amcc canyonlands powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS canyonlands_nand powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 +canyonlands_ramboot powerpc ppc4xx canyonlands amcc - canyonlands:CANYONLANDS,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds ebony powerpc ppc4xx - amcc glacier powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER glacier_nand powerpc ppc4xx canyonlands amcc - canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 8c03582..c7c817f 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -137,17 +137,31 @@ * Environment *----------------------------------------------------------------------*/ /* - * Define here the location of the environment variables (FLASH). + * Define here the location of the environment variables (FLASH). + */ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */ +#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ +#elif defined(CONFIG_SYS_RAMBOOT) +#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only*/ +#define CONFIG_ENV_SIZE (8 << 10) +/* + * In RAM-booting version, we have no environment storage. So we need to + * provide at least preliminary MAC addresses for the 4xx EMAC driver to + * register the interfaces. */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_ETHADDR 4a:56:49:22:3e:43 +#define CONFIG_ETH1ADDR 02:93:53:d5:06:98 +#else #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ -#else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#endif/*CONFIG_NAND_U_BOOT || CONFIG_NAND_SPL*/ + +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) \ + || defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */ #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ #endif /* @@ -251,7 +265,7 @@ /*------------------------------------------------------------------------------ * DDR SDRAM *----------------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_SYS_RAMBOOT) #if !defined(CONFIG_ARCHES) /* * NAND booting U-Boot version uses a fixed initialization, since the whole @@ -324,7 +338,7 @@ #define CONFIG_SYS_SDRAM0_MMODE 0x00000432 #define CONFIG_SYS_SDRAM0_MEMODE 0x00000004 #endif /* !defined(CONFIG_ARCHES) */ -#endif /* !defined(CONFIG_NAND_U_BOOT) */ +#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_SYS_RAMBOOT) */ #define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */ @@ -571,7 +585,8 @@ * 0xfe00.0000 -> 4.ce00.0000 */ -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) \ + || defined(CONFIG_SYS_RAMBOOT) /* Memory Bank 3 (NOR-FLASH) initialization */ #define CONFIG_SYS_EBC_PB3AP 0x10055e00 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000) -- Best Regards Fawaz Gaili NCTR NTC - Tower 8th floor

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