February 2011 - U-Boot

[U-Boot] [PATCH] ppc, mgcoge: add DIP switch detection
by Holger Brunck 06 May '11

06 May '11

From: Andreas Huber <andreas.huber(a)keymile.com> This reads the DIP switch on mgcoge. The DIP switch is connected to the BFTICU (0x40000089) FPGA. If the DIP switch is set the environment variable 'actual_bank' is set to 0 and starts the SW in bank0. Signed-off-by: Andreas Huber <andreas.huber(a)keymile.com> Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> --- board/keymile/mgcoge/mgcoge.c | 18 ++++++++++++++++++ include/configs/mgcoge.h | 5 +++++ 2 files changed, 23 insertions(+), 0 deletions(-) diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index 5c9496c..5dcdf37 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -293,6 +293,24 @@ int checkboard(void) return 0; } +#define DIPSWITCH_OFFSET 0x89 +#define DIPSWITCH_MASK 0x0f + +int last_stage_init(void) +{ + u8 dip_switch; + /* Dip switch */ + dip_switch = readb(CONFIG_SYS_BFTICU_BASE + DIPSWITCH_OFFSET); + dip_switch &= DIPSWITCH_MASK; + /* dip switch 'full reset' or 'db erase' */ + if (dip_switch & 0x1 || dip_switch & 0x2) { + /* start bootloader */ + puts("DIP: Enabled\n"); + setenv("actual_bank", "0"); + } + return 0; +} + /* * Early board initalization. */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 6dec0ee..f1bd32a 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -348,4 +348,9 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" +/* enable last_stage_init */ +#define CONFIG_LAST_STAGE_INIT 1 +/* bfticu address */ +#define CONFIG_SYS_BFTICU_BASE 0x40000000 + #endif /* __CONFIG_H */ -- 1.7.0.5

2 9

[U-Boot] [PATCH] update VCMA9 port
by David Müller 02 May '11

02 May '11

This patch brings the VCMA9 port in sync with the latest U-Boot version by doing the following: - do the necessary adjustments to support the ARM relocation feature - use the CFI flash driver (and removing the old one) - various cleanups and coding style fixes Signed-off-by: David Mueller <d.mueller(a)elsoft.ch> diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 27cef1d..59c25f9 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).o -COBJS := vcma9.o flash.o cmd_vcma9.o +COBJS := vcma9.o cmd_vcma9.o COBJS += ../common/common_util.o SOBJS := lowlevel_init.o diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 0d5f46e..0f02b7e 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -43,7 +43,7 @@ static uchar cs8900_chksum(ushort data) DECLARE_GLOBAL_DATA_PTR; -extern void print_vcma9_info(void); +extern void vcma9_print_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); extern int vcma9_nanderase(void); @@ -60,7 +60,7 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char cs8900_name[10]; if (strcmp(argv[1], "info") == 0) { - print_vcma9_info(); + vcma9_print_info(); return 0; } #if defined(CONFIG_CS8900) diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk index e345913..fef5308 100644 --- a/board/mpl/vcma9/config.mk +++ b/board/mpl/vcma9/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2002, 2003 +# (C) Copyright 2002, 2003, 2010 # David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> # # MPL VCMA9 board with S3C2410X (ARM920T) cpu @@ -7,18 +7,10 @@ # see http://www.mpl.ch/ for more information about the MPL VCMA9 # -# -# MPL VCMA9 has 1 bank of minimal 16 MB DRAM -# from 0x30000000 -# # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 # optionally with a ramdisk at 3040'0000 # -# we load ourself to 33F8'0000 +# NOR flash is mapped at address 0 # -# download area is 3080'0000 -# - -#CONFIG_SYS_TEXT_BASE = 0x30F80000 -CONFIG_SYS_TEXT_BASE = 0x33F80000 +CONFIG_SYS_TEXT_BASE = 0x0 diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c deleted file mode 100644 index 7abf9cf..0000000 --- a/board/mpl/vcma9/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu(a)sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -ulong myflush (void); - - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - puts ("AMD: "); - break; - default: - puts ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - puts ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - puts ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - puts ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - puts ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - puts ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - puts ("ok.\n"); - } else { /* it was protected */ - - puts ("protected!\n"); - } - } - - if (ctrlc ()) - puts ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index 062e868..cb1518b 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -4,9 +4,9 @@ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw(a)its.tudelft.nl) and * Jan-Derk Bakker (J.D.Bakker(a)its.tudelft.nl) * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * (C) Copyright 2002, 2003, 2004, 2005 * * See file CREDITS for list of people who contributed to this * project. @@ -32,12 +32,21 @@ #include <version.h> -/* some parameters for the board */ +/* register definitions */ +#define PLD_BASE 0x28000000 +#define MISC_REG 0x103 +#define SDRAM_REG 0x106 #define BWSCON 0x48000000 -#define PLD_BASE 0x2C000000 -#define SDRAM_REG 0x2C000106 +#define CLKBASE 0x4C000000 +#define LOCKTIME 0x0 +#define MPLLCON 0x4 +#define UPLLCON 0x8 +#define GPIOBASE 0x56000000 +#define GSTATUS1 0xB0 +#define FASTCPU 0x02 +/* some parameters for the board */ /* BWSCON */ #define DW8 (0x0) #define DW16 (0x1) @@ -48,83 +57,160 @@ /* BANKSIZE */ #define BURST_EN (0x1<<7) -#define B1_BWSCON (DW16) -#define B2_BWSCON (DW32) -#define B3_BWSCON (DW32) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW8 + UBLB) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x1 /* 1clk */ -/*#define B0_Tcos 0x0 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -/*#define B0_Tacc 0x5 8clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* page mode is not used */ -#define B0_PMC 0x0 /* page mode disabled */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x1 /* 1clk */ -/*#define B1_Tcos 0x0 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -/*#define B1_Tacc 0x5 8clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 /* page mode is not used */ -#define B1_PMC 0x0 /* page mode disabled */ +/* BANK0CON 200 */ +#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B0_Tcoh_200 0x0 /* 0clk */ +#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */ +#define B0_Tacp_200 0x0 /* page mode is not used */ +#define B0_PMC_200 0x0 /* page mode disabled */ + +/* BANK0CON 250 */ +#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B0_Tcoh_250 0x0 /* 0clk */ +#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_250 0x0 /* page mode is not used */ +#define B0_PMC_250 0x0 /* page mode disabled */ + +/* BANK0CON 266 */ +#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B0_Tcoh_266 0x0 /* 0clk */ +#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_266 0x0 /* page mode is not used */ +#define B0_PMC_266 0x0 /* page mode disabled */ + +/* BANK1CON 200 */ +#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B1_Tcoh_200 0x0 /* 0clk */ +#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_200 0x0 /* page mode is not used */ +#define B1_PMC_200 0x0 /* page mode disabled */ + +/* BANK1CON 250 */ +#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B1_Tcoh_250 0x0 /* 0clk */ +#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_250 0x0 /* page mode is not used */ +#define B1_PMC_250 0x0 /* page mode disabled */ + +/* BANK1CON 266 */ +#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B1_Tcoh_266 0x0 /* 0clk */ +#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_266 0x0 /* page mode is not used */ +#define B1_PMC_266 0x0 /* page mode disabled */ +/* BANK2CON 200 + 250 + 266 */ #define B2_Tacs 0x3 /* 4clk */ #define B2_Tcos 0x3 /* 4clk */ #define B2_Tacc 0x7 /* 14clk */ #define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tah 0x3 /* 4clk */ +#define B2_Tcah 0x3 /* 4clk */ #define B2_Tacp 0x0 /* page mode is not used */ #define B2_PMC 0x0 /* page mode disabled */ +/* BANK3CON 200 + 250 + 266 */ #define B3_Tacs 0x3 /* 4clk */ #define B3_Tcos 0x3 /* 4clk */ #define B3_Tacc 0x7 /* 14clk */ #define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tah 0x3 /* 4clk */ +#define B3_Tcah 0x3 /* 4clk */ #define B3_Tacp 0x0 /* page mode is not used */ #define B3_PMC 0x0 /* page mode disabled */ -#define B4_Tacs 0x3 /* 4clk */ -#define B4_Tcos 0x1 /* 1clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x1 /* 1clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 /* page mode is not used */ -#define B4_PMC 0x0 /* page mode disabled */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x3 /* 4clk */ -#define B5_Tacc 0x5 /* 8clk */ -#define B5_Tcoh 0x2 /* 2clk */ -#define B5_Tah 0x1 /* 1clk */ -#define B5_Tacp 0x0 /* page mode is not used */ -#define B5_PMC 0x0 /* page mode disabled */ +/* BANK4CON 200 */ +#define B4_Tacs_200 0x1 /* 1clk */ +#define B4_Tcos_200 0x3 /* 4clk */ +#define B4_Tacc_200 0x7 /* 14clk */ +#define B4_Tcoh_200 0x3 /* 4clk */ +#define B4_Tcah_200 0x2 /* 2clk */ +#define B4_Tacp_200 0x0 /* page mode is not used */ +#define B4_PMC_200 0x0 /* page mode disabled */ + +/* BANK4CON 250 */ +#define B4_Tacs_250 0x1 /* 1clk */ +#define B4_Tcos_250 0x3 /* 4clk */ +#define B4_Tacc_250 0x7 /* 14clk */ +#define B4_Tcoh_250 0x3 /* 4clk */ +#define B4_Tcah_250 0x2 /* 2clk */ +#define B4_Tacp_250 0x0 /* page mode is not used */ +#define B4_PMC_250 0x0 /* page mode disabled */ + +/* BANK4CON 266 */ +#define B4_Tacs_266 0x1 /* 1clk */ +#define B4_Tcos_266 0x3 /* 4clk */ +#define B4_Tacc_266 0x7 /* 14clk */ +#define B4_Tcoh_266 0x3 /* 4clk */ +#define B4_Tcah_266 0x2 /* 2clk */ +#define B4_Tacp_266 0x0 /* page mode is not used */ +#define B4_PMC_266 0x0 /* page mode disabled */ + +/* BANK5CON 200 */ +#define B5_Tacs_200 0x0 /* 0clk */ +#define B5_Tcos_200 0x3 /* 4clk */ +#define B5_Tacc_200 0x4 /* 6clk */ +#define B5_Tcoh_200 0x3 /* 4clk */ +#define B5_Tcah_200 0x1 /* 1clk */ +#define B5_Tacp_200 0x0 /* page mode is not used */ +#define B5_PMC_200 0x0 /* page mode disabled */ + +/* BANK5CON 250 */ +#define B5_Tacs_250 0x0 /* 0clk */ +#define B5_Tcos_250 0x3 /* 4clk */ +#define B5_Tacc_250 0x5 /* 8clk */ +#define B5_Tcoh_250 0x3 /* 4clk */ +#define B5_Tcah_250 0x1 /* 1clk */ +#define B5_Tacp_250 0x0 /* page mode is not used */ +#define B5_PMC_250 0x0 /* page mode disabled */ + +/* BANK5CON 266 */ +#define B5_Tacs_266 0x0 /* 0clk */ +#define B5_Tcos_266 0x3 /* 4clk */ +#define B5_Tacc_266 0x5 /* 8clk */ +#define B5_Tcoh_266 0x3 /* 4clk */ +#define B5_Tcah_266 0x1 /* 1clk */ +#define B5_Tacp_266 0x0 /* page mode is not used */ +#define B5_PMC_266 0x0 /* page mode disabled */ #define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ +#define B6_Trcd_200 0x0 /* 2clk */ +#define B6_Trcd_250 0x1 /* 3clk */ +#define B6_Trcd_266 0x1 /* 3clk */ #define B6_SCAN 0x2 /* 10bit */ #define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ +#define B7_Trcd_200 0x0 /* 2clk */ +#define B7_Trcd_250 0x1 /* 3clk */ +#define B7_Trcd_266 0x1 /* 3clk */ #define B7_SCAN 0x2 /* 10bit */ /* REFRESH parameter */ #define REFEN 0x1 /* Refresh enable */ #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +#define Trp_200 0x0 /* 2clk */ +#define Trp_250 0x1 /* 3clk */ +#define Trp_266 0x1 /* 3clk */ +#define Tsrc_200 0x1 /* 5clk */ +#define Tsrc_250 0x2 /* 6clk */ +#define Tsrc_266 0x3 /* 7clk */ + +/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */ +#define REFCNT_200 489 +/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */ +#define REFCNT_250 99 +/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */ +#define REFCNT_266 0 /**************************************/ _TEXT_BASE: @@ -132,81 +218,304 @@ _TEXT_BASE: .globl lowlevel_init lowlevel_init: + /* use r0 to relocate DATA read/write to flash rather than memory ! */ + ldr r0, _TEXT_BASE + ldr r13, =BWSCON + + /* enable minimal access to PLD */ + ldr r1, [r13] /* load default BWSCON */ + orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */ + str r1, [r13] /* set BWSCON */ + ldr r1, =0x7FF0 /* select slowest timing */ + str r1, [r13, #0x18] /* set BANKCON5 */ + + ldr r1, =PLD_BASE + ldr r2, =SETUPDATA + ldrb r1, [r1, #MISC_REG] + sub r2, r2, r0 + tst r1, #FASTCPU /* FASTCPU available ? */ + addeq r2, r2, #SETUPENTRY_SIZE + /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =CSDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #CSDATA_END-CSDATA + /* r2 = pointer into timing table */ + /* r13 = pointer to MEM controller regs (starting with BWSCON) */ + add r3, r2, #CSDATA_OFFSET + add r4, r3, #CSDATAENTRY_SIZE 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b /* PLD access is now possible */ - /* r0 == SDRAMDATA */ - /* r1 == SDRAM controller regs */ - ldr r2, =PLD_BASE - ldrb r3, [r2, #SDRAM_REG-PLD_BASE] - mov r4, #SDRAMDATA1_END-SDRAMDATA + /* r3 = SDRAMDATA + /* r13 = pointer to MEM controller regs */ + ldr r1, =PLD_BASE + mov r4, #SDRAMENTRY_SIZE + ldrb r1, [r1, #SDRAM_REG] /* calculate start and end point */ - mla r0, r3, r4, r0 - add r2, r0, r4 + mla r3, r4, r1, r3 + add r4, r3, r4 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b + /* setup MPLL registers */ + ldr r1, =CLKBASE + ldr r4, =0xFFFFFF + add r3, r2, #4 /* r3 points to PLL values */ + str r4, [r1, #LOCKTIME] + ldmia r3, {r4,r5} + str r5, [r1, #UPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + + str r4, [r1, #MPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + /* everything is fine now */ mov pc, lr .ltorg /* the literal pools origin */ -CSDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) -CSDATA_END: - -SDRAMDATA: -/* 4Mx8x4 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 -SDRAMDATA1_END: - -/* 8Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 2Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 4Mx8x2 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 +#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \ + ((bws1) << 4) + \ + ((bws2) << 8) + \ + ((bws3) << 12) + \ + ((bws4) << 16) + \ + ((bws5) << 20) + \ + ((bws6) << 24) + \ + ((bws7) << 28) + +#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \ + ((tacs) << 13) + \ + ((tcos) << 11) + \ + ((tacc) << 8) + \ + ((tcoh) << 6) + \ + ((tcah) << 4) + \ + ((tacp) << 2) + \ + (pmc) + +#define MK_BANKCON_SDRAM(trcd, scan) \ + ((0x03) << 15) + \ + ((trcd) << 2) + \ + (scan) + +#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \ + ((enable) << 23) + \ + ((trefmd) << 22) + \ + ((trp) << 20) + \ + ((tsrc) << 18) + \ + (cnt) + +SETUPDATA: + .word 0x32410002 + /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */ + .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 250 MHz*/ +0: + .equiv CSDATA_OFFSET, (. - SETUPDATA) + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_250, \ + B0_Tcos_250, \ + B0_Tacc_250, \ + B0_Tcoh_250, \ + B0_Tcah_250, \ + B0_Tacp_250, \ + B0_PMC_250) + + .word MK_BANKCON(B1_Tacs_250, \ + B1_Tcos_250, \ + B1_Tacc_250, \ + B1_Tcoh_250, \ + B1_Tcah_250, \ + B1_Tacp_250, \ + B1_PMC_250) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_250, \ + B4_Tcos_250, \ + B4_Tacc_250, \ + B4_Tcoh_250, \ + B4_Tcah_250, \ + B4_Tacp_250, \ + B4_PMC_250) + + .word MK_BANKCON(B5_Tacs_250, \ + B5_Tcos_250, \ + B5_Tacc_250, \ + B5_Tcoh_250, \ + B5_Tcah_250, \ + B5_Tacp_250, \ + B5_PMC_250) + + .equiv CSDATAENTRY_SIZE, (. - 0b) + /* 4Mx8x4 */ +0: + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + .equiv SDRAMENTRY_SIZE, (. - 0b) + + /* 8Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPENTRY_SIZE, (. - SETUPDATA) + + .word 0x32410000 + /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */ + .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 200 MHz and default*/ + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_200, \ + B0_Tcos_200, \ + B0_Tacc_200, \ + B0_Tcoh_200, \ + B0_Tcah_200, \ + B0_Tacp_200, \ + B0_PMC_200) + + .word MK_BANKCON(B1_Tacs_200, \ + B1_Tcos_200, \ + B1_Tacc_200, \ + B1_Tcoh_200, \ + B1_Tcah_200, \ + B1_Tacp_200, \ + B1_PMC_200) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_200, \ + B4_Tcos_200, \ + B4_Tacc_200, \ + B4_Tcoh_200, \ + B4_Tcah_200, \ + B4_Tacp_200, \ + B4_PMC_200) + + .word MK_BANKCON(B5_Tacs_200, \ + B5_Tcos_200, \ + B5_Tacc_200, \ + B5_Tcoh_200, \ + B5_Tcah_200, \ + B5_Tacp_200, \ + B5_PMC_200) + + /* 4Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 8Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPDATA_SIZE, (. - SETUPDATA) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 978e6fd..b6b49f5 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -3,7 +3,7 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger(a)sysgo.de> * - * (C) Copyright 2002 + * (C) Copyright 2002, 2010 * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> * * See file CREDITS for list of people who contributed to this @@ -27,100 +27,53 @@ #include <common.h> #include <netdev.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> #include "vcma9.h" #include "../common/common_util.h" DECLARE_GLOBAL_DATA_PTR; -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - /* * Miscellaneous platform dependent initialisations */ -int board_init(void) +int board_early_init_f(void) { struct s3c24x0_clock_power * const clk_power = s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x002AAAAA; - gpio->gpbup = 0x000002BF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x000037F7; - gpio->gpfcon = 0x00000000; - gpio->gpfup = 0x00000000; - gpio->gpgcon = 0xFFEAFF5A; - gpio->gpgup = 0x0000F0DC; - gpio->gphcon = 0x0028AAAA; - gpio->gphup = 0x00000656; - - /* setup correct IRQ modes for NIC */ - /* rising edge mode */ - gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); - - /* select USB port 2 to be host or device (fix to host for now) */ - gpio->misccr |= 0x08; - - /* init serial */ - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; - serial_init(); + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); + + /* setup correct IRQ modes for NIC (rising edge mode) */ + writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); + + /* select USB port 2 to be host or device (setup as host for now) */ + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); + + return 0; +} +int board_init(void) +{ /* arch number of VCMA9-Board */ gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9; @@ -134,113 +87,32 @@ int board_init(void) } /* - * NAND flash initialization. - */ -#if defined(CONFIG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - - -static inline void NF_Init(void) -{ -#if 0 /* a little bit too optimistic */ -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void -nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -/* * Get some Board/PLD Info */ -static u8 Get_PLD_ID(void) +static u8 get_pld_reg(enum vcma9_pld_regs reg) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->ID); + return readb(VCMA9_PLD_BASE + reg); } -static u8 Get_PLD_BOARD(void) +static u8 get_pld_version(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->BOARD); + return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; } -static u8 Get_PLD_SDRAM(void) +static u8 get_pld_revision(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->SDRAM); + return get_pld_reg(VCMA9_PLD_ID) & 0x0F; } -static u8 Get_PLD_Version(void) +static uchar get_board_pcb(void) { - return((Get_PLD_ID() >> 4) & 0x0F); + return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; } -static u8 Get_PLD_Revision(void) +static u8 get_nr_chips(void) { - return(Get_PLD_ID() & 0x0F); -} - -#if 0 /* not used */ -static int Get_Board_Config(void) -{ - u8 config = Get_PLD_BOARD() & 0x03; - - if (config == 3) - return 1; - else - return 0; -} -#endif - -static uchar Get_Board_PCB(void) -{ - return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); -} - -static u8 Get_SDRAM_ChipNr(void) -{ - switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { + switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { case 0: return 4; case 1: return 1; case 2: return 2; @@ -248,9 +120,9 @@ static u8 Get_SDRAM_ChipNr(void) } } -static ulong Get_SDRAM_ChipSize(void) +static ulong get_chip_size(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return 16 * (1024*1024); case 1: return 32 * (1024*1024); case 2: return 8 * (1024*1024); @@ -258,9 +130,10 @@ static ulong Get_SDRAM_ChipSize(void) default: return 0; } } -static const char * Get_SDRAM_ChipGeom(void) + +static const char *get_chip_geom(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return "4Mx8x4"; case 1: return "8Mx8x4"; case 2: return "2Mx8x4"; @@ -269,23 +142,21 @@ static const char * Get_SDRAM_ChipGeom(void) } } -static void Show_VCMA9_Info(char *board_name, char *serial) +static void vcma9_show_info(char *board_name, char *serial) { printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); - printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); + board_name, serial, + get_board_pcb(), get_pld_version(), get_pld_revision()); + printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); } int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); - + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_chip_size() * get_nr_chips(); return 0; } -/* ------------------------------------------------------------------------- */ - /* * Check Board Identity: */ @@ -303,50 +174,35 @@ int checkboard(void) puts ("### No HW ID - assuming VCMA9"); } else { b->serial_name[5] = 0; - Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); + vcma9_show_info(b->serial_name, &b->serial_name[6]); } } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } - /*printf("\n");*/ - return(0); -} - -int last_stage_init(void) -{ - checkboard(); - stdio_print_current_devices(); - check_env(); return 0; } -/*************************************************************************** - * some helping routines - */ -#if !CONFIG_USB_KEYBOARD -int overwrite_console(void) +int board_late_init(void) { - /* return TRUE if console should be overwritten */ + /* + * check if environment is healthy, otherwise restore values + * from shadow copy + */ + check_env(); return 0; } -#endif -/************************************************************************ -* Print VCMA9 Info -************************************************************************/ -void print_vcma9_info(void) +void vcma9_print_info(void) { - char s[50]; - int i; + char *s = getenv("serial#"); - if ((i = getenv_f("serial#", s, 32)) < 0) { + if (!s) { puts ("### No HW ID - assuming VCMA9"); - printf("i %d", i*24); } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } } @@ -360,3 +216,15 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F400BB flash. + */ +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 94fd2fa..baaea85 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -29,106 +29,17 @@ extern int mem_test(unsigned long start, unsigned long ramsize,int mode); -void print_vcma9_info(void); - -#if defined(CONFIG_CMD_NAND) -typedef enum { - NFCE_LOW, - NFCE_HIGH -} NFCE_STATE; - -static inline void NF_Conf(u16 conf) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF = conf; -} - -static inline void NF_Cmd(u8 cmd) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCMD = cmd; -} - -static inline void NF_CmdW(u8 cmd) -{ - NF_Cmd(cmd); - udelay(1); -} - -static inline void NF_Addr(u8 addr) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFADDR = addr; -} - -static inline void NF_SetCE(NFCE_STATE s) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - switch (s) { - case NFCE_LOW: - nand->NFCONF &= ~(1<<11); - break; - - case NFCE_HIGH: - nand->NFCONF |= (1<<11); - break; - } -} - -static inline void NF_WaitRB(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - while (!(nand->NFSTAT & (1<<0))); -} - -static inline void NF_Write(u8 data) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFDATA = data; -} - -static inline u8 NF_Read(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFDATA); -} - -static inline void NF_Init_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF |= (1<<12); -} - -static inline u32 NF_Read_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFECC); -} - -#endif - -/* VCMA9 PLD regsiters */ -typedef struct { - u8 ID; - u8 NIC; - u8 CAN; - u8 MISC; - u8 GPCD; - u8 BOARD; - u8 SDRAM; -} /*__attribute__((__packed__))*/ VCMA9_PLD; - -#define VCMA9_PLD_BASE 0x2C000100 -static inline VCMA9_PLD *VCMA9_get_base_PLD(void) -{ - return (VCMA9_PLD * const)VCMA9_PLD_BASE; -} +void vcma9_print_info(void); + +/* VCMA9 PLD registers */ +enum vcma9_pld_regs { + VCMA9_PLD_ID, + VCMA9_PLD_NIC, + VCMA9_PLD_CAN, + VCMA9_PLD_MISC, + VCMA9_PLD_GPCD, + VCMA9_PLD_BOARD, + VCMA9_PLD_SDRAM +}; + +#define VCMA9_PLD_BASE (0x2C000100) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ebe9e42..a82012f 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,21 +33,21 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH -#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* input clock of PLL (VCMA9 has 12MHz input clock) */ +#define CONFIG_SYS_CLK_FREQ 12000000 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* * BOOTP options @@ -57,7 +57,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -68,146 +67,154 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FAT #define CONFIG_CMD_DATE #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_BSP +#define CONFIG_CMD_NAND +#define BOARD_LATE_INIT #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING + /*********************************************************** * I2C stuff: * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at * address 0x50 with 16bit addressing ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */ +/* we use the built-in I2C controller */ +#define CONFIG_DRIVER_S3C24X0_I2C + #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ -#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */ +/* use EEPROM for environment vars */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +/* environment starts at offset 0 */ +#define CONFIG_ENV_OFFSET 0x000 +/* 2KB should be more than enough */ +#define CONFIG_ENV_SIZE 0x800 #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ +/* 64 bytes page write mode on 24C256 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* - * Size of malloc() pool - */ -/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/ - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ - -/* * Hardware drivers */ #define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x20000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000300 +#define CONFIG_CS8900_BUS16 /* * select serial console configuration */ #define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ /************************************************************ - * USB support + * USB support (currently only works with D-cache off) ************************************************************/ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_USB_OHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION /* Enable needed helper functions */ -#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ +#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ /************************************************************ * RTC ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 +#define CONFIG_RTC_S3C24X0 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1 #if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 /* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "VCMA9 # " +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO /* Display board info */ -#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */ -/* we configure PWM Timer 4 to 1us ~ 1MHz */ -/*#define CONFIG_SYS_HZ 1000000 */ -#define CONFIG_SYS_HZ 1562500 +/* we configure PWM Timer 4 to 1ms 1000Hz */ +#define CONFIG_SYS_HZ 1000 /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/* support BZIP2 compression */ -#define CONFIG_BZIP2 1 +/* support additional compression methods */ +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA /************************************************************ * Ident ************************************************************/ /*#define VERSION_TAG "released"*/ #define VERSION_TAG "unstable" -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG +#define CONFIG_IDENT_STRING "\n(c) 2010 by MPL AG Switzerland, " \ + "MEV-10080-001 " VERSION_TAG /*----------------------------------------------------------------------- * Stack sizes * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ #endif /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 @@ -215,36 +222,60 @@ * FLASH and environment organization */ -#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif - +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT (19) -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +/* + * Size of malloc() pool + * BZIP2 / LZO / LZMA need a lot of RAM + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_S3C2410 +#define CONFIG_SYS_S3C2410_NAND_HWECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x4E000000 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING +#define CONFIG_S3C24XX_TACLS 1 +#define CONFIG_S3C24XX_TWRPH0 5 +#define CONFIG_S3C24XX_TWRPH1 3 #endif +#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 +/* + * File system + */ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_YAFFS2 +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_BOARD_EARLY_INIT_F #endif /* __CONFIG_H */

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[U-Boot] [PATCH] spi: add new driver for OpenCores tiny_spi
by Thomas Chou 30 Apr '11

30 Apr '11

This patch adds support for OpenCores tiny_spi. http://opencores.org/project,tiny_spi Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- drivers/spi/Makefile | 1 + drivers/spi/oc_tiny_spi.c | 241 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 242 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/oc_tiny_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index e34a124..8ad1d7f 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o +COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o diff --git a/drivers/spi/oc_tiny_spi.c b/drivers/spi/oc_tiny_spi.c new file mode 100644 index 0000000..c234d90 --- /dev/null +++ b/drivers/spi/oc_tiny_spi.c @@ -0,0 +1,241 @@ +/* + * Opencore tiny_spi driver + * + * http://opencores.org/project,tiny_spi + * + * based on bfin_spi.c + * Copyright (c) 2005-2008 Analog Devices Inc. + * Copyright (C) 2010 Thomas Chou <thomas(a)wytron.com.tw> + * + * Licensed under the GPL-2 or later. + */ +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> +#include <asm/gpio.h> +#define TINY_SPI_RXDATA 0 +#define TINY_SPI_TXDATA 4 +#define TINY_SPI_STATUS 8 +#define TINY_SPI_CONTROL 12 +#define TINY_SPI_BAUD 16 + +#define TINY_SPI_STATUS_TXE 0x1 +#define TINY_SPI_STATUS_TXR 0x2 + +struct tiny_spi_host { + ulong base; + uint freq; + uint baudwidth; +}; +static struct tiny_spi_host tiny_spi_host_list[] = CONFIG_SYS_TINY_SPI_LIST; + +struct tiny_spi_slave { + struct spi_slave slave; + struct tiny_spi_host *host; + uint mode; + uint baud; + uint flg; +}; +#define to_tiny_spi_slave(s) container_of(s, struct tiny_spi_slave, slave) + +__attribute__((weak)) +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus < ARRAY_SIZE(tiny_spi_host_list) && gpio_is_valid(cs); +} + +__attribute__((weak)) +void spi_cs_activate(struct spi_slave *slave) +{ + struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); + unsigned int cs = slave->cs; + gpio_set_value(cs, tiny_spi->flg); + debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs)); +} + +__attribute__((weak)) +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); + unsigned int cs = slave->cs; + gpio_set_value(cs, !tiny_spi->flg); + debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs)); +} + +void spi_set_speed(struct spi_slave *slave, uint hz) +{ + struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); + struct tiny_spi_host *host = tiny_spi->host; + tiny_spi->baud = DIV_ROUND_UP(host->freq, hz * 2) - 1; + if (tiny_spi->baud > (1 << host->baudwidth) - 1) + tiny_spi->baud = (1 << host->baudwidth) - 1; + debug("%s: speed %u actual %u\n", __func__, hz, + host->freq / ((tiny_spi->baud + 1) * 2)); +} + +void spi_init(void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int hz, unsigned int mode) +{ + struct tiny_spi_slave *tiny_spi; + + if (!spi_cs_is_valid(bus, cs) || gpio_request(cs, "tiny_spi")) + return NULL; + + tiny_spi = malloc(sizeof(*tiny_spi)); + if (!tiny_spi) + return NULL; + memset(tiny_spi, 0, sizeof(*tiny_spi)); + + tiny_spi->slave.bus = bus; + tiny_spi->slave.cs = cs; + tiny_spi->host = &tiny_spi_host_list[bus]; + tiny_spi->mode = mode & (SPI_CPOL | SPI_CPHA); + tiny_spi->flg = mode & SPI_CS_HIGH ? 1 : 0; + spi_set_speed(&tiny_spi->slave, hz); + + debug("%s: bus:%i cs:%i base:%lx\n", __func__, + bus, cs, tiny_spi->host->base); + return &tiny_spi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); + gpio_free(slave->cs); + free(tiny_spi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); + struct tiny_spi_host *host = tiny_spi->host; + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + gpio_direction_output(slave->cs, !tiny_spi->flg); + writel(tiny_spi->mode, host->base + TINY_SPI_CONTROL); + writel(tiny_spi->baud, host->base + TINY_SPI_BAUD); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); +} + +#ifndef CONFIG_TINY_SPI_IDLE_VAL +# define CONFIG_TINY_SPI_IDLE_VAL 0xff +#endif + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct tiny_spi_host *host = to_tiny_spi_slave(slave)->host; + const u8 *txp = dout; + u8 *rxp = din; + uint bytes = bitlen / 8; + uint i; + + debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, + slave->bus, slave->cs, bitlen, bytes, flags); + if (bitlen == 0) + goto done; + + /* assume to do 8 bits transfers */ + if (bitlen % 8) { + flags |= SPI_XFER_END; + goto done; + } + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + /* we need to tighten the transfer loop */ + if (txp && rxp) { + writeb(*txp++, host->base + TINY_SPI_TXDATA); + if (bytes > 1) { + writeb(*txp++, host->base + TINY_SPI_TXDATA); + for (i = 2; i < bytes; i++) { + u8 rx, tx = *txp++; + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXR)) + ; + rx = readb(host->base + TINY_SPI_TXDATA); + writeb(tx, host->base + TINY_SPI_TXDATA); + *rxp++ = rx; + } + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXR)) + ; + *rxp++ = readb(host->base + TINY_SPI_TXDATA); + } + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXE)) + ; + *rxp++ = readb(host->base + TINY_SPI_RXDATA); + } else if (rxp) { + writeb(CONFIG_TINY_SPI_IDLE_VAL, host->base + TINY_SPI_TXDATA); + if (bytes > 1) { + writeb(CONFIG_TINY_SPI_IDLE_VAL, + host->base + TINY_SPI_TXDATA); + for (i = 2; i < bytes; i++) { + u8 rx; + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXR)) + ; + rx = readb(host->base + TINY_SPI_TXDATA); + writeb(CONFIG_TINY_SPI_IDLE_VAL, + host->base + TINY_SPI_TXDATA); + *rxp++ = rx; + } + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXR)) + ; + *rxp++ = readb(host->base + TINY_SPI_TXDATA); + } + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXE)) + ; + *rxp++ = readb(host->base + TINY_SPI_RXDATA); + } else if (txp) { + writeb(*txp++, host->base + TINY_SPI_TXDATA); + if (bytes > 1) { + writeb(*txp++, host->base + TINY_SPI_TXDATA); + for (i = 2; i < bytes; i++) { + u8 tx = *txp++; + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXR)) + ; + writeb(tx, host->base + TINY_SPI_TXDATA); + } + } + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXE)) + ; + } else { + writeb(CONFIG_TINY_SPI_IDLE_VAL, host->base + TINY_SPI_TXDATA); + if (bytes > 1) { + writeb(CONFIG_TINY_SPI_IDLE_VAL, + host->base + TINY_SPI_TXDATA); + for (i = 2; i < bytes; i++) { + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXR)) + ; + writeb(CONFIG_TINY_SPI_IDLE_VAL, + host->base + TINY_SPI_TXDATA); + } + } + while (!(readb(host->base + TINY_SPI_STATUS) & + TINY_SPI_STATUS_TXE)) + ; + } + + done: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} -- 1.7.3.4

3 8

[U-Boot] [PATCH] fsl: add 'pixis_reset dump' command
by Timur Tabi 29 Apr '11

29 Apr '11

Add the 'pixis_reset dump' command, which displays the contents of the PIXIS registers. This command is only available if DEBUG is defined. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- board/freescale/common/ngpixis.c | 58 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 58 insertions(+), 0 deletions(-) diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index 4e01e5a..765f035 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -119,11 +119,50 @@ void __set_altbank(void) } void set_altbank(void) __attribute__((weak, alias("__set_altbank"))); +#ifdef DEBUG +static void pixis_dump_regs(void) +{ + unsigned int i; + + printf("id=%02x\n", PIXIS_READ(id)); + printf("arch=%02x\n", PIXIS_READ(arch)); + printf("scver=%02x\n", PIXIS_READ(scver)); + printf("csr=%02x\n", PIXIS_READ(csr)); + printf("rst=%02x\n", PIXIS_READ(rst)); + printf("aux=%02x\n", PIXIS_READ(aux)); + printf("spd=%02x\n", PIXIS_READ(spd)); + printf("brdcfg0=%02x\n", PIXIS_READ(brdcfg0)); + printf("brdcfg1=%02x\n", PIXIS_READ(brdcfg1)); + printf("addr=%02x\n", PIXIS_READ(addr)); + printf("data=%02x\n", PIXIS_READ(data)); + printf("led=%02x\n", PIXIS_READ(led)); + printf("vctl=%02x\n", PIXIS_READ(vctl)); + printf("vstat=%02x\n", PIXIS_READ(vstat)); + printf("vcfgen0=%02x\n", PIXIS_READ(vcfgen0)); + printf("ocmcsr=%02x\n", PIXIS_READ(ocmcsr)); + printf("ocmmsg=%02x\n", PIXIS_READ(ocmmsg)); + printf("gmdbg=%02x\n", PIXIS_READ(gmdbg)); + printf("sclk=%02x%02x%02x\n", + PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2])); + printf("dclk=%02x%02x%02x\n", + PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2])); + printf("watch=%02x\n", PIXIS_READ(watch)); + + for (i = 0; i < 8; i++) { + printf("SW%u=%02x/%02x ", i + 1, + PIXIS_READ(s[i].sw), PIXIS_READ(s[i].en)); + } + putc('\n'); +} +#endif int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned int i; char *p_altbank = NULL; +#ifdef DEBUG + char *p_dump = NULL; +#endif char *unknown_param = NULL; /* No args is a simple reset request. @@ -137,6 +176,13 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) continue; } +#ifdef DEBUG + if (strcmp(argv[i], "dump") == 0) { + p_dump = argv[i]; + continue; + } +#endif + unknown_param = argv[i]; } @@ -145,6 +191,15 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } +#ifdef DEBUG + if (p_dump) { + pixis_dump_regs(); + + /* 'dump' ignores other commands */ + return 0; + } +#endif + if (p_altbank) set_altbank(); else @@ -161,4 +216,7 @@ U_BOOT_CMD( "Reset the board using the FPGA sequencer", "- hard reset to default bank\n" "pixis_reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "pixis_reset dump - display the PIXIS registers\n" +#endif ); -- 1.7.3.4

2 1

[U-Boot] [PATCH] cfb_console: fix RLE bitmap drawing code
by Anatolij Gustschin 28 Apr '11

28 Apr '11

There seems to be tools producing incorrect 'end of bitmap data' markers '0100' in a RLE bitmap. Drawing such bitmaps can result in overwriting memory above the frame buffer. E.g. on MPC5121e based boards this memory can contain U-Boot environment. We may not rely on the correct end of bitmap data marker 0001 only, but also have to check whether we are going to draw a valid frame buffer scan line. The patch provides a simple fix by checking the row index: we finish the drawing if the row index becomes negative. Reported-by: Michael Weiss <michael.weiss(a)ifm.com> Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Tested-by: Anatolij Gustschin <agust(a)denx.de> --- drivers/video/cfb_console.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 3d047f2..599ebdb 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -938,7 +938,10 @@ static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, /* scan line end marker */ bm += 2; x = 0; - y--; + if (--y < 0) { + decode = 0; + continue; + } fbp = (unsigned char *) ((unsigned int)video_fb_address + (((y + yoff) * VIDEO_COLS) + @@ -952,6 +955,10 @@ static int display_rle8_bitmap (bmp_image_t *img, int xoff, int yoff, /* run offset marker */ x += bm[2]; y -= bm[3]; + if (y < 0) { + decode = 0; + continue; + } fbp = (unsigned char *) ((unsigned int)video_fb_address + (((y + yoff) * VIDEO_COLS) + -- 1.7.1

1 2

[U-Boot] [PATCH 0/3] Add support for the MMC device to the vexpress
by matt.waddel＠linaro.org 28 Apr '11

28 Apr '11

From: Matt Waddel <matt.waddel(a)linaro.org> These patches add support for the ARM PrimeCell PL180 MultiMedia Interface. The Versatile Express was the test platform for these changes. Matt Waddel (3): MMC: Max blocks value adjustable MMC: Add support for PL180 ARM mmc device ARMV7: Vexpress: Add MMC support board/armltd/vexpress/ca9x4_ct_vxp.c | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/mmc.c | 19 +- drivers/mmc/mmci.c | 452 ++++++++++++++++++++++++++++++++++ drivers/mmc/mmci.h | 181 ++++++++++++++ include/configs/ca9x4_ct_vxp.h | 4 + 6 files changed, 656 insertions(+), 10 deletions(-) create mode 100644 drivers/mmc/mmci.c create mode 100644 drivers/mmc/mmci.h

6 24

[U-Boot] [PATCH v6 0/7] those series patches for add ben nanonote board
by Xiangfu Liu 26 Apr '11

26 Apr '11

Hi Wolfgang those patches are for add xburst jz4740 base file and Ben NanoNote (codename qi_lb60) to U-Boot some info about xburst jz4740: the xburst jz4740 is recently added to linux 2.6.36 and it's support the device Ben NanoNote out of box, this xburst jz4740 cpu have one feature is Boot From USB, there is a small rom in jz4740, but LOW some PIN, the cpu will boot to this small rom, then init cpu and USB module, then we can send 8KB bin file to the cpu by USB(by using 'xbboot' or 'usbboot'[1]). which means if your bootloader is borken,(the first few KBs in NAND) you can always boot the device from usb, then reflash the nand. in OpenMoko FreeRunner, there are NOR and NAND. when people broken the nand bootloader, it's must boot from NOR, reflash the bootloader back when people broken the NAND and NOR, he(she) must reflash by using JTAG but in Ben NanoNote, we just need boot from usb. flash the nand again :) BTW:there are a lot of PMP, Audio device in China use the Xburst cpu, but I think they are all base on u-boot 1.1.6. by working on Ben NanoNote (http://en.qi-hardware.com) one year, we try to update the u-boot to last version and send it to upstream. :) for more info about Ingenic Xburst JZ4740 http://www.ingenic.cn/eng/default.aspx http://www.linux-mips.org/wiki/Ingenic Xiangfu Liu (7): those files are jz4740 base files this is jz4740 head file jz4740 nand spl files jz4740 nand driver add Ben NanoNote board add entry to MAINTAINERS and boards.cfg modify files for ben nanonote board MAINTAINERS | 4 + MAKEALL | 4 +- Makefile | 13 + arch/mips/cpu/xburst/Makefile | 50 ++ arch/mips/cpu/xburst/config.mk | 33 + arch/mips/cpu/xburst/cpu.c | 160 +++++ arch/mips/cpu/xburst/jz4740.c | 264 +++++++ arch/mips/cpu/xburst/jz_serial.c | 114 +++ arch/mips/cpu/xburst/start.S | 160 +++++ arch/mips/cpu/xburst/start_spl.S | 63 ++ arch/mips/cpu/xburst/timer.c | 167 +++++ arch/mips/cpu/xburst/usbboot.S | 841 ++++++++++++++++++++++ arch/mips/include/asm/global_data.h | 15 + arch/mips/include/asm/jz4740.h | 1102 +++++++++++++++++++++++++++++ arch/mips/lib/board.c | 8 + arch/mips/lib/time.c | 2 + board/xburst/nanonote/Makefile | 45 ++ board/xburst/nanonote/config.mk | 31 + board/xburst/nanonote/nanonote.c | 95 +++ board/xburst/nanonote/u-boot-nand.lds | 63 ++ boards.cfg | 1 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/jz4740_nand.c | 329 +++++++++ include/configs/nanonote.h | 205 ++++++ include/configs/qi_lb60.h | 34 + nand_spl/board/xburst/nanonote/Makefile | 106 +++ nand_spl/board/xburst/nanonote/u-boot.lds | 63 ++ 27 files changed, 3972 insertions(+), 1 deletions(-) create mode 100644 arch/mips/cpu/xburst/Makefile create mode 100644 arch/mips/cpu/xburst/config.mk create mode 100644 arch/mips/cpu/xburst/cpu.c create mode 100644 arch/mips/cpu/xburst/jz4740.c create mode 100644 arch/mips/cpu/xburst/jz_serial.c create mode 100644 arch/mips/cpu/xburst/start.S create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 arch/mips/cpu/xburst/timer.c create mode 100644 arch/mips/cpu/xburst/usbboot.S create mode 100644 arch/mips/include/asm/jz4740.h create mode 100644 board/xburst/nanonote/Makefile create mode 100644 board/xburst/nanonote/config.mk create mode 100644 board/xburst/nanonote/nanonote.c create mode 100644 board/xburst/nanonote/u-boot-nand.lds create mode 100644 drivers/mtd/nand/jz4740_nand.c create mode 100644 include/configs/nanonote.h create mode 100644 include/configs/qi_lb60.h create mode 100644 nand_spl/board/xburst/nanonote/Makefile create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds

3 22

[U-Boot] [PATCH 1/2] cmd_ide: enhance new feature "CONFIG_IDE_AHB"
by Macpaul Lin 25 Apr '11

25 Apr '11

Although most IDE controller is designed to be connected to PCI bridge, there are still some IDE controller support AHB interface for SoC design. The driver implementation of these IDE-AHB controllers differ from other IDE-PCI controller, some additional registers and commands access is required during CMD/DATA I/O. Hence a configuration "CONFIG_IDE_AHB" in cmd_ide.c is required to be defined to support these kinds of SoC controllers. Such as Faraday's FTIDE020 series and Global Unichip's UINF-0301. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- README | 8 ++++++++ common/cmd_ide.c | 37 ++++++++++++++++++++++++++++++++++++- 2 files changed, 44 insertions(+), 1 deletions(-) diff --git a/README b/README index 727bf8a..3de0605 100644 --- a/README +++ b/README @@ -2673,6 +2673,14 @@ Low Level (hardware related) configuration options: source code. It is used to make hardware dependant initializations. +- CONFIG_IDE_AHB: + Most IDE controllers were designed to be connected with PCI + interface. Only few of them were designed for AHB interface. + When software is doing ATA command and data transfer to + IDE devices through IDE-AHB controller, some additional + registers accessing to these kind of IDE-AHB controller + is requierd. + - CONFIG_SYS_IMMR: Physical address of the Internal Memory. DO NOT CHANGE unless you know exactly what you're doing! (11-4) [MPC8xx/82xx systems only] diff --git a/common/cmd_ide.c b/common/cmd_ide.c index ea0f4a7..edb4fc0 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -518,8 +518,22 @@ __ide_outb(int dev, int port, unsigned char val) { debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", dev, port, val, (ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port))); + +#if defined(CONFIG_IDE_AHB) + if (port) { + /* write command */ + extern void ide_write_register(int, unsigned int, unsigned char); + + ide_write_register(dev, port, val); + } else { + /* write data */ + outb(val, (ATA_CURR_BASE(dev))); + } +#else outb(val, (ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port))); +#endif } + void ide_outb (int dev, int port, unsigned char val) __attribute__((weak, alias("__ide_outb"))); @@ -527,7 +541,15 @@ unsigned char inline __ide_inb(int dev, int port) { uchar val; + +#if defined(CONFIG_IDE_AHB) + extern unsigned char ide_read_register(int, unsigned int); + + val = ide_read_register(dev, port); +#else val = inb((ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port))); +#endif + debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", dev, port, (ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port)), val); return val; @@ -696,6 +718,7 @@ void ide_init (void) ide_dev_desc[i].blksz=0; ide_dev_desc[i].lba=0; ide_dev_desc[i].block_read=ide_read; + ide_dev_desc[i].block_write = ide_write; if (!ide_bus_ok[IDE_BUS(i)]) continue; ide_led (led, 1); /* LED on */ @@ -902,7 +925,13 @@ output_data(int dev, ulong *sect_buf, int words) static void output_data(int dev, ulong *sect_buf, int words) { - outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words<<1); +#if defined(CONFIG_IDE_AHB) + extern void ide_write_data(int, ulong *, int); + + ide_write_data(dev, sect_buf, words); +#else + outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1); +#endif } #endif /* CONFIG_IDE_SWAP_IO */ @@ -960,7 +989,13 @@ input_data(int dev, ulong *sect_buf, int words) static void input_data(int dev, ulong *sect_buf, int words) { +#if defined(CONFIG_IDE_AHB) + extern void ide_read_data(int, ulong *, int); + + ide_read_data(dev, sect_buf, words); +#else insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1); +#endif } #endif /* CONFIG_IDE_SWAP_IO */ -- 1.7.3.5

3 4

[U-Boot] [PATCH] xilinx_ppc_boards: Change address of RESET_VECTOR
by Ricardo Ribalda Delgado 21 Apr '11

21 Apr '11

Old address of RESET_VECTOR were overwritten by the bss sector, making impossible its run from xmd. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- boards.cfg | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/boards.cfg b/boards.cfg index 94b8745..2ba603d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -675,9 +675,9 @@ yellowstone powerpc ppc4xx yosemite amcc yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE yucca powerpc ppc4xx - amcc AP1000 powerpc ppc4xx ap1000 amirix -fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o +fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o -v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o +v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o v5fx30teval_flash powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o CRAYL1 powerpc ppc4xx L1 cray CATcenter powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1 @@ -736,11 +736,11 @@ p3p440 powerpc ppc4xx - prodriv KAREF powerpc ppc4xx karef sandburst METROBOX powerpc ppc4xx metrobox sandburst xpedite1000 powerpc ppc4xx - xes -ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o +ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o ml507_flash powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o -xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC +xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 xilinx-ppc405-generic_flash powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC -xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1 +xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC rsk7203 sh sh2 rsk7203 renesas - mpr2 sh sh3 mpr2 - - -- 1.7.2.3

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[U-Boot] [PATCH 00/15] [REWORK AVR32/AT91] additional changes for avr32
by Andreas Bießmann 19 Apr '11

19 Apr '11

This series do some cleanup all avr32 boards. This series is on top of 'Get AVR32 boards working with partial linking' rebased to u-boot-atmel/rework110202. In summary the board specific config.mk and u-boot.lds files are deleted in favor of a version at architecture level. Theses files had all the same content cause they where pure copies of the atstk100x ones. I have splitted the patches to each board cause some of them should be actively maintained and the respectively maintainer should have a chance to give some feedback. Andreas Bießmann (15): avr32/config.mk: simplify PLATFORM_RELFLAGS avr32: use single linker script atngw100: fix "#define XXXX 1" atstk1002: fix "#define XXXX 1" atstk1003: fix "#define XXXX 1" atstk1004: fix "#define XXXX 1" atstk1006: fix "#define XXXX 1" favr-32-ezkit: fix "#define XXXX 1" hammerhead: fix "#define XXXX 1" mimc200: fix "#define XXXX 1" atngw100: move CONFIG_SYS_TEXT_BASE to header atstk100x: move CONFIG_SYS_TEXT_BASE to header favr-32-ezkit: move CONFIG_SYS_TEXT_BASE to header mimc200: move CONFIG_SYS_TEXT_BASE to header hammerhead: move CONFIG_SYS_TEXT_BASE to header arch/avr32/config.mk | 4 + .../atmel/atstk1000 => arch/avr32/cpu}/u-boot.lds | 0 board/atmel/atngw100/config.mk | 2 - board/atmel/atngw100/u-boot.lds | 72 -------------------- board/atmel/atstk1000/config.mk | 3 - board/earthlcd/favr-32-ezkit/config.mk | 3 - board/earthlcd/favr-32-ezkit/u-boot.lds | 70 ------------------- board/mimc/mimc200/config.mk | 2 - board/mimc/mimc200/u-boot.lds | 72 -------------------- board/miromico/hammerhead/config.mk | 2 - board/miromico/hammerhead/u-boot.lds | 72 -------------------- include/configs/atngw100.h | 55 ++++++++------- include/configs/atstk1002.h | 49 +++++++------- include/configs/atstk1003.h | 43 ++++++------ include/configs/atstk1004.h | 43 ++++++------ include/configs/atstk1006.h | 49 +++++++------- include/configs/favr-32-ezkit.h | 47 +++++++------ include/configs/hammerhead.h | 49 +++++++------- include/configs/mimc200.h | 57 ++++++++-------- 19 files changed, 204 insertions(+), 490 deletions(-) rename {board/atmel/atstk1000 => arch/avr32/cpu}/u-boot.lds (100%) delete mode 100644 board/atmel/atngw100/config.mk delete mode 100644 board/atmel/atngw100/u-boot.lds delete mode 100644 board/atmel/atstk1000/config.mk delete mode 100644 board/earthlcd/favr-32-ezkit/config.mk delete mode 100644 board/earthlcd/favr-32-ezkit/u-boot.lds delete mode 100644 board/mimc/mimc200/config.mk delete mode 100644 board/mimc/mimc200/u-boot.lds delete mode 100644 board/miromico/hammerhead/config.mk delete mode 100644 board/miromico/hammerhead/u-boot.lds -- 1.7.2.3

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