December 2011 - U-Boot

[U-Boot] [PATCH] Adds driver for Xilinx' xps_spi SPI controller.
by Graeme Smecher 02 Apr '12

02 Apr '12

This code differs in only trivial ways from the altera_spi driver. It plays nice with Thomas Chou's mmc_spi driver, as well as with SPI flash. Documentation for the SPI core is available here: http://www.xilinx.com/support/documentation/ip_documentation/xps_spi.pdf Signed-off-by: Graeme Smecher <graeme.smecher(a)mail.mcgill.ca> --- drivers/spi/Makefile | 1 + drivers/spi/xilinx_spi.c | 173 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 174 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/xilinx_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index dfcbb8b..34e0f31 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.a COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o +COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c new file mode 100644 index 0000000..bda7c5b --- /dev/null +++ b/drivers/spi/xilinx_spi.c @@ -0,0 +1,173 @@ +/* + * Xilinx SPI driver + * + * based on bfin_spi.c, by way of altera_spi.c + * Copyright (c) 2005-2008 Analog Devices Inc. + * Copyright (c) 2010 Thomas Chou <thomas(a)wytron.com.tw> + * Copyright (c) 2010 Graeme Smecher <graeme.smecher(a)mail.mcgill.ca> + * + * Licensed under the GPL-2 or later. + */ +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> + +#define XILINX_SPI_RR 0x6c +#define XILINX_SPI_TR 0x68 +#define XILINX_SPI_SR 0x64 +#define XILINX_SPI_CR 0x60 +#define XILINX_SPI_SSR 0x70 + +#define XILINX_SPI_SR_RX_EMPTY_MSK 0x01 + +#define XILINX_SPI_CR_DEFAULT (0x0006) +#define XILINX_SPI_CR_MSS_MSK (0x0080) + +#if XPAR_XSPI_NUM_INSTANCES > 4 +# warning "The xilinx_spi driver will ignore some of your SPI peripherals!" +#endif + +static ulong xilinx_spi_base_list[] = { +#ifdef XPAR_SPI_0_BASEADDR + XPAR_SPI_0_BASEADDR, +#endif +#ifdef XPAR_SPI_1_BASEADDR + XPAR_SPI_1_BASEADDR, +#endif +#ifdef XPAR_SPI_2_BASEADDR + XPAR_SPI_2_BASEADDR, +#endif +#ifdef XPAR_SPI_3_BASEADDR + XPAR_SPI_3_BASEADDR, +#endif +}; + +struct xilinx_spi_slave { + struct spi_slave slave; + ulong base; +}; +#define to_xilinx_spi_slave(s) container_of(s, struct xilinx_spi_slave, slave) + +__attribute__((weak)) +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32; +} + +__attribute__((weak)) +void spi_cs_activate(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + writel(~(1 << slave->cs), xilspi->base + XILINX_SPI_SSR); + writel(XILINX_SPI_CR_DEFAULT | XILINX_SPI_CR_MSS_MSK, + xilspi->base + XILINX_SPI_CR); +} + +__attribute__((weak)) +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + + writel(XILINX_SPI_CR_DEFAULT, xilspi->base + XILINX_SPI_CR); + writel(~0, xilspi->base + XILINX_SPI_SSR); +} + +void spi_init(void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct xilinx_spi_slave *xilspi; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + xilspi = malloc(sizeof(*xilspi)); + if (!xilspi) + return NULL; + + xilspi->slave.bus = bus; + xilspi->slave.cs = cs; + xilspi->base = xilinx_spi_base_list[bus]; + debug("%s: bus:%i cs:%i base:%lx\n", __func__, + bus, cs, xilspi->base); + + return &xilspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + free(xilspi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + writel(XILINX_SPI_CR_DEFAULT, xilspi->base + XILINX_SPI_CR); + writel(~0, xilspi->base + XILINX_SPI_SSR); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + writel(~0, xilspi->base + XILINX_SPI_SSR); +} + +#ifndef CONFIG_XILINX_SPI_IDLE_VAL +# define CONFIG_XILINX_SPI_IDLE_VAL 0xff +#endif + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + /* assume spi core configured to do 8 bit transfers */ + uint bytes = bitlen / 8; + const uchar *txp = dout; + uchar *rxp = din; + + debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, + slave->bus, slave->cs, bitlen, bytes, flags); + if (bitlen == 0) + goto done; + + if (bitlen % 8) { + flags |= SPI_XFER_END; + goto done; + } + + /* empty read buffer */ + while (!(readl(xilspi->base + XILINX_SPI_SR) & + XILINX_SPI_SR_RX_EMPTY_MSK)) + readl(xilspi->base + XILINX_SPI_RR); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (bytes--) { + uchar d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; + debug("%s: tx:%x ", __func__, d); + writel(d, xilspi->base + XILINX_SPI_TR); + while (readl(xilspi->base + XILINX_SPI_SR) & + XILINX_SPI_SR_RX_EMPTY_MSK) + ; + d = readl(xilspi->base + XILINX_SPI_RR); + if (rxp) + *rxp++ = d; + debug("rx:%x\n", d); + } + done: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} -- 1.6.3.3

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[U-Boot] [PATCH 00/11] MIPS: fixes and updates
by Daniel Schwierzeck 02 Apr '12

02 Apr '12

This series contains bugfixes and coding style cleanups. Furthermore it contains some extensions for MIPS24k and MIPS34k cores as preparation for merging the support for various Lantiq SoCs. Daniel Schwierzeck (11): MIPS: board.c: make checkpatch.pl clean MIPS: board.c: fix warning if CONFIG_CMD_NET is not defined MIPS: board.c: fix init of flash data in bd_info MIPS: add register definition for EBase register MIPS: add sleep handler for slave CPUs in multi-processor systems MIPS: make cache operation mode configurable in dcache_enable() MIPS: extend cache initialization for MIPS24K and MIPS34K cores MIPS: add additional reserved vectors for MIPS24K and MIPS34K cores MIPS: add header file for generic GPIO API MIPS: add init hook for CPU specific initialization MIPS: MAKEALL: fix lists for MIPSel and MIPS boards MAKEALL | 11 +--- arch/mips/cpu/mips32/cache.S | 24 ++++++- arch/mips/cpu/mips32/start.S | 37 ++++++++++- arch/mips/include/asm/gpio.h | 13 ++++ arch/mips/include/asm/mipsregs.h | 20 ++++++ arch/mips/lib/board.c | 139 +++++++++++++++++++++----------------- 6 files changed, 171 insertions(+), 73 deletions(-) create mode 100644 arch/mips/include/asm/gpio.h -- 1.7.7.2

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[U-Boot] [PATCH] m28evk: Use GENERATED_GBL_DATA_SIZE
by Fabio Estevam 02 Apr '12

02 Apr '12

Use GENERATED_GBL_DATA_SIZE for calculating CONFIG_SYS_INIT_SP_OFFSET. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/m28evk.h | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 39c841f..2b4871e 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -92,7 +92,14 @@ #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Point initial SP in SRAM so SPL can use it too. */ -#define CONFIG_SYS_INIT_SP_ADDR 0x00002000 + +#define CONFIG_SYS_INIT_RAM_ADDR 0x00002000 +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* * We need to sacrifice first 4 bytes of RAM here to avoid triggering some * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot -- 1.7.1

4 6

Re: [U-Boot] [PATCH] MIPS: fix endianess handling
by Shinya Kuribayashi 31 Mar '12

31 Mar '12

On 12/4/11 9:02 PM, Daniel Schwierzeck wrote: >> diff --git a/boards.cfg b/boards.cfg >> index c83d861..2cd917e 100644 >> --- a/boards.cfg >> +++ b/boards.cfg >> @@ -324,13 +324,13 @@ dbau1000 mips mips32 dbau1x00 - >> dbau1100 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1100 >> dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500 >> dbau1550 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550 >> -dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550 >> +dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN This looks Ok. >> gth2 mips mips32 - - au1x00 >> incaip mips mips32 incaip - incaip >> incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000 >> incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000 >> incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000 >> -pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000 >> +pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000,SYS_LITTLE_ENDIAN >> qemu_mips mips mips32 qemu-mips - - qemu-mips >> tb0229 mips mips32 >> vct_premium mips mips32 vct micronas - vct:VCT_PREMIUM But I don't see any reason CONFIG_SYS_LITTLE_ENDIAN is specified in boards.cfg. Just putting it in configs/pb1000.h is enough, isn't it? > Shinya, do you have an opinion about this? No, if it works for you, I'm fine. Thanks for tackling this issue. Does anyone disagree with this change? If not, I'll pick this up. >> diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile >> index e23865b..eab23b4 100644 >> --- a/examples/standalone/Makefile >> +++ b/examples/standalone/Makefile >> @@ -88,6 +88,10 @@ endif >> CFLAGS_NTR := $(call cc-option,-fno-toplevel-reorder) >> CFLAGS += $(CFLAGS_NTR) >> >> +# Pass through endianess settings in LDFLAGS to LD s/endianess/endianness/

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[U-Boot] [PATCH] Honor /memory/reg node in DTB files
by Deepak Saxena 31 Mar '12

31 Mar '12

commit 341764495180a712b9aaccfa0479b2ff7e44e35b Author: Deepak Saxena <deepak_saxena(a)mentor.com> Date: Mon Dec 6 15:52:07 2010 -0800 Honor /memory/reg node in DTB files This patch adds code to the bootm path to check if a valid /memory/reg node exists in the DTB file and if so, it does not override it with the values in bi_memstart and bi_memsize. This is particularly useful in multi-core environments where the memory may be partitioned across a large number of nodes. While the same can be accomplished on certain boards (p1022ds and p1_p2_rdb) by using the bootm_low and bootm_size environment variables, that solution is not universal and requires adding code ft_board_setup() for any new board that wants to support AMP operation. Also, given that the DTB is already used to partition board devices (see commit dc2e673 in the Linux kernel tree), it makes sense to allow memory to be partitioned the same way from a user configuration perspective. This patch allows for the user to override the DTB file parameters on the p1022ds and p1_p2_rdb boards by setting the bootm_low and bootm_size to something other than bi_memstart and bi_memsize. In the long-term, those env variables should be depecrated and removed and system implementors should provide the memory partitioning information in the DTB. Signed-off-by: Deepak Saxena <deepak_saxena(a)mentor.com> Signed-off-by: Hollis Blanchard <hollis_blanchard(a)mentor.com> --- See http://lists.denx.de/pipermail/u-boot/2010-December/083057.html for initial proposal on this. diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 4540364..6d384e3 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -377,6 +377,55 @@ static void ft_fixup_qe_snum(void *blob) } #endif +/* + * Check to see if an valid memory/reg property exists + * in the fdt. If so, we do not overwrite it with what's + * been scanned. + * + * Valid mean all the following: + * + * - Memory node has a device-type of "memory" + * - A reg property exists which: + * + has exactly as many cells as #address-cells + #size-cells + * + provides a range that is within [bi_memstart, bi_memstart + bi_memsize] + */ +static int ft_validate_memory(void *blob, bd_t *bd) +{ + int nodeoffset; + u32 *addrcell = (u32*)fdt_getprop(blob, 0, "#address-cells", NULL); + u32 *sizecell = (u32*)fdt_getprop(blob, 0, "#size-cells", NULL); + u64 reg_base, reg_size; + void *reg, *dtype; + int len; + + if ((nodeoffset = fdt_path_offset(blob, "/memory")) >= 0) + { + dtype = fdt_getprop(blob, nodeoffset, "device_type", &len); + if (!dtype || (strcmp(dtype, "memory") != 0)) + return 0; + + reg = fdt_getprop(blob, nodeoffset, "reg", &len); + if (reg && len == ((*addrcell + *sizecell) * 4)) { + if (*addrcell == 2) { + reg_base = ((u64*)reg)[0]; + reg_size = ((u64*)reg)[1]; + } else { + reg_base = ((u32*)reg)[0]; + reg_size = ((u32*)reg)[1]; + } + + if ((reg_size) && + (reg_base >= (u64)bd->bi_memstart) && + ((reg_size + reg_base) + <= ((u64)bd->bi_memstart + (u64)bd->bi_memsize))) + return 1; + } + } + + return 0; + +} + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -434,7 +483,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); #endif - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + if (!ft_validate_memory(blob, bd)) + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 5cdee9f..7378d88 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -320,7 +320,8 @@ void ft_board_setup(void *blob, bd_t *bd) base = getenv_bootm_low(); size = getenv_bootm_size(); - fdt_fixup_memory(blob, (u64)base, (u64)size); + if (base != (phys_addr_t)bd->bi_memstart && size != (phys_addr_t)bd->bi_memsize) + fdt_fixup_memory(blob, (u64)base, (u64)size); FT_FSL_PCI_SETUP; diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index fae31f2..5e4adc6 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -220,9 +220,10 @@ void ft_board_setup(void *blob, bd_t *bd) base = getenv_bootm_low(); size = getenv_bootm_size(); - ft_pci_board_setup(blob); + if (base != (phys_addr_t)bd->bi_memstart && size != (phys_addr_t)bd->bi_memsize) + fdt_fixup_memory(blob, (u64)base, (u64)size); - fdt_fixup_memory(blob, (u64)base, (u64)size); + ft_pci_board_setup(blob); } #endif

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[U-Boot] [PATCH v3 0/6] Introduce generic relocation feature
by Simon Glass 31 Mar '12

31 Mar '12

(I am resending this rebased so I can continue with this board-unification work and allow people to review patches. There were some comments on the v2 series but my questions have been sitting on the list for 2 weeks so it is probably time for a new series.) This is the second patch series aiming to unify the various board.c files in each architecture into a single one. This series implements a generic relocation feature, which is the bridge between board_init_f() and board_init_r(). It then moves ARM over to use this framework, as an example. On ARM the relocation code is duplicated for each CPU yet it is the same. We can bring this up to the arch level. But since (I believe) Elf relocation is basically the same process for all archs, there is no reason not to bring it up to the generic level. Each architecture which uses this framework needs to provide a function called arch_elf_relocate_entry() which processes a single relocation entry. This is a static inline function to reduce code size overhead. For ARM, a new arch/arm/lib/proc.S file is created, which holds generic ARM assembler code (things that cannot be written in C and are common functions used by all ARM CPUs). This helps reduce duplication. Interrupt handling code and perhaps even some startup code can move there later. It may be useful for other architectures with a lot of different CPUs to have a similar file. Code size on my ARMv7 system increases by 54 bytes with generic relocation. This overhead is mostly just literal pool access and setting up to call the relocated U-Boot at the end. On my system, execution time increases from 10.8ms to 15.6ms due to the less efficient C implementations of the copy and zero loops. If execution time is of concern, you can define CONFIG_USE_ARCH_MEMSET and CONFIG_USE_ARCH_MEMCPY to reduce it. For met this reduces relocation time to 5.4ms, i.e. twice as fast as the old system. One problem remains which causes mx31pdk to fail to build. It doesn't have string.c in its SPL code and the architecture-specific versions of memset()/memcpy() are too large. I propose to add a local change to reloc.c that uses inline code for boards that use the old legacy SPL framework. We can remove it later. This is not included in v2 but I am interested in comments on this approach. An alternative would be just to add simple memset()/memcpy() functions just for this board (and one other affected MX31 board). Changes in v2: - Use CONFIG_SYS_SKIP_RELOC instead of CONFIG_SYS_LEGACY_BOARD - Import asm-generic/sections.h from Linux and add U-Boot extras - Squash generic link symbols patch into generic relocation patch - Move reloc.c into common/ - Add function comments - Use memset, memcpy instead of inline code - Add README file for relocation - Invalidate I-cache when we jump to relocated code - Use an inline relocation function to reduce code size - Make relocation symbols global so we can use them outside start.S Changes in v3: - Remove the 'reloc' tag from each commit - Rebase to master Simon Glass (6): Create reloc.h and include it where needed define CONFIG_SYS_SKIP_RELOC for all archs Add generic relocation feature arm: Add processor function library arm: Move over to generic relocation arm: Remove unused code in start.S README | 4 + arch/arm/cpu/arm1136/start.S | 133 ++------------ arch/arm/cpu/arm1176/start.S | 214 ++------------------- arch/arm/cpu/arm720t/start.S | 127 ++----------- arch/arm/cpu/arm920t/start.S | 135 ++------------ arch/arm/cpu/arm925t/start.S | 135 ++------------ arch/arm/cpu/arm926ejs/davinci/spl.c | 1 + arch/arm/cpu/arm926ejs/start.S | 144 ++------------- arch/arm/cpu/arm946es/start.S | 130 ++----------- arch/arm/cpu/arm_intcm/start.S | 135 ++------------ arch/arm/cpu/armv7/omap-common/spl.c | 1 + arch/arm/cpu/armv7/start.S | 140 ++------------ arch/arm/cpu/ixp/start.S | 127 ++----------- arch/arm/cpu/lh7a40x/start.S | 124 ++----------- arch/arm/cpu/pxa/start.S | 138 ++------------ arch/arm/cpu/s3c44b0/start.S | 127 ++----------- arch/arm/cpu/sa1100/start.S | 124 ++----------- arch/arm/include/asm/reloc.h | 56 ++++++ arch/arm/lib/Makefile | 2 + arch/arm/lib/board.c | 1 + arch/arm/lib/proc.S | 40 ++++ arch/avr32/config.mk | 3 + arch/avr32/lib/board.c | 1 + arch/blackfin/config.mk | 3 + arch/m68k/config.mk | 3 + arch/m68k/lib/board.c | 1 + arch/microblaze/config.mk | 3 + arch/mips/config.mk | 3 + arch/mips/lib/board.c | 1 + arch/nds32/config.mk | 3 + arch/nds32/lib/board.c | 1 + arch/nios2/config.mk | 3 + arch/powerpc/config.mk | 3 + arch/powerpc/lib/board.c | 1 + arch/sandbox/config.mk | 3 + arch/sh/config.mk | 3 + arch/sparc/config.mk | 3 + arch/x86/config.mk | 3 + arch/x86/lib/board.c | 1 + board/freescale/mpc8313erdb/mpc8313erdb.c | 1 + board/freescale/mpc8315erdb/mpc8315erdb.c | 1 + board/samsung/smdk6400/smdk6400_nand_spl.c | 1 + board/sheldon/simpc8313/simpc8313.c | 1 + common/Makefile | 4 + common/reloc.c | 121 ++++++++++++ doc/README.relocation | 87 +++++++++ include/asm-generic/sections.h | 92 +++++++++ include/common.h | 2 +- include/reloc.h | 54 +++++ nand_spl/board/freescale/mpc8536ds/nand_boot.c | 1 + nand_spl/board/freescale/mpc8569mds/nand_boot.c | 1 + nand_spl/board/freescale/mpc8572ds/nand_boot.c | 1 + nand_spl/board/freescale/mx31pdk/Makefile | 8 +- nand_spl/board/freescale/mx31pdk/u-boot.lds | 1 + nand_spl/board/freescale/p1010rdb/nand_boot.c | 1 + nand_spl/board/freescale/p1023rds/nand_boot.c | 1 + nand_spl/board/freescale/p1_p2_rdb/nand_boot.c | 1 + nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 1 + nand_spl/board/karo/tx25/Makefile | 8 +- nand_spl/board/karo/tx25/u-boot.lds | 1 + nand_spl/nand_boot_fsl_nfc.c | 1 + 61 files changed, 705 insertions(+), 1765 deletions(-) create mode 100644 arch/arm/include/asm/reloc.h create mode 100644 arch/arm/lib/proc.S create mode 100644 common/reloc.c create mode 100644 doc/README.relocation create mode 100644 include/asm-generic/sections.h create mode 100644 include/reloc.h -- 1.7.3.1

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[U-Boot] [PATCH 0/3] Fix conflicting definitions of flush_dcache
by Stefan Kristiansson 30 Mar '12

30 Mar '12

nios2 and a couple of network drivers have been using a non defined API to flush the data cache (flush_dcache(ulong, ulong)), this is problematic since it conflicts with other architectures definitions of flush_dcache. This series cleans that up by letting the two network drivers use the defined flush_dcache_range(ulong, ulong) API. It also adds this function to the nios2 architecture to avoid breakage. Stefan Kristiansson (3): net/ethoc: use flush_dcache_range instead of flush_dcache net/altera_tse: use flush_dcache_range instead of flush_dcache nios2: add flush_dcache_range function arch/nios2/lib/cache.S | 10 ++++++++++ drivers/net/altera_tse.c | 9 ++++++--- drivers/net/ethoc.c | 6 +++--- 3 files changed, 19 insertions(+), 6 deletions(-) -- 1.7.5.4

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[U-Boot] [PATCH v2 0/3] Enable access to FAT filesystem in an ISO9660 El-Torito volume
by Kyle Moffett 30 Mar '12

30 Mar '12

This series fixes several bugs in the FAT code and the USB storage stack to make it possible to read from a FAT filesystem image embedded as an "El-Torito boot image" in an ISO9660 volume (IE: a CD or DVD). This has been tested on the eXMeritus HWW-1U-1A I've addressed the review commentary on these patches and I believe that they should be acceptable for merging into "next" now. Cheers, Kyle Moffett -- Interested in my work on the Debian powerpcspe port? I'm keeping a blog here: http://pureperl.blogspot.com/

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[U-Boot] u-boot usb-ethernet patch
by Mehmet Fatih Özay 27 Mar '12

27 Mar '12

Hello all We are using OMAP 3530 board and SMSC9512 usb-ethernet adapter. The main goal is to connect this adapter through USB OTG port and initialize at u-boot. In order to do it, we are using your u-boot patches for usb-ethernet SMSC95xx ( we patch your patch file to our u-boot-release (version u-boot 2009.11-svn12). What we succeed so far is introducing SMSC9512 to the system.As you can see from debugging below, we couldnot succeed to configure SMSC9512 and so we couldnot make ethernet work. By the way, USB OTG is connected to the OMAP through TPS6593. OMAP3 SBC3530 # usb start do usb (Re)start USB... USB: scanning bus for devices... New Device 0 usb_control_msg: devnum: 0x0, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x40 set address 1 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length 0x0 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x12 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x9 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x19 get_conf_no 0 Result 25, wLength 25 if 0, ep 0 ##EP epmaxpacketin[1] = 1 set configuration 1 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 0x0 new device strings: Mfr=0, Product=0, SerialNumber=0 Manufacturer Product SerialNumber usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 0x4 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 0x9 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length 0x4 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length 0x0 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x2 length 0x0 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x3 length 0x0 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x1, requesttype: 0x23, value 0x10 index 0x1 length 0x0 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1 length 0x0 New Device 1 usb_control_msg: devnum: 0x0, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x40 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1 length 0x0 set address 2 usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x5, requesttype: 0x0, value 0x2 index 0x0 length 0x0 usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x12 usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x9 usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x27 get_conf_no 0 Result 39, wLength 39 if 0, ep 0 if 0, ep 1 if 0, ep 2 ##EP epmaxpacketin[1] = 64 ##EP epmaxpacketout[2] = 64 ##EP epmaxpacketin[3] = 16 set configuration 1 usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 0x0 new device strings: Mfr=1, Product=2, SerialNumber=3 usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 length 0xFF USB device number 2 default language ID 0x409 usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x409 length 0xFF usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x302 index 0x409 length 0xFF usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x303 index 0x409 length 0xFF Manufacturer Modeo Product LAN9512 SerialNumber 00951101 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x2 length 0x4 usb_control_msg: devnum: 0x1, configno: 0x0, irq_act_len 0x0 maxchild 0x3 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x3 length 0x4 2 USB Device(s) found scanning bus for ethernet devices... i=0 smsc95xx probe vend, product:424 9512 i=1 smsc95xx probe vend, product:424 EC00 USB Ethernet device detected Endpoints In 1 Out 2 Int 3 smsc95xx get info i=2 1 Ethernet Device(s) found OMAP3 SBC3530 # ping 192.168.2.1 ** smsc95xx_halt() ** smsc95xx_init() usb_control_msg: devnum: 0x2, configno: 0x0, irq_act_len 0x0 maxchild 0x0 usb_control_msg: request: 0xA0, requesttype: 0x40, value 0x0 index 0x14 length 0x4 len:-1 sizeof(data):4 Failed to write HW_CFG_LRST_ bit in HW_CFG register, ret = -1 ** smsc95xx_halt() ping failed; host 192.168.2.1 is not alive -- Mehmet Fatih Özay Yaz?l?m Gelis,tirme / Software Development C Tech Bil. Tek. San ve Tic. A.S,. (C2Tech) TUBITAK TEKSEB C-210 Gebze, Kocaeli, Turkey Tel: +90 262 644 90 48 Fax: +90 262 644 90 47 http://www.ctech.com.tr

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[U-Boot] [BUG] cfi_flash can't work correctly on latest uboot
by Bob Liu 21 Mar '12

21 Mar '12

Hi, folks I think this patch make cfi_flash can't work correctly. http://git.denx.de/?p=u-boot.git;a=commitdiff;h=df4e813b72bf07d9026b00455f5… --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1426,6 +1426,11 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) #endif }; + /* + * Flash needs to be in status register read mode for + * flash_full_status_check() to work correctly + */ + flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); -------------------------------------- without this line, flash can't be recognized. So it's correct here. U-Boot 2011.09-svn2735 (ADI-2012R1-pre) (Nov 02 2011 - 15:05:23) CPU: ADSP bf526-0.0 (Detected Rev: 0.2) (parallel flash boot) Board: ADI BF526 EZ-Board board Support: http://blackfin.uclinux.org/ Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz RAM: 64 MiB Flash: Flash protect timeout at address 20004000 data 1520ff01 Flash protect error at address 20004000 Vpp Low Error. 4 MiB Flash protect timeout at address 20000000 data 1520ff01 Flash protect error at address 20000000 Flash protect timeout at address 20002000 data 1520ff01 Flash protect error at address 20002000 Block locked. Vpp Low Error. Flash protect timeout at address 20004000 data 1520ff01 Flash protect error at address 20004000 Vpp Low Error. Flash protect timeout at address 20006000 data 1520ff01 Flash protect error at address 20006000 Flash protect timeout at address 20008000 data 1520ff01 Flash protect error at address 20008000 Block locked. Vpp Low Error. Flash protect timeout at address 2000a000 data 1520ff01 Flash protect error at address 2000a000 Block locked. Vpp Low Error. Flash protect timeout at address 2000c000 data 1520ff01 Flash protect error at address 2000c000 Vpp Low Error. Flash protect timeout at address 2000e000 data 1520ff01 Flash protect error at address 2000e000 Block Erase Error. -------------------------------------- if ((retcode = flash_full_status_check (info, sector, info->erase_blk_tout, prot ? "protect" : "unprotect")) == 0) { @@ -1975,6 +1980,13 @@ ulong flash_get_size (phys_addr_t base, int banknum) case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: + /* + * Set flash to read-id mode. Otherwise + * reading protected status is not + * guaranteed. + */ + flash_write_cmd(info, sect_cnt, 0, + FLASH_CMD_READ_ID); ---------------------------------------------------------------------------- But with this two lines. flash ops are not correct. I used old uboot version to read out data from flash. Then tftpboot and run with latest uboot version, you can see that the read out data from flash is different. And without set flash to read-id mode here, it works fine. U-Boot 2010.06 (ADI-2010R1-RC2) (Oct 20 2010 - 04:37:34) CPU: ADSP bf526-0.0 (Detected Rev: 0.2) (parallel flash boot) Board: ADI BF526 EZ-Board board Support: http://blackfin.uclinux.org/ Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz RAM: 64 MiB Flash: 4 MiB In: serial Out: serial Err: serial KGDB: [on serial] ready Net: bfin_mac Hit any key to stop autoboot: 0 bfin> bfin> md 0x20100000 20100000: 56190527 0b223987 d60baf4e 2e871c00 '..V.9".N....... 20100010: 00100000 c42c1c00 a86adb94 01021005 ......,...j..... 20100020: 32356662 2e302d36 2e332d30 2d382e30 bf526-0.0-3.0.8- 20100030: 2d494441 31313032 702d3152 732d6572 ADI-2011R1-pre-s 20100040: 00088b1f 00000000 fdc40302 4514780b .............x.E 20100050: 570e38d6 3d33264f 24f48743 0649d303 .8.WO&3=C..$..I. 20100060: 93080932 834e9970 0931141a 648443a0 2...p.N...1..C.d 20100070: e0804212 12048762 56501a34 086bb2f1 .B..b...4.PV..k. 20100080: 66e0888a d9782808 d165049d 75049945 ...f.(x...e.E..u 20100090: 31415041 ba02cba2 aebbb2ae 8093d34b APA1........K... 201000a0: 682f1a8a 9cffceb8 105ceeea 7f7df77d ../h......\.}.}. 201000b0: 3c7cf3df 3aea984f 9d554ea7 4e753aaa ..|<O..:.NU..:uN 201000c0: b1a94e5d b13ae91e cc436dbe 749b42c2 ]N....:..mC..B.t 201000d0: fa449283 2aa2ec29 a82e0846 b7089ae5 ..D.)..*F....... 201000e0: cc1f9dc4 a9920651 113e5122 b1122213 ....Q..."Q>..".. 201000f0: 308f15a9 b6496a6a 12562598 49a8c8af ...0jjI..%V....I bfin> tftpboot 0x1000 u-boot.bin Using bfin_mac device TFTP from server 10.100.4.174; our IP address is 10.100.4.50 Filename 'u-boot.bin'. Load address: 0x1000 Loading: ############### done Bytes transferred = 213828 (34344 hex) bfin> go 0x1000 ## Starting application at 0x00001000 ... U-Boot 2011.09-svn2735 (ADI-2012R1-pre) (Nov 02 2011 - 15:15:05) CPU: ADSP bf526-0.0 (Detected Rev: 0.2) (parallel flash boot) Board: ADI BF526 EZ-Board board Support: http://blackfin.uclinux.org/ Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz RAM: 64 MiB Flash: 4 MiB In: serial Out: serial Err: serial KGDB: [on serial] ready Net: bfin_mac Hit any key to stop autoboot: 0 bfin> md 0x20100000 20100000: 88150020 ffff0001 bfcfffff ffffffff ............... 20100010: ffffffff ffffffff ffffffff ffffffff ................ 20100020: 00520051 00030059 00390000 00000000 Q.R.Y.....9..... 20100030: 00000000 00170000 00850020 00040095 ........ ....... 20100040: 000a0000 00030000 00020000 00160000 ................ 20100050: 00000001 00000000 00070002 00200000 .............. . 20100060: 003e0000 00000000 ffff0001 ffffffff ..>............. 20100070: 0050ffff 00490052 00330031 000300e6 ..P.R.I.1.3..... 20100080: 00000000 00030001 00180000 00010090 ................ 20100090: 00000080 00040003 00040003 00020001 ................ 201000a0: 00070003 00010002 00110000 00000000 ................ 201000b0: 00070002 00200000 00640000 00010000 ...... ...d..... 201000c0: 00060003 00000000 00640001 00010000 ..........d..... 201000d0: 00070003 00110000 00000000 00070001 ................ 201000e0: 00000000 00640001 00010000 ffff0003 ......d......... 201000f0: ffffffff ffffffff ffffffff ffffffff ................ bfin> flinfo Bank # 1: CFI conformant flash (16 x 16) Size: 4 MB in 71 Sectors Intel Standard command set, Manufacturer ID: 0x20, Device ID: 0x8815 Erase timeout: 4096 ms, write timeout: 1 ms Sector Start Addresses: 20000000 RO 20002000 RO 20004000 RO 20006000 RO 20008000 RO 2000A000 RO 2000C000 RO 2000E000 RO 20010000 RO 20020000 RO 20030000 RO 20040000 RO 20050000 RO 20060000 RO 20070000 RO 20080000 RO 20090000 RO 200A0000 RO 200B0000 RO 200C0000 RO 200D0000 RO 200E0000 RO 200F0000 RO 20100000 RO 20110000 RO 20120000 RO 20130000 RO 20140000 RO 20150000 RO 20160000 RO 20170000 RO 20180000 RO 20190000 RO 201A0000 RO 201B0000 RO 201C0000 RO 201D0000 RO 201E0000 RO 201F0000 RO 20200000 RO 20210000 RO 20220000 RO 20230000 RO 20240000 RO 20250000 RO 20260000 RO 20270000 RO 20280000 RO 20290000 RO 202A0000 RO 202B0000 RO 202C0000 RO 202D0000 RO 202E0000 RO 202F0000 RO 20300000 RO 20310000 RO 20320000 RO 20330000 RO 20340000 RO 20350000 RO 20360000 RO 20370000 RO 20380000 RO 20390000 RO 203A0000 RO 203B0000 RO 203C0000 RO 203D0000 RO 203E0000 RO 203F0000 RO bfin> ---------------------------------------------------------------------------- info->protect[sect_cnt] = flash_isset (info, sect_cnt, FLASH_OFFSET_PROTECT, -- Regards, --Bob

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