November 2011 - U-Boot

[U-Boot] [PATCH 1/2] PXA: Add MMC driver using the generic MMC framework
by Marek Vasut 02 Nov '11

02 Nov '11

Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- arch/arm/include/asm/arch-pxa/regs-mmc.h | 155 +++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/pxa_mmc_gen.c | 442 ++++++++++++++++++++++++++++++ 3 files changed, 598 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-pxa/regs-mmc.h create mode 100644 drivers/mmc/pxa_mmc_gen.c diff --git a/arch/arm/include/asm/arch-pxa/regs-mmc.h b/arch/arm/include/asm/arch-pxa/regs-mmc.h new file mode 100644 index 0000000..fd1eb1e --- /dev/null +++ b/arch/arm/include/asm/arch-pxa/regs-mmc.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __REGS_MMC_H__ +#define __REGS_MMC_H__ + +#define MMC0_BASE 0x41100000 +#define MMC1_BASE 0x42000000 + +int pxa_mmc_register(int card_index); + +struct pxa_mmc_regs { + uint32_t strpcl; + uint32_t stat; + uint32_t clkrt; + uint32_t spi; + uint32_t cmdat; + uint32_t resto; + uint32_t rdto; + uint32_t blklen; + uint32_t nob; + uint32_t prtbuf; + uint32_t i_mask; + uint32_t i_reg; + uint32_t cmd; + uint32_t argh; + uint32_t argl; + uint32_t res; + uint32_t rxfifo; + uint32_t txfifo; +}; + +/* MMC_STRPCL */ +#define MMC_STRPCL_STOP_CLK (1 << 0) +#define MMC_STRPCL_START_CLK (1 << 1) + +/* MMC_STAT */ +#define MMC_STAT_END_CMD_RES (1 << 13) +#define MMC_STAT_PRG_DONE (1 << 12) +#define MMC_STAT_DATA_TRAN_DONE (1 << 11) +#define MMC_STAT_CLK_EN (1 << 8) +#define MMC_STAT_RECV_FIFO_FULL (1 << 7) +#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6) +#define MMC_STAT_RES_CRC_ERROR (1 << 5) +#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4) +#define MMC_STAT_CRC_READ_ERROR (1 << 3) +#define MMC_STAT_CRC_WRITE_ERROR (1 << 2) +#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1) +#define MMC_STAT_READ_TIME_OUT (1 << 0) + +/* MMC_CLKRT */ +#define MMC_CLKRT_20MHZ 0 +#define MMC_CLKRT_10MHZ 1 +#define MMC_CLKRT_5MHZ 2 +#define MMC_CLKRT_2_5MHZ 3 +#define MMC_CLKRT_1_25MHZ 4 +#define MMC_CLKRT_0_625MHZ 5 +#define MMC_CLKRT_0_3125MHZ 6 + +/* MMC_SPI */ +#define MMC_SPI_EN (1 << 0) +#define MMC_SPI_CS_EN (1 << 2) +#define MMC_SPI_CS_ADDRESS (1 << 3) +#define MMC_SPI_CRC_ON (1 << 1) + +/* MMC_CMDAT */ +#define MMC_CMDAT_SD_4DAT (1 << 8) +#define MMC_CMDAT_MMC_DMA_EN (1 << 7) +#define MMC_CMDAT_INIT (1 << 6) +#define MMC_CMDAT_BUSY (1 << 5) +#define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT) +#define MMC_CMDAT_STREAM (1 << 4) +#define MMC_CMDAT_WRITE (1 << 3) +#define MMC_CMDAT_DATA_EN (1 << 2) +#define MMC_CMDAT_R0 0 +#define MMC_CMDAT_R1 1 +#define MMC_CMDAT_R2 2 +#define MMC_CMDAT_R3 3 + +/* MMC_RESTO */ +#define MMC_RES_TO_MAX_MASK 0x7f + +/* MMC_RDTO */ +#define MMC_READ_TO_MAX_MASK 0xffff + +/* MMC_BLKLEN */ +#define MMC_BLK_LEN_MAX_MASK 0x3ff + +/* MMC_PRTBUF */ +#define MMC_PRTBUF_BUF_PART_FULL (1 << 0) + +/* MMC_I_MASK */ +#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6) +#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5) +#define MMC_I_MASK_CLK_IS_OFF (1 << 4) +#define MMC_I_MASK_STOP_CMD (1 << 3) +#define MMC_I_MASK_END_CMD_RES (1 << 2) +#define MMC_I_MASK_PRG_DONE (1 << 1) +#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0) +#define MMC_I_MASK_ALL 0x7f + + +/* MMC_I_REG */ +#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6) +#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5) +#define MMC_I_REG_CLK_IS_OFF (1 << 4) +#define MMC_I_REG_STOP_CMD (1 << 3) +#define MMC_I_REG_END_CMD_RES (1 << 2) +#define MMC_I_REG_PRG_DONE (1 << 1) +#define MMC_I_REG_DATA_TRAN_DONE (1 << 0) + +/* MMC_CMD */ +#define MMC_CMD_INDEX_MAX 0x6f +#define CMD(x) (x) + +#define MMC_R1_IDLE_STATE 0x01 +#define MMC_R1_ERASE_STATE 0x02 +#define MMC_R1_ILLEGAL_CMD 0x04 +#define MMC_R1_COM_CRC_ERR 0x08 +#define MMC_R1_ERASE_SEQ_ERR 0x01 +#define MMC_R1_ADDR_ERR 0x02 +#define MMC_R1_PARAM_ERR 0x04 + +#define MMC_R1B_WP_ERASE_SKIP 0x0002 +#define MMC_R1B_ERR 0x0004 +#define MMC_R1B_CC_ERR 0x0008 +#define MMC_R1B_CARD_ECC_ERR 0x0010 +#define MMC_R1B_WP_VIOLATION 0x0020 +#define MMC_R1B_ERASE_PARAM 0x0040 +#define MMC_R1B_OOR 0x0080 +#define MMC_R1B_IDLE_STATE 0x0100 +#define MMC_R1B_ERASE_RESET 0x0200 +#define MMC_R1B_ILLEGAL_CMD 0x0400 +#define MMC_R1B_COM_CRC_ERR 0x0800 +#define MMC_R1B_ERASE_SEQ_ERR 0x1000 +#define MMC_R1B_ADDR_ERR 0x2000 +#define MMC_R1B_PARAM_ERR 0x4000 + +#endif /* __REGS_MMC_H__ */ diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 3968c14..59bda49 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o +COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o COBJS-$(CONFIG_SDHCI) += sdhci.o COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c new file mode 100644 index 0000000..aa475e5 --- /dev/null +++ b/drivers/mmc/pxa_mmc_gen.c @@ -0,0 +1,442 @@ +/* + * Copyright (C) 2010 Marek Vasut <marek.vasut(a)gmail.com> + * + * Loosely based on the old code and Linux's PXA MMC driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> + +#include <mmc.h> +#include <asm/errno.h> +#include <asm/arch/hardware.h> +#include <asm/arch/regs-mmc.h> +#include <asm/io.h> + +/* PXAMMC Generic default config for various CPUs */ +#if defined(CONFIG_PXA250) +#define PXAMMC_FIFO_SIZE 1 +#define PXAMMC_MIN_SPEED 312500 +#define PXAMMC_MAX_SPEED 20000000 +#define PXAMMC_HOST_CAPS (0) +#elif defined(CONFIG_PXA27X) +#define PXAMMC_CRC_SKIP +#define PXAMMC_FIFO_SIZE 32 +#define PXAMMC_MIN_SPEED 304000 +#define PXAMMC_MAX_SPEED 19500000 +#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT) +#elif defined(CONFIG_CPU_MONAHANS) +#define PXAMMC_FIFO_SIZE 32 +#define PXAMMC_MIN_SPEED 304000 +#define PXAMMC_MAX_SPEED 26000000 +#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS) +#else +#error "This CPU isn't supported by PXA MMC!" +#endif + +#define MMC_STAT_ERRORS \ + (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN | \ + MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE | \ + MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR) + +/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */ +#define PXA_MMC_TIMEOUT 100 + +struct pxa_mmc_priv { + struct pxa_mmc_regs *regs; +}; + +/* Wait for bit to be set */ +static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) +{ + struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_regs *regs = priv->regs; + unsigned int timeout = PXA_MMC_TIMEOUT; + + /* Wait for bit to be set */ + while (--timeout) { + if (readl(&regs->stat) & mask) + break; + udelay(10); + } + + if (!timeout) + return -ETIMEDOUT; + + return 0; +} + +static int pxa_mmc_stop_clock(struct mmc *mmc) +{ + struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_regs *regs = priv->regs; + unsigned int timeout = PXA_MMC_TIMEOUT; + + /* If the clock aren't running, exit */ + if (!(readl(&regs->stat) & MMC_STAT_CLK_EN)) + return 0; + + /* Tell the controller to turn off the clock */ + writel(MMC_STRPCL_STOP_CLK, &regs->strpcl); + + /* Wait until the clock are off */ + while (--timeout) { + if (!(readl(&regs->stat) & MMC_STAT_CLK_EN)) + break; + udelay(10); + } + + /* The clock refused to stop, scream and die a painful death */ + if (!timeout) + return -ETIMEDOUT; + + /* The clock stopped correctly */ + return 0; +} + +static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + uint32_t cmdat) +{ + struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_regs *regs = priv->regs; + int ret; + + /* The card can send a "busy" response */ + if (cmd->flags & MMC_RSP_BUSY) + cmdat |= MMC_CMDAT_BUSY; + + /* Inform the controller about response type */ + switch (cmd->resp_type) { + case MMC_RSP_R1: + case MMC_RSP_R1b: + cmdat |= MMC_CMDAT_R1; + break; + case MMC_RSP_R2: + cmdat |= MMC_CMDAT_R2; + break; + case MMC_RSP_R3: + cmdat |= MMC_CMDAT_R3; + break; + default: + break; + } + + /* Load command and it's arguments into the controller */ + writel(cmd->cmdidx, &regs->cmd); + writel(cmd->cmdarg >> 16, &regs->argh); + writel(cmd->cmdarg & 0xffff, &regs->argl); + writel(cmdat, &regs->cmdat); + + /* Start the controller clock and wait until they are started */ + writel(MMC_STRPCL_START_CLK, &regs->strpcl); + + ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN); + if (ret) + return ret; + + /* Correct and happy end */ + return 0; +} + +static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) +{ + struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_regs *regs = priv->regs; + uint32_t a, b, c; + int i; + int stat; + + /* Read the controller status */ + stat = readl(&regs->stat); + + /* + * Linux says: + * Did I mention this is Sick. We always need to + * discard the upper 8 bits of the first 16-bit word. + */ + a = readl(&regs->res) & 0xffff; + for (i = 0; i < 4; i++) { + b = readl(&regs->res) & 0xffff; + c = readl(&regs->res) & 0xffff; + cmd->response[i] = (a << 24) | (b << 8) | (c >> 8); + a = c; + } + + /* The command response didn't arrive */ + if (stat & MMC_STAT_TIME_OUT_RESPONSE) + return -ETIMEDOUT; + else if (stat & MMC_STAT_RES_CRC_ERROR && cmd->flags & MMC_RSP_CRC) { +#ifdef PXAMMC_CRC_SKIP + if (cmd->flags & MMC_RSP_136 && cmd->response[0] & (1 << 31)) + printf("Ignoring CRC, this may be dangerous!\n"); + else +#endif + return -EILSEQ; + } + + /* The command response was successfully read */ + return 0; +} + +static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) +{ + struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_regs *regs = priv->regs; + uint32_t len; + uint32_t *buf = (uint32_t *)data->dest; + int size; + int ret; + + len = data->blocks * data->blocksize; + + while (len) { + /* The controller has data ready */ + if (readl(&regs->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) { + size = min(len, PXAMMC_FIFO_SIZE); + len -= size; + size /= 4; + + /* Read data into the buffer */ + while (size--) + *buf++ = readl(&regs->rxfifo); + + } + + if (readl(&regs->stat) & MMC_STAT_ERRORS) + return -EIO; + } + + /* Wait for the transmission-done interrupt */ + ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE); + if (ret) + return ret; + + return 0; +} + +static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) +{ + struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_regs *regs = priv->regs; + uint32_t len; + uint32_t *buf = (uint32_t *)data->src; + int size; + int ret; + + len = data->blocks * data->blocksize; + + while (len) { + /* The controller is ready to receive data */ + if (readl(&regs->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) { + size = min(len, PXAMMC_FIFO_SIZE); + len -= size; + size /= 4; + + while (size--) + writel(*buf++, &regs->txfifo); + + if (min(len, PXAMMC_FIFO_SIZE) < 32) + writel(MMC_PRTBUF_BUF_PART_FULL, &regs->prtbuf); + } + + if (readl(&regs->stat) & MMC_STAT_ERRORS) + return -EIO; + } + + /* Wait for the transmission-done interrupt */ + ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE); + if (ret) + return ret; + + /* Wait until the data are really written to the card */ + ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE); + if (ret) + return ret; + + return 0; +} + +static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_regs *regs = priv->regs; + uint32_t cmdat = 0; + int ret; + + /* Stop the controller */ + ret = pxa_mmc_stop_clock(mmc); + if (ret) + return ret; + + /* If we're doing data transfer, configure the controller accordingly */ + if (data) { + writel(data->blocks, &regs->nob); + writel(data->blocksize, &regs->blklen); + /* This delay can be optimized, but stick with max value */ + writel(0xffff, &regs->rdto); + cmdat |= MMC_CMDAT_DATA_EN; + if (data->flags & MMC_DATA_WRITE) + cmdat |= MMC_CMDAT_WRITE; + } + + /* Run in 4bit mode if the card can do it */ + if (mmc->bus_width == 4) + cmdat |= MMC_CMDAT_SD_4DAT; + + /* Execute the command */ + ret = pxa_mmc_start_cmd(mmc, cmd, cmdat); + if (ret) + return ret; + + /* Wait until the command completes */ + ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES); + if (ret) + return ret; + + /* Read back the result */ + ret = pxa_mmc_cmd_done(mmc, cmd); + if (ret) + return ret; + + /* In case there was a data transfer scheduled, do it */ + if (data) { + if (data->flags & MMC_DATA_WRITE) + pxa_mmc_do_write_xfer(mmc, data); + else + pxa_mmc_do_read_xfer(mmc, data); + } + + return 0; +} + +static void pxa_mmc_set_ios(struct mmc *mmc) +{ + struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_regs *regs = priv->regs; + uint32_t tmp; + uint32_t pxa_mmc_clock; + + if (!mmc->clock) { + pxa_mmc_stop_clock(mmc); + return; + } + + /* PXA3xx can do 26MHz with special settings. */ + if (mmc->clock == 26000000) { + writel(0x7, &regs->clkrt); + return; + } + + /* Set clock to the card the usual way. */ + pxa_mmc_clock = 0; + tmp = mmc->f_max / mmc->clock; + tmp += tmp % 2; + + while (tmp > 1) { + pxa_mmc_clock++; + tmp >>= 1; + } + + writel(pxa_mmc_clock, &regs->clkrt); +} + +static int pxa_mmc_init(struct mmc *mmc) +{ + struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_regs *regs = priv->regs; + + /* Make sure the clock are stopped */ + pxa_mmc_stop_clock(mmc); + + /* Turn off SPI mode */ + writel(0, &regs->spi); + + /* Set up maximum timeout to wait for command response */ + writel(MMC_RES_TO_MAX_MASK, &regs->resto); + + /* Mask all interrupts */ + writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ), + &regs->i_mask); + return 0; +} + +int pxa_mmc_register(int card_index) +{ + struct mmc *mmc; + struct pxa_mmc_priv *priv; + uint32_t reg; + int ret = -ENOMEM; + + mmc = malloc(sizeof(struct mmc)); + if (!mmc) + goto err0; + + priv = malloc(sizeof(struct pxa_mmc_priv)); + if (!priv) + goto err1; + + switch (card_index) { + case 0: + priv->regs = (struct pxa_mmc_regs *)MMC0_BASE; + break; + case 1: + priv->regs = (struct pxa_mmc_regs *)MMC1_BASE; + break; + default: + printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n", + card_index); + goto err2; + } + + mmc->priv = priv; + + sprintf(mmc->name, "PXA MMC"); + mmc->send_cmd = pxa_mmc_request; + mmc->set_ios = pxa_mmc_set_ios; + mmc->init = pxa_mmc_init; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->f_max = PXAMMC_MAX_SPEED; + mmc->f_min = PXAMMC_MIN_SPEED; + mmc->host_caps = PXAMMC_HOST_CAPS; + + mmc->b_max = 0; + +#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */ + reg = readl(CKEN); + reg |= CKEN12_MMC; + writel(reg, CKEN); +#else /* PXA3xx */ + reg = readl(CKENA); + reg |= CKENA_12_MMC0 | CKENA_13_MMC1; + writel(reg, CKENA); +#endif + + mmc_register(mmc); + + return 0; + +err2: + free(priv); +err1: + free(mmc); +err0: + return ret; +} -- 1.7.5.4

2 9

[U-Boot] [PATCH] at91: Add support for Bluewater Systems Snapper 9G45 module
by Simon Glass 02 Nov '11

02 Nov '11

Snapper 9G45 is a ARM9-based CPU module with 1GB NAND and 128MB DDR SDRAM. This patch includes NAND and Ethernet support. Signed-off-by: Simon Glass <sglass(a)bluewatersys.com> --- board/bluewater/snapper9g45/Makefile | 43 +++++++ board/bluewater/snapper9g45/snapper9g45.c | 155 +++++++++++++++++++++++ boards.cfg | 1 + include/configs/snapper9g45.h | 189 +++++++++++++++++++++++++++++ 4 files changed, 388 insertions(+), 0 deletions(-) create mode 100644 board/bluewater/snapper9g45/Makefile create mode 100644 board/bluewater/snapper9g45/snapper9g45.c create mode 100644 include/configs/snapper9g45.h diff --git a/board/bluewater/snapper9g45/Makefile b/board/bluewater/snapper9g45/Makefile new file mode 100644 index 0000000..9016e5a --- /dev/null +++ b/board/bluewater/snapper9g45/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += snapper9g45.o + +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bluewater/snapper9g45/snapper9g45.c b/board/bluewater/snapper9g45/snapper9g45.c new file mode 100644 index 0000000..f057e59 --- /dev/null +++ b/board/bluewater/snapper9g45/snapper9g45.c @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2011 Bluewater Systems Ltd + * Author: Andre Renaud <andre(a)bluewatersys.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9g45_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hardware.h> +#include <i2c.h> +#include <net.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void macb_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; + + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PA15) => PHY normal mode (not Test mode) / CRSDV + * ERX0 (PA12) => PHY ADDR0 / RXD0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 / RXD1 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13), + &pioa->pudr); + + /* Need to reset PHY -> 500ms reset */ + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + + /* The phy internal reset take 21ms */ + udelay(21 * 1000); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13), + &pioa->puer); + + at91_macb_hw_init(); +} + +static void nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 as NAND/SmartMedia */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} + +int board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable PIO clocks */ + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC | + (1 << ATMEL_ID_PIODE)), &pmc->pcer); + + gd->bd->bi_arch_number = MACH_TYPE_SNAPPER9G45; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Initialise peripherals */ + at91_seriald_hw_init(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + nand_hw_init(); + + macb_hw_init(); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x1b); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} diff --git a/boards.cfg b/boards.cfg index 738c186..b56f1d0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -95,6 +95,7 @@ at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 +snapper9g45 arm arm926ejs snapper9g45 bluewater at91 snapper9g45:AT91SAM9G45 sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM tny_a9g20_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h new file mode 100644 index 0000000..23798c3 --- /dev/null +++ b/include/configs/snapper9g45.h @@ -0,0 +1,189 @@ +/* + * Bluewater Systems Snapper 9G45 modules + * + * (C) Copyright 2011 Bluewater Systems + * Author: Andre Renaud <andre(a)bluewatersys.com> + * Author: Ryan Mallon <ryan(a)bluewatersys.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* SoC type is defined in boards.cfg */ +#include <asm/hardware.h> +#include <asm/sizes.h> + +#define CONFIG_SYS_TEXT_BASE 0x70000000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 + +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_FIT + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 128MB */ +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +/* Mem test settings */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /*0x40000000*/ +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_TFTP_PORT +#define CONFIG_TFTP_TSIZE + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE + +/* GPIOs and IO expander */ +#define CONFIG_AT91_LEGACY +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 + +#ifndef NEW +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } +#endif + +/* UARTs/Serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } +#define CONFIG_SYS_PROMPT "Snapper> " + +/* I2C - Bit-bashed */ +#define CONFIG_SOFT_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SOFT_I2C_READ_REPEATED_START +#define CONFIG_I2C_MULTI_BUS +#define I2C_INIT do { \ + at91_set_gpio_output(AT91_PIN_PA21, 1); \ + at91_set_gpio_output(AT91_PIN_PA20, 1); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 21, 1); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 20, 1); \ + } while (0) +#define I2C_SOFT_DECLARATIONS +#define I2C_ACTIVE +#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA20, 1); +#define I2C_READ at91_get_gpio_value(AT91_PIN_PA20); +#define I2C_SDA(bit) do { \ + if (bit) { \ + at91_set_gpio_input(AT91_PIN_PA20, 1); \ + } else { \ + at91_set_gpio_output(AT91_PIN_PA20, 1); \ + at91_set_gpio_value(AT91_PIN_PA20, bit); \ + } \ + } while (0) +#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 21, bit) +#define I2C_DELAY udelay(2) + +/* Boot options */ +#define CONFIG_SYS_LOAD_ADDR 0x71000000 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Environment settings */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (512 << 10) +#define CONFIG_ENV_SIZE (256 << 10) +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BOOTARGS "console=ttyS0,115200 ip=any" + +/* Console settings */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_EXTBDINFO +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* U-Boot memory settings */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) +#define CONFIG_STACKSIZE (256 << 10) + +/* Command line configuration */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_GPIO +#define CONFIG_CMD_USB +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND + +#endif -- 1.7.5.4

4 5

[U-Boot] [PATCH 0/2] LaCie 2Big Network v2 support
by Simon Guinot 02 Nov '11

02 Nov '11

From: Simon Guinot <simon.guinot(a)sequanux.org> This patch series provides support for the LaCie NAS 2Big Network v2. Simon Guinot (2): mvsata: fix ide_preinit for missing disks ARM: add support for LaCie 2Big Network v2 MAINTAINERS | 1 + board/LaCie/net2big_v2/Makefile | 49 +++++++++ board/LaCie/net2big_v2/kwbimage.cfg | 162 ++++++++++++++++++++++++++++++ board/LaCie/net2big_v2/net2big_v2.c | 188 +++++++++++++++++++++++++++++++++++ board/LaCie/net2big_v2/net2big_v2.h | 43 ++++++++ boards.cfg | 1 + drivers/block/mvsata_ide.c | 14 ++- include/configs/net2big_v2.h | 161 ++++++++++++++++++++++++++++++ 8 files changed, 613 insertions(+), 6 deletions(-) create mode 100644 board/LaCie/net2big_v2/Makefile create mode 100644 board/LaCie/net2big_v2/kwbimage.cfg create mode 100644 board/LaCie/net2big_v2/net2big_v2.c create mode 100644 board/LaCie/net2big_v2/net2big_v2.h create mode 100644 include/configs/net2big_v2.h -- 1.7.5.1

2 5

[U-Boot] Pull request for u-boot-marvell.git
by Prafulla Wadaskar 02 Nov '11

02 Nov '11

Hi Albert Please pull The following changes since commit b3fee4e17f9f2c136b8fcfc1b7e575b6b3ccd66a: Anatolij Gustschin (1): ARM: dreamplug: fix compilation are available in the git repository at: u-boot-marvell.git ..BRANCH.NOT.VERIFIED.. Ajay Bhargav (1): gplugD: Fix for error:MACH_TYPE_SHEEVAD undeclared Holger Brunck (2): arm/km: add variable waitforne to mgcoge3un arm/km/mgcoge3un: enhance "waitforne" feature Michael Walle (1): kirkwood: define CONFIG_SYS_CACHELINE_SIZE Mike Frysinger (1): kirkwood: drop empty asm-offsets.s file arch/arm/include/asm/arch-kirkwood/config.h | 3 ++- board/keymile/km_arm/km_arm.c | 11 ++++++++++- include/configs/gplugd.h | 12 +++++++++++- include/configs/mgcoge3un.h | 2 ++ 4 files changed, 25 insertions(+), 3 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s Regards... Prafulla . . .

2 2

[U-Boot] [PATCH] mmc: mv_sdhci: Fix host version read for Armada100
by Ajay Bhargav 02 Nov '11

02 Nov '11

sdhci_readw does not work for host version read in Armada100 series SoCs. This patch fix this issue by making a sdhci_readl call to get host version. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- drivers/mmc/mv_sdhci.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index f92caeb..c7fd287 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -30,6 +30,7 @@ static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ static char *MVSDH_NAME = "mv_sdh"; + int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) { struct sdhci_host *host = NULL; @@ -48,7 +49,12 @@ int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) mv_ops.write_b = mv_sdhci_writeb; host->ops = &mv_ops; #endif +#ifdef CONFIG_ARMADA100 + /* SDHCI host version read workaround for Armada100 series */ + host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; +#else host->version = sdhci_readw(host, SDHCI_HOST_VERSION); +#endif add_sdhci(host, max_clk, min_clk); return 0; } -- 1.7.0.4

3 3

[U-Boot] Bitte lesen und beantworten mir sehr dringend ... von miss GRACE JACKSON……please read and reply to me very urgently …from miss GRACE JACKSON
by Grace Grace 02 Nov '11

02 Nov '11

Liebste, Ich bin froh, Ihnen zu schreiben, ich hoffe alles ist gut mit dir? Ich nahm mir vor, Sie wegen meiner derzeitigen Situation hier Kontakt im Flüchtlingslager, und ich bete, dass Gott das Herz berühren und geben Ihnen die Gnade, mir zu helfen Mein Name ist Miss Grace Jackson Abasi Saitoti, ich bin ein 24 Jahre altes Mädchen, ich war in meinem zweiten Jahr in der Universität Gesundheitswissenschaften, bevor das Problem in diesem Land begann, bin ich aus Nairobi in Kenia, aber jetzt bin ich mit Wohnsitz in einem Flüchtlingslager in Burkina Faso mein Vater seligen Angedenkens nach Name verstorbenen Mr. Jackson Abasi Saitoti, der Sektionsleiter mit Dalbit Petroleum in Nairobi, Kenia, war mein geliebter Vater bei lebendigem Leibe verbrannt mit meinem geliebten Mutter und unserem Haus von den Rebellen niedergebrannt an der Seite in den letzten Krise in meinem Land Sie können mehr über den Vorfall durch die folgenden Seiten lesen Sie: http://www.msnbc.msn.com/id/22460182/ns/world_news-africa/t/mob-kills-kenya… nach der Beerdigung meiner Eltern, packte meine Stiefmutter alles, was mein Vater hatte und schickte mich von meiner Familie Haus, und sie behauptete, alles, was mein verstorbener Vater selbst, weil sie kinderlos ist, so schickt sie die Menschen um mich zu töten, weil sie Angst ist, dass ich könnte, um Rache versuchen alle die Bosheit sie mir angetan hat, aber wenn die Mörder mich sah, sie hart Mitleid mit mir und erzählte mir, dass sie in dem von meinem Schritt Mutter schickte mich zu töten, so fragten sie mich, zu leben unser Land Kenia sofort, wenn Ich will leben kurz will ich gerne etwas mehr über mich selbst an Sie weitergeben und sehen, ob Sie mir helfen können, um Ihr Land zu verlagern, um so mit meinem Studium weiter und haben ein neues Leben, und bitte das ist ein wenig abzusondern und flehe ich Sie an Behalt es für dich allein, bis alles richtig angeordnet und ausgeführt wird, dann werde ich kommen, um Sie in Ihrem Land beitreten Ich habe die Summe von 3,8 Millionen Dollar als Erbe von meinem verstorbenen Vater, die Ich mag, um in Ihrem Land mit Ihrer Hilfe investieren will, brauche ich Eure Hilfe, weil mein verstorbener Vater wies die Bank den Fonds um mich zu befreien, im Alter von 24 bis ein Ausländer, der mir helfen kann, den Fonds mit Bedacht zu investieren, und es hat mein Vater den Wunsch für mich in einem fremden Land zu leben, so die Bank nicht frei den Fonds für mich ohne die Hilfe eines Ausländers, wie mein Vater wies die Bank Dieser Fonds ist in meinem verstorbenen Vater das Bankkonto mit einer der Banken hier in Burkina-Faso hinterlegt und ich werde Ihnen alle Details / Kontakt, weil ich das Geld auf Ihr Konto überwiesen werden, bevor ich zu Ihnen kommen kommen wollen in Ihrem Land, Ich brauche Ihre dringende Antwort auf Ihre Fähigkeit, diese für mich das so, dass ich Ihnen sagen, der nächste Schritt, weil ich zu diesem Flüchtlingslager so schnell wie möglich verlassen wollen, die Lage dieses Ortes sehr schwierig ist, was noch wichtiger ist, ich liebe meine Studien und die Menschen hier sind nicht freundlich, ich bin wirklich Leid an diesem Ort, es zu schmerzhaft ist, aber ich hoffe mit eurer Hilfe, um die Übertragung der Fonds in Ihrem Konto, werde ich ein besseres Leben zu leben so freundlich mir Ihre Bereitschaft, mir zu helfen und ich verspreche, immer nett sein und dir treu, ich werde mich freuen, Sie mit 25% des gesamten Fonds für die Hilfe zu kompensieren, und Sie können mir auch helfen, den Fonds zu investieren während meines Studiums, weil ich Arzt werden will fortfahren, ist es mein Wunsch, einen positiven Beitrag für die Menschheit Ich schicke Ihnen mein Foto und ich hoffe, Ihnen und Ihrer Telefonnummer, damit wir per Telefon sprechen kann und ich werde auch gerne deine Stimme hören Vielen Dank und Gott segne Sie Mit freundlichen Grüßen, GRACE ENGLISH................................................. Dearest, I am glad to write to you, I hope everything is well with you? I made up my mind to contact you because of my present situation here in the refugee camp, and I pray that God will touch your heart and give you the grace to help me My name is Miss GRACE Jackson Abasi Saitoti, I am a 24 years old girl, I was in my second year in the university health science before the problem in the country started, I am from Nairobi in Kenya, but I am now residing in a refugee camp in Burkina Faso my father of blessed memory by name late Mr. Jackson Abasi Saitoti who was the section manager with Dalbit Petroleum at Nairobi, Kenya, my beloved father was burnt alive along side with my beloved mother and our family house burnt down by the rebels during the last crisis in my country You can read more about the incident through the below site: http://www.msnbc.msn.com/id/22460182/ns/world_news-africa/t/mob-kills-kenya… after the burial of my parents, my step mother seized everything my father had and sent me out of my family house, and she claimed everything my late father own because she is childless, so she send people to kill me because she is afraid that I might try to revenge all the wickedness she did to me, but when the killers saw me, they hard pity on me and told me that they where sent by my step mother to kill me, so they asked me to live our country Kenya immediately if I want to live briefly i will like to disclose little more about myself to you and see if you can help me to relocate to your country so as to continue with my studies and have a new life, and please this is a little secrete and i plead with you to keep it to yourself alone until everything is properly arranged and executed, then i will come over to join you in your country i have the sum of $3.8 Million as an inheritance from my late father which i will like to invest in your country with your help, i need your help because my late father instructed the bank to release the fund to me at the age of 24 through a foreigner who can help me to invest the fund wisely, and it has been my father's desire for me to live in a foreign country, so the bank will not release the fund to me without the help of a foreigner as my father instructed the bank this fund is deposited in my late father's bank account with one of the banks here in Burkina-Faso and i am going to give you all the details / contact because i want the money to be transferred to your account before i come over to join you in your country, i need your urgent answer of your ability to handle this for me so that i will tell you the next step because i want to leave this refugee camp as soon as possible, the situation of this place is very difficult, more importantly, i love my studies and people here are not friendly, i am really suffering in this place, it is too painful, but i hope with your help to transferring the fund in your account, i will have a better life to live so kindly let me know your readiness to help me and i promise to always be nice and faithful to you, I will be glad to compensate you with 25% of the total fund for helping me, and you can also help me to invest the fund while I continue my studies because I want to be a doctor, it is my desire to contribute positively to humanity i will send you my photo and i hope to have yours and your phone number so that we can talk through phone and i will also like to hear your voice thank you and God bless you sincerely yours, GRACE

1 0

[U-Boot] Hello
by Sonia Geddi 01 Nov '11

01 Nov '11

Hello It is with profound respect and humble submission, I beg to state the following few lines for your kind consideration. I hope you will spare some of your valuable minutes to read the following appeal with sympathetic mind. I must confess that it is with great hope, joy and enthusiasm to write you this mail and I believe by the faith that it must surely find you in good condition of health. My name is Sonia Geddi Abdi Gadid, Somalian citizen, female, age 23 years old. I`m the daughter of Late Hon. Geddi Abdi Gadid, a former Somali member of the Transitional Federal Parliament. My father was among the four(4) lawmakers who were killed in a bomb attack on Tuesday 24 August 2010, by the Islamist rebel group Al Shabaab. I lost my mother long time ago, when I was just 6 years old and since then, my father loved me so dearly may he rest in peace and may the great God give him a safe entry in Paradise. Amen. Before the death of my father, he told me that he made a fixed deposit of the sum of Five Million, Eight Hundred thousand United States Dollars(5.8Million USD) in one of the Banks in Burkina Faso with my name as his next of kin. I have traveled to Burkina Faso to clear the money but the Bank manager told me that my refugee status is not authorized by the laws of Burkina Faso to clear the money. He advised me to appoint a trustee. Now, I am Soliciting your help for transfer of the money into your bank account and investment assistance in your Country. I have suffered lots of set back as a result of my parents death. I left Somalia because of incessant family feuds. Presently, I am living in Ouagadougou,Burkina Faso. Hence, I want to settle abroad to continue my studies and spend the rest of my life. Please consider my request as my life is being hugely affected . Thanks a lot in anticipation of your prompt response. Yours sincerely, Sonia Geddi Abdi.

1 0

[U-Boot] This letter is for you
by Jule Bonue 01 Nov '11

01 Nov '11

Good Day!!! I know this message will get to you as a suprise, It is born out of Confidence Honest and Trust, My Names are Dir. Jule BONUE, The Regional Managing Director, I am contacting you to stand for a dormant account worth the sum of €9.500.000.00 in our bank. The part of the fund, shall be used to help the orphanages home around the world If you are interested send the below information for more details and clerification. Full Name................. Nationality............... Occupation................ Address................... Telephone number............... Age......................... Your urgent reply is needed. Thank Mr Jule Bonue The Regional Managing Director Coris Bank International Ouagadougou-Burkina Faso Tel: +226 758 65977

1 0

[U-Boot] [PATCH v5 00/11] arm, davinci: add support for dm368 based cam_enc_4xx board
by Heiko Schocher 01 Nov '11

01 Nov '11

This is a repost of the cam_enc_4xx board support patches from http://lists.denx.de/pipermail/u-boot/2011-October/106692.html changes for v5: - rebase against TOT ce5207e191c59b3135303fd03b98dd2ac3701ba2 - add comment from Christian Riesch: use lpsc_on() and lpsc_syncreset(), remove dm365_lpc_transition() patches http://patchwork.ozlabs.org/patch/114942/ http://patchwork.ozlabs.org/patch/119375/ needed for this. Patches are checkpatch clean "./MAKEALL -a arm --soc davinci" compiles clean with patch: http://patchwork.ozlabs.org/patch/122348/ Also needed patches: [U-Boot] net, davinci_emac: fix compiler error http://patchwork.ozlabs.org/patch/122348/ arm, arm926: fix missing symbols in NAND_SPL mode http://patchwork.ozlabs.org/patch/104942/ arm, davinci: replace CONFIG_PRELOADER with CONFIG_SPL_BUILD http://patchwork.ozlabs.org/patch/106983/ [U-Boot,v2,2/3] arm, davinci: Add function lpsc_syncreset() http://patchwork.ozlabs.org/patch/119375/ Albert? Maybe this patchset has a chance to go now in mainline? It is pending now since Sat Jul 16 12:06:41 CEST 2011, see: http://lists.denx.de/pipermail/u-boot/2011-July/096302.html Cc: Sandeep Paulraj <s-paulraj(a)ti.com> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Heiko Schocher (11): usb, davinci: add enable_vbus() weak function arm, usb, davinci: make USBPHY_CTL register configurable net, davinci_emac: make clock divider in MDIO control register configurable spl: add option for adding post memory test to the SPL framework arm, davinci: add support for new spl framework spl, nand: add 4bit HW ecc oob first nand_read_page function arm, davinci: add header files for dm365 arm, davinci: add lowlevel function for dm365 soc arm926ejs, davinci: add cpuinfo for dm365 arm926ejs, davinci: add missing spi defines for dm365 arm, davinci: add cam_enc_4xx support MAINTAINERS | 1 + Makefile | 8 +- README | 5 + arch/arm/cpu/arm926ejs/davinci/Makefile | 8 + arch/arm/cpu/arm926ejs/davinci/cpu.c | 27 ++- arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c | 439 +++++++++++++++++++ arch/arm/cpu/arm926ejs/davinci/spl.c | 63 +++ arch/arm/cpu/arm926ejs/davinci/spl_nand.c | 57 +++ arch/arm/cpu/arm926ejs/start.S | 25 +- arch/arm/include/asm/arch-davinci/aintc_defs.h | 50 +++ arch/arm/include/asm/arch-davinci/dm365_lowlevel.h | 41 ++ arch/arm/include/asm/arch-davinci/hardware.h | 15 + arch/arm/include/asm/arch-davinci/pll_defs.h | 84 ++++ arch/arm/include/asm/arch-davinci/psc_defs.h | 86 ++++ arch/arm/include/asm/arch-davinci/syscfg_defs.h | 66 +++ board/ait/cam_enc_4xx/Makefile | 46 ++ board/ait/cam_enc_4xx/cam_enc_4xx.c | 446 +++++++++++++++++++ board/ait/cam_enc_4xx/config.mk | 15 + board/ait/cam_enc_4xx/u-boot-spl.lds | 73 ++++ board/ait/cam_enc_4xx/ublimage.cfg | 48 ++ boards.cfg | 1 + doc/README.SPL | 1 + doc/README.davinci.nand_spl | 141 ++++++ drivers/mtd/nand/nand_spl_simple.c | 43 ++- drivers/net/davinci_emac.c | 9 +- drivers/usb/musb/davinci.c | 18 +- include/configs/cam_enc_4xx.h | 452 ++++++++++++++++++++ spl/Makefile | 1 + tools/ublimage.h | 2 +- 29 files changed, 2261 insertions(+), 10 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl.c create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_nand.c create mode 100644 arch/arm/include/asm/arch-davinci/aintc_defs.h create mode 100644 arch/arm/include/asm/arch-davinci/dm365_lowlevel.h create mode 100644 arch/arm/include/asm/arch-davinci/pll_defs.h create mode 100644 arch/arm/include/asm/arch-davinci/psc_defs.h create mode 100644 arch/arm/include/asm/arch-davinci/syscfg_defs.h create mode 100644 board/ait/cam_enc_4xx/Makefile create mode 100644 board/ait/cam_enc_4xx/cam_enc_4xx.c create mode 100644 board/ait/cam_enc_4xx/config.mk create mode 100644 board/ait/cam_enc_4xx/u-boot-spl.lds create mode 100644 board/ait/cam_enc_4xx/ublimage.cfg create mode 100644 doc/README.davinci.nand_spl create mode 100644 include/configs/cam_enc_4xx.h -- 1.7.6.4

5 18

[U-Boot] [PATCH 0/5] HWW-1U-1A: e1000 driver cleanups and new features
by Kyle Moffett 01 Nov '11

01 Nov '11

This is a reposted patch series from several months that enhances the e1000 driver in U-Boot to support the Intel 82571EB and provides several new features for the board manufacturing process. Based on prior review, the EEPROM programming and SPI code has been moved into a separate file, "e1000_spi.c", and it calls a few exported functions in the main e1000.c file to coordinate EEPROM access. Comments, critiques, and compliments are highly appreciated. Cheers, Kyle Moffett -- Curious about my work on the Debian powerpcspe port? I'm keeping a blog here: http://pureperl.blogspot.com/

6 24