November 2011 - U-Boot

Re: [U-Boot] (no subject)
by Nokia XMAS Bonanza 14 Nov '11

14 Nov '11

You have emerge the beneficiary of 750,000.00 GBP in Nokia End Of Year Bonanza send your name and address.

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[U-Boot] [PATCH] Improve Power Management in SMC911X driver.
by Bertrand Cachet 14 Nov '11

14 Nov '11

>From datasheet, when READY bit is set inside PM_CTRL register, it means that device is already in *normal* (D0) mode => it doesn't need to be wake-up. With this patch, we only wake-up (writing on TEST_BYTE register) if PM_MODE bits of PM_CTRL register is in D1/D2 mode. Signed-off-by: Bertrand Cachet <bertrand.cachet(a)heig-vd.ch> --- drivers/net/smc911x.h | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index 8ce08a9..258b9b6 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h @@ -471,8 +471,10 @@ static void smc911x_reset(struct eth_device *dev) { int timeout; - /* Take out of PM setting first */ - if (smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) { + /* Take out of PM setting first */ + /* If PMT_CTRL_READY bit is set to 1b => power management is + already ready */ + if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) { /* Write to the bytetest will take out of powerdown */ smc911x_reg_write(dev, BYTE_TEST, 0x0); -- 1.7.5.4

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[U-Boot] OPEN THE ATTACHMENT AND READ THE INHERITANCE CLAIMS LETTER.....
by INHERITANCE CLAIMS DEPT. 14 Nov '11

14 Nov '11

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[U-Boot] [PATCH v2] AT91: pio: Add PIO3 features
by Hong Xu 14 Nov '11

14 Nov '11

This patch adds the support for new PIO controller introduced by some AT91 SoCs. New features include * More peripheral multiplexing * Pull-down, Schmitt trigger, Debouncer * More irq trigger mode (may be not interesting in U-Boot) Signed-off-by: Hong Xu <hong.xu(a)atmel.com> --- - Correct register group definitions - ATMEL_CPU_HAS_PIO3 -> CONFIG_CPU_HAS_PIO3 arch/arm/include/asm/arch-at91/at91_pio.h | 48 ++++++++++- drivers/gpio/at91_gpio.c | 130 +++++++++++++++++++++++++++- 2 files changed, 171 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 416cabf..90a3ad6 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -4,6 +4,7 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People * Copyright (C) 2009 Jens Scharsig (js_at_ng(a)scharsoft.de) + * Copyright (C) 2011 Hong Xu (hong.xu(a)atmel.com) * * Parallel I/O Controller (PIO) - System peripherals registers. * Based on AT91RM9200 datasheet revision E. @@ -17,7 +18,6 @@ #ifndef AT91_PIO_H #define AT91_PIO_H - #define AT91_ASM_PIO_RANGE 0x200 #define AT91_ASM_PIOC_ASR \ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) @@ -66,14 +66,51 @@ typedef struct at91_port { u32 puer; /* 0x64 Pull-up Enable Register */ u32 pusr; /* 0x68 Pad Pull-up Status Register */ u32 reserved4; +#if defined(CONFIG_CPU_HAS_PIO3) + u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ + u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ + u32 reserved5[2]; + u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ + u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ + u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ + u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ +#define PIO_SCDR_DIV_MASK (0x3fff << 0) /* Slow Clock Divider Mask */ + u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ + u32 ppder; /* 0x94 Pad Pull-down Enable Register */ + u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ + u32 reserved6; +#else u32 asr; /* 0x70 Select A Register */ u32 bsr; /* 0x74 Select B Register */ u32 absr; /* 0x78 AB Select Status Register */ u32 reserved5[9]; /* */ +#endif u32 ower; /* 0xA0 Output Write Enable Register */ u32 owdr; /* 0xA4 Output Write Disable Register */ - u32 owsr; /* OxA8 utput Write Status Register */ + u32 owsr; /* OxA8 Output Write Status Register */ +#if defined(CONFIG_CPU_HAS_PIO3) + u32 reserved7; /* */ + u32 aimer; /* Additional Interrupt Modes Enable Register*/ + u32 aimdr; /* Additional Interrupt Modes Disable Register*/ + u32 aimmr; /* Additional Intterupt Modes Mask Register */ + u32 reserved8; /* */ + u32 esr; /* 0xC0 Edge Select Register */ + u32 lsr; /* 0xC4 Level Select Register */ + u32 elsr; /* 0xC8 Edge/Level Status Register */ + u32 reserved9; /* 0xCC */ + u32 fellsr; /* 0xD0 Falling Edge/Low Level Select Register*/ + u32 rehlsr; /* 0xD4 Rising Edge/High Level Select Register*/ + u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ + u32 reserved10; /* */ + u32 locksr; /* 0xE0 Lock Status */ + u32 wpmr; /* 0xE4 Write Protect Mode Register */ + u32 wpsr; /* 0xE4 Write Protect Status Register */ + u32 reserved11[5]; /* */ + u32 schmitt; /* 0x100 Schmitt Trigger Register */ + u32 reserved12[63]; +#else u32 reserved6[85]; +#endif } at91_port_t; typedef union at91_pio { @@ -94,6 +131,13 @@ typedef union at91_pio { #ifdef CONFIG_AT91_GPIO int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); +#if defined(CONFIG_CPU_HAS_PIO3) +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); +int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); +#endif int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); int at91_set_pio_output(unsigned port, unsigned pin, int value); diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index be2a026..d85f3e3 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -1,6 +1,8 @@ /* * Memory Setup stuff - taken from blob memsetup.S * + * Copyright (C) 2011 Hong Xu (hong.xu(a)atmel.com) + * * Copyright (C) 2009 Jens Scharsig (js_at_ng(a)scharsoft.de) * * Copyright (C) 2005 HP Labs @@ -58,7 +60,7 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) } /* - * mux the pin to the "GPIO" peripheral role. + * mux the pin to the "GPIO" peripheral function. */ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) { @@ -75,7 +77,7 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) } /* - * mux the pin to the "A" internal peripheral role. + * mux the pin to the "A" internal peripheral function. */ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) { @@ -86,14 +88,21 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(CONFIG_CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].asr); +#endif writel(mask, &pio->port[port].pdr); } return 0; } /* - * mux the pin to the "B" internal peripheral role. + * mux the pin to the "B" internal peripheral function. */ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) { @@ -104,13 +113,120 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(CONFIG_CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].bsr); +#endif + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +#if defined(CONFIG_CPU_HAS_PIO3) +/* + * mux the pin to the "C" internal peripheral function. + */ +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); writel(mask, &pio->port[port].pdr); } return 0; } /* + * mux the pin to the "D" internal peripheral function. + */ +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +/* + * enable/disable the debounce filter. + */ +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (is_on) { + writel(1 << pin, &pio->port[port].ifscer); + writel(div & PIO_SCDR_DIV_MASK, &pio->port[port].scdr); + writel(1 << pin, &pio->port[port].ifer); + } else { + writel(1 << pin, &pio->port[port].ifdr); + } + } + return 0; +} + +/* + * enable/disable the pull-down. + * If pull-up already enabled while calling the function, we disable it. + */ +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_pulldown) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + writel(1 << pin, &pio->port[port].pudr); + if (is_pulldown) + writel(1 << pin, &pio->port[port].ppder); + else + writel(1 << pin, &pio->port[port].ppddr); + } + return 0; +} + +/* + * Set Schmitt trigger mode + */ +int at91_set_pio_schmitt_trig(unsigned port, unsigned pin, int is_enabled) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 data; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + data = readl(&pio->port[port].schmitt); + if (is_enabled) + data &= ~(1 << pin); + else + data |= (1 << pin); + writel(data, &pio->port[port].schmitt); + } + return 0; +} +#endif + +/* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and * configure it for an input. */ @@ -162,10 +278,14 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; - if (is_on) + if (is_on) { +#if defined(CONFIG_CPU_HAS_PIO3) + writel(mask, &pio->port[port].ifscdr); +#endif writel(mask, &pio->port[port].ifer); - else + } else { writel(mask, &pio->port[port].ifdr); + } } return 0; } -- 1.7.3.3

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[U-Boot] Using Micron (Numonyx) m28w640hcb with u-boot
by Gudjon I. Gudjonsson 14 Nov '11

14 Nov '11

Hi list I have replaced the at49bv642d nor flash memory on my Atmel ngw100 board with the pin compatible m28w640hcb flash memory from Micron (formerly Numonyx). I can program the U-boot to the flash without problems using a JTAG. I can also program the full buildroot Linux system using JTAG and verify the bytes using the md.b command in U-boot. Therefore I assume there is nothing wrong with my hardware. However, I can neither make U-boot nor Linux write to the flash and Linux doesn't boot from the flash. I did start the Linux system from an NFS root and could detect the memory as a read only device in Linux but the /dev/mtdblockX devices did not appear. I have spent a lot of time on the problem without success and I am wondering how to proceed. Hopefully someone spots the problem directly. The spear3xx series boards include the m28w640hct device. I could buy such a board to test but is anyone using that board with U-boot? If so can you please confirm that U-boot can write to the flash? Another idea is to replace the at64bv642 chip with some other NOR-flash, has anyone done that with success? The u-boot debug output can be found below. There are some (null) addresses that don't appear when using the working at49bv642d flash Thanks a lot for any help Gudjon /****************************** U-boot startup *******************************/ U-Boot 2010.06 (Nov 12 2011 - 11:48:36) U-Boot code: (null) -> 00011ae0 data: 00018e38 -> 0004e7b8 VMR table @ 0x11fca684 DMA: Using memory from 0x11f6d000 to 0x11f71000 flash detect cfi fwc addr (null) cmd f0 f0 8bit x 8 bit fwc addr (null) cmd ff ff 8bit x 8 bit fwc addr 00000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr 00000010 is= ff 51 fwc addr 00000555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr 00000010 is= ff 51 fwc addr (null) cmd f0 f0f0 16bit x 8 bit fwc addr (null) cmd ff ffff 16bit x 8 bit fwc addr 000000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr 00000020 is= 0051 5151 fwc addr 00000aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr 00000020 is= 0051 5151 fwc addr (null) cmd f0 00f0 16bit x 16 bit fwc addr (null) cmd ff 00ff 16bit x 16 bit fwc addr 000000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr 00000020 is= 0051 0051 is= cmd 52(R) addr 00000022 is= 0052 0052 is= cmd 59(Y) addr 00000024 is= 0059 0059 device interface is 1 found port 2 chip 2 port 16 bits chip 16 bits 00 : 51 52 59 03 00 35 00 00 00 00 00 27 36 b4 c6 04 QRY..5.....'6... 10 : 04 0a 00 05 05 03 00 17 01 00 03 00 02 07 00 20 ............... 20 : 00 7e 00 00 01 50 52 49 31 30 e6 00 00 11 fb 4e .~...PRI10.....N fwc addr (null) cmd ff 00ff 16bit x 16 bit fwc addr (null) cmd 90 0090 16bit x 16 bit fwc addr (null) cmd ff 00ff 16bit x 16 bit fwc addr 000000aa cmd 98 0098 16bit x 16 bit manufacturer is 3 manufacturer id is 0x20 device id is 0x49 device id2 is 0x0 cfi version is 0x3130 size_ratio 1 port 16 bits chip 16 bits found 2 erase regions erase region 0: 0x00200007 erase_region_count = 8 erase_region_size = 8192 erase region 1: 0x0100007e erase_region_count = 127 erase_region_size = 65536 fwc addr (null) cmd ff 00ff 16bit x 16 bit flash_protect ON: from 0x00000000 to 0x0001AC37 protect on 0 protect on 1 protect on 2 protect on 3 protect on 4 protect on 5 protect on 6 protect on 7 protect on 8 flash_protect ON: from 0x007F0000 to 0x007FFFFF protect on 134 Flash: 8 MiB at address 0x00000000 DRAM Configuration: Bank #0: 10000000 32 MiB *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: macb0, macb1 Press SPACE to abort autoboot in 1 seconds ### JFFS2 loading 'uImage' to 0x10400000 Scanning JFFS2 FS: done. find_inode failed for name=uImage load: Failed to find inode ### JFFS2 LOAD ERROR<0> for uImage! Wrong Image Format for bootm command ERROR: can't get kernel image! /****************************** Flash info *******************************/ U-Boot> fli Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors Intel Standard command set, Manufacturer ID: 0x20, Device ID: 0x49 Erase timeout: 8192 ms, write timeout: 1 ms Buffer write timeout: 1 ms, buffer size: 8 bytes Sector Start Addresses: 00000000 RO 00002000 RO 00004000 RO 00006000 RO 00008000 RO 0000A000 RO 0000C000 RO 0000E000 RO 00010000 RO 00020000 RO 00030000 RO 00040000 RO 00050000 RO 00060000 RO 00070000 RO 00080000 RO 00090000 RO 000A0000 RO 000B0000 RO 000C0000 RO 000D0000 RO 000E0000 RO 000F0000 RO 00100000 RO 00110000 RO 00120000 RO 00130000 RO 00140000 RO 00150000 RO 00160000 RO 00170000 RO 00180000 RO 00190000 RO 001A0000 RO 001B0000 RO 001C0000 RO 001D0000 RO 001E0000 RO 001F0000 RO 00200000 RO 00210000 RO 00220000 RO 00230000 RO 00240000 RO 00250000 RO 00260000 RO 00270000 RO 00280000 RO 00290000 RO 002A0000 RO 002B0000 RO 002C0000 RO 002D0000 RO 002E0000 RO 002F0000 RO 00300000 RO 00310000 RO 00320000 RO 00330000 RO 00340000 RO 00350000 RO 00360000 RO 00370000 RO 00380000 RO 00390000 RO 003A0000 RO 003B0000 RO 003C0000 RO 003D0000 RO 003E0000 RO 003F0000 RO 00400000 RO 00410000 RO 00420000 RO 00430000 RO 00440000 RO 00450000 RO 00460000 RO 00470000 RO 00480000 RO 00490000 RO 004A0000 RO 004B0000 RO 004C0000 RO 004D0000 RO 004E0000 RO 004F0000 RO 00500000 RO 00510000 RO 00520000 RO 00530000 RO 00540000 RO 00550000 RO 00560000 RO 00570000 RO 00580000 RO 00590000 RO 005A0000 RO 005B0000 RO 005C0000 RO 005D0000 RO 005E0000 RO 005F0000 RO 00600000 RO 00610000 RO 00620000 RO 00630000 RO 00640000 RO 00650000 RO 00660000 RO 00670000 RO 00680000 RO 00690000 RO 006A0000 RO 006B0000 RO 006C0000 RO 006D0000 RO 006E0000 RO 006F0000 RO 00700000 RO 00710000 RO 00720000 RO 00730000 RO 00740000 RO 00750000 RO 00760000 RO 00770000 RO 00780000 RO 00790000 RO 007A0000 RO 007B0000 RO 007C0000 RO 007D0000 RO 007E0000 RO 007F0000 RO /****************************** Unprotecting memory *******************************/ U-Boot> protect off 0x20000 0x7effff /****************************** Flash info *******************************/ U-Boot> fli Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors Intel Standard command set, Manufacturer ID: 0x20, Device ID: 0x49 Erase timeout: 8192 ms, write timeout: 1 ms Buffer write timeout: 1 ms, buffer size: 8 bytes Sector Start Addresses: 00000000 RO 00002000 RO 00004000 RO 00006000 RO 00008000 RO 0000A000 RO 0000C000 RO 0000E000 RO 00010000 RO 00020000 00030000 00040000 00050000 00060000 00070000 00080000 00090000 000A0000 000B0000 000C0000 000D0000 000E0000 000F0000 00100000 00110000 00120000 00130000 00140000 00150000 00160000 00170000 00180000 00190000 001A0000 001B0000 001C0000 001D0000 001E0000 001F0000 00200000 00210000 00220000 00230000 00240000 00250000 00260000 00270000 00280000 00290000 002A0000 002B0000 002C0000 002D0000 002E0000 002F0000 00300000 00310000 00320000 00330000 00340000 00350000 00360000 00370000 00380000 00390000 003A0000 003B0000 003C0000 003D0000 003E0000 003F0000 00400000 00410000 00420000 00430000 00440000 00450000 00460000 00470000 00480000 00490000 004A0000 004B0000 004C0000 004D0000 004E0000 004F0000 00500000 00510000 00520000 00530000 00540000 00550000 00560000 00570000 00580000 00590000 005A0000 005B0000 005C0000 005D0000 005E0000 005F0000 00600000 00610000 00620000 00630000 00640000 00650000 00660000 00670000 00680000 00690000 006A0000 006B0000 006C0000 006D0000 006E0000 006F0000 00700000 00710000 00720000 00730000 00740000 00750000 00760000 00770000 00780000 00790000 007A0000 007B0000 007C0000 007D0000 007E0000 007F0000 RO Un-Protected 125 sectors /****************************** Erasing memory *******************************/ U-Boot> erase 0x20000 0x7effff fwc addr 00020000 cmd 50 0050 16bit x 16 bit fwc addr 00020000 cmd 20 0020 16bit x 16 bit fwc addr 00020000 cmd d0 00d0 16bit x 16 bit flash_is_busy: 0 ........ fwc addr 007d0000 cmd ff 00ff 16bit x 16 bit .fwc addr 007e0000 cmd 50 0050 16bit x 16 bit fwc addr 007e0000 cmd 20 0020 16bit x 16 bit fwc addr 007e0000 cmd d0 00d0 16bit x 16 bit flash_is_busy: 0 fwc addr 007e0000 cmd ff 00ff 16bit x 16 bit . done Erased 125 sectors /****************************** Display memory at 0x20000 *******************************/ U-Boot> md.b 0x20000 00020000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 00020010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 00020020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 00020030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ /****************************** I want to try to copy some bytes to the memory with the cp.b command. This works with the at49bc642d flash. Look at the memory at 0x90000000 in ram before copying it to flash at 0x20000 *******************************/ U-Boot> md.b 0x90000000 90000000: 00 00 00 00 33 cc 63 4c 77 cc 13 48 23 ec 37 dc ....3.cLw..H#.7. 90000010: 13 ce 33 cc 33 cc b3 cc 37 cc 73 ce 31 cc 33 cc ..3.3...7.s.1.3. /****************************** Copy from RAM memory at 0x90000000 to Flash memory, this works on a normal ngw100 with at49bv642d *******************************/ U-Boot> cp.b 0x90000000 0x20000 0x10 Copy to Flash... fwc addr (null) cmd 50 0050 16bit x 16 bit fwc addr (null) cmd 40 0040 16bit x 16 bit flash_is_busy: 0 fwc addr 00020000 cmd ff 00ff 16bit x 16 bit fwc addr (null) cmd 50 0050 16bit x 16 bit fwc addr (null) cmd 40 0040 16bit x 16 bit ...... flash_is_busy: 0 fwc addr 00020000 cmd ff 00ff 16bit x 16 bit fwc addr (null) cmd 50 0050 16bit x 16 bit fwc addr (null) cmd 40 0040 16bit x 16 bit flash_is_busy: 0 fwc addr 00020000 cmd ff 00ff 16bit x 16 bit done /****************************** Display memory at 0x20000, nothing has been written. *******************************/ U-Boot> md.b 0x20000 00020000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 00020010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ U-Boot>

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[U-Boot] Please My Dear I Need Your Help.
by mary kipkalya 14 Nov '11

14 Nov '11

Please My Dear I Need Your Help. I know you will be surprise to receive this email, but Before I go further I will like you to understand that, I am writing this mail to you With due respect trust and humanity, I appeal to you to exercise a little patience and read through my letter I feel quite safe dealing with you in this important business, honestly i am writing this email to you with pains, tears and sorrow from my heart, i will really like to have a good relationship with you and i have a special reason why i decided to contact you, i decided to contact you due to the urgency of my present situation here in the refugee camp. My name is Miss. Mary Kipkalya Kones, 25yrs old female and I from Kenya here in Africa; my father was the former Kenyan road Minister. He and Assistant Minister of Home Affairs Lorna Laboso had been on board the Cessna 210, which was headed to Kericho and crashed in a remote area called Kajong'a, in western Kenya. The plane crashed on Tuesday 10th, June, 2008. After the burial of my beloved father, my stepmother and uncle conspired and sold all my father's properties to an Italian Expertrate which they shared the money they sold from the properties among themselves and live nothing for me. Unfortunately to me I fined my father's briefcase and when I opened it I found a document which my Father used to deposited amount of money in one bank here in Burkina Faso, with my name as the next of kin. I travelled to Burkina Faso here I am, to withdraw the money for a better life so that I can take care of myself and start up a new life and also further my education, when I arrival to the bank, the Bank foreign Operation Department Director whom I meet in person told me that my father instruction to their bank is that the fund would only be release to me when I am married or present a trustee/partner who will help me and invest the fund overseas after the transfer, and the bank ask me to go and look for a foreign partner, that was why am contacting you, which I believe that you are going to be honest and reliable person that will help me and stand as my trustee/partner, so that I can present you to the Bank for the release and transfer of the inherited fund into your bank account in your country. I have chosen to contact you after my prayers and I believe that you will not betray my trust. But rather take me as your own sister. Though you may wonder why I am so soon revealing myself to you without knowing you, well I will say that my mind convinced me that you will be the true person to help me. Moreover, I will like to disclose much to you if you can help me to relocate to your country because my stepmothers have threatened to assinate me. The fund my Father deposited into the bank, is ($8.5 USD) Million United State Dollars, and I have confirmed from the bank here in Burkina Faso, on my arrival, You will also help me to place the fund in a good profitable business venture in your Country, However you will also help by recommending a nice University in your country so that I can further my education. It is my intention to compensate you with 40% of the total money for your services and the balance shall be my capital in your establishment. Now my dear as soon as I receive your positive response showing your interest and wiliness to help me, I will put things into action immediately. In the light of the above, I shall appreciate an urgent message indicating your ability and willingness to help me and also handle this transaction sincerely. Awaiting your urgent and positive response. Please my dear I want you to keep this as a top secret only to your self for now until the bank will release and transfer my inherited fund to you as my appointed trustee/partner. I beg you once again not to disclose this to any body until i come over your country because I am afraid of my wreaked stepmother who has threatened to kill me and have my inherited fund alone. I thank you very much and am expecting to hear from you soonest. Yours Sincerely Mary Kipkalya Kones.

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[U-Boot] Hello
by Aicha Ciss 13 Nov '11

13 Nov '11

Hello How are you doing today? I hope fine My name Is miss aicha ciss i become interested when i gone through your profile today at skymem.com/ contact me back i have a lot to discuss with you Yours New Friend Aicha

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[U-Boot] arm mach-types.h
by Michael Walle 13 Nov '11

13 Nov '11

Hi, Does u-boot always follow the mach-types.h from upstream linux? Is there any policy? If thats true, it means, that - every supported board in u-boot has to be supported in mainline linux, too. because that is the basic requirement for an entry to stay in this file. - a device with device tree bindings, won't have any mach-type entry at all, which means, that a distribution is not able to backport a device support from DT form to an old-fashioned setup code (eg. support for a board on older linux kernels, which doesn't have ARM device tree support). IMHO u-boot should have its own mach-types.h (maybe autogenerated, like the linux kernel do), just with entries for boards which are supported by u-boot. This way, there won't be any problems with new board support patches. Opinions? -- Michael

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[U-Boot] [PATCH] [fdt] Fix constness of the fdt void pointer in fdt_getprop_u32_default
by Gabe Black 13 Nov '11

13 Nov '11

The function fdt_getprop_u32_default doesn't modify the fdt, so it can use a const void * for its fdt argument. Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- common/fdt_support.c | 4 ++-- include/fdt_support.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index bdda64d..bd3a014 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -49,8 +49,8 @@ DECLARE_GLOBAL_DATA_PTR; * Convenience function to find a node and return it's property or a * default value if it doesn't exist. */ -u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop, - const u32 dflt) +u32 fdt_getprop_u32_default(const void *fdt, const char *path, + const char *prop, const u32 dflt) { const u32 *val; int off; diff --git a/include/fdt_support.h b/include/fdt_support.h index c7b4605..cef3c65 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -28,8 +28,8 @@ #include <fdt.h> -u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop, - const u32 dflt); +u32 fdt_getprop_u32_default(const void *fdt, const char *path, + const char *prop, const u32 dflt); int fdt_chosen(void *fdt, int force); int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force); void do_fixup_by_path(void *fdt, const char *path, const char *prop, -- 1.7.3.1

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[U-Boot] [PATCH] Add some missing endian conversions in fdt_support.c
by Gabe Black 13 Nov '11

13 Nov '11

Some functions in fdt_support.c use fdt_getprop to read 32 bit values out of the device tree, but then use them directly without doing any endian conversion. Because they check for a value that doesn't actually appear in practice, the functions continued to work even though they're incorrect. This change adds the missing conversions. Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- common/fdt_support.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index bdda64d..c501604 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -61,7 +61,7 @@ u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop, val = fdt_getprop(fdt, off, prop, NULL); if (val) - return *val; + return fdt32_to_cpu(*val); else return dflt; } @@ -372,7 +372,7 @@ static int get_cells_len(void *blob, char *nr_cells_name) const u32 *cell; cell = fdt_getprop(blob, 0, nr_cells_name, NULL); - if (cell && *cell == 2) + if (cell && fdt32_to_cpu(*cell) == 2) return 8; return 4; -- 1.7.3.1

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