November 2011 - U-Boot

[U-Boot] [PATCH 1/5] mx53loco: Configure the pins as GPIOs prior to using gpio_get_value
by Fabio Estevam 17 Nov '11

17 Nov '11

Configure the pins as GPIO prior to using gpio_get_value. Cc: Jason Liu <r64343(a)freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/freescale/mx53loco/mx53loco.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index b4c7f33..5e5c38f 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -139,6 +139,9 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = { int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(77); /*GPIO3_13*/ -- 1.7.1

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[U-Boot] (no subject)
by Kenoye Eke 17 Nov '11

17 Nov '11

Guten Tag Obwohl Sie vielleicht besorgt über meine E-Mail, da wir nicht getroffen haben, bevor ich Mervyn King bin, und ich bin der Gouverneur der Bank of England, Es ist die Summe von EUR 20,600,000.00 Euros in meiner Bank, gab es keine Begünstigten angegeben in Bezug auf diese Gelder, die bedeutet, dass niemand jemals nach vorne kommen, um es zu verlangen. Beachten Sie, dass diese Transaktion legal und 100% kein Risiko beteiligt ist, beachten Sie auch, dass dies nicht einer kriminellen Tätigkeit oder Geldwäsche. Darum bitte ich, dass wir zusammen arbeiten, um die Überweisung von meiner Bank auf Ihr Bankkonto oder ein beliebiges anderes Konto Ihrer Wahl, die ich gerne sehen, wenn Sie mir helfen können und auch eine gute und vertrauenswürdige Person sein wird. Sobald das Geld auf Ihr Nominiert Bank Account übertragen haben, werden wir dann im Verhältnis von 60% für mich zu teilen, 40% für Sie, schicken Sie mir per E-Mail so schnell wie möglich für mehr Details hier ist meine E-Mail-Adresse: mervynking-uk(a)live.co.uk Mr. Mervyn King E-Mail - mervynking-uk(a)live.co.uk Regards, Herr Mervyn King. Bitte senden Sie Ihre Antwort auf (mervynking-uk(a)live.co.uk)

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[U-Boot] (no subject)
by Western Union Office 17 Nov '11

17 Nov '11

How are you doing today? I write to inform you that we have already sent you $9,000.00USD dollars through Western union as we have been given the mandate to transfer your full benefited sum of $700,000.00 USD (Seven Hundred Thousand US Dollars) via our office here (Western Union) by the United nations in conjunction with the ECOWAS as a compensation. I called to give you the information through phone as internet hackers were many but I cannot reach you yesterday even this morning.So,I decided to email you the MTCN and sender name so that you can pick up this $9,000.00USD to enable us send another $9,000.00USD by tomorrow as you knows we will be sending you only $9,000.00USD per day. All you need to do now is to visit any Western Union office or outlet close to you in your city with the payment information giving to you and your full name in your ID card as the receiver's name to pick up your First payment of $9,000USD and get back to us as soon as possible to enable us send another $9,000.00USD by tomorrow. Manager :Mr Ken Texman Contact Email: westumt(a)kimo.com Email me once you picked up this $9,000.00USD today. Here is the western union information to pick up the $9,000.00USD, Payment Information. Sender's Name:_________Austin Ginika Amount Sent______________$9,000.00 USD MTCN :___________________8492251083 Country:_________________NIGERIA Text Question:___________Trust Answer:__________________God With due respect please get back to us urgently after the pick of the money and if you have any problem you can as well contact us immediately. NOTE: You are advice to keep this transaction strictly confidential pending claim, this is to avoid any double crossing. Thanks Mr Ken Texman Western Union Office.

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[U-Boot] FINAL NOTIFICATION!!!
by Microsoft Corporations 17 Nov '11

17 Nov '11

Micro-Soft Sweepstakes Promotion, Customer Service. Your Batch No: 2011/19803/CMT Your Reference No: SHK/SMO/0829 OFFICIAL WINNING NOTIFICATION. We are pleased to inform you of the release of the long awaited results of Sweepstakes promotion organized by Micro-Soft Corporations, in conjunction with the FOUNDATION FOR THE PROMOTION OF SOFTWARE products, (F.P.S.) held this November 2011, in London. Where in your email address emerged as one of the online Winning emails in the 2nd category and therefore attracted a cash award of £1,000,000.00 Pounds (One Million British Pounds Sterling) and a Toshiba laptop. To begin your claim, do file for the releaseof your winning by contacting our Foreign Transfer Manager: Agent Name: Mr. Parry Cole Tel: +44 704-571-0545 Email: msredeemdept01(a)yahoo.cn The Micro-Soft Sweepstakes Internet E-mail Promotion Awards is sponsored by former CEO/Chairman, Bill Gates and a consortium of software promotion companies.The Intel Group, Toshiba, Dell Computers and other International Companies. The Microsoft internet E-mail draw is held periodically and is organized to encourage the use of the Internet and promote computer literacy worldwide. Congratulations!! Sincerely, Mrs. Anna Williams Co-ordinator Microsoft Promotion

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[U-Boot] [PATCH] powerpc/85xx: Add workaround for erratum CPU-A003999
by Kumar Gala 17 Nov '11

17 Nov '11

Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/release.S | 6 ++++++ arch/powerpc/cpu/mpc85xx/start.S | 6 ++++++ arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ 4 files changed, 21 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 07be03e..f7c0934 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -53,6 +53,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) + puts("Work-around for Erratum CPU-A003999 enabled\n"); +#endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 6678ed4..c81e19c 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -68,6 +68,12 @@ __secondary_start_page: mtspr SPRN_HID1,r3 #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 + mfspr r3,977 + oris r3,r3,0x0100 + mtspr 977,r3 +#endif + /* Enable branch prediction */ lis r3,BUCSR_ENABLE@h ori r3,r3,BUCSR_ENABLE@l diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 39f1438..d032788 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -264,6 +264,12 @@ l2_disabled: mtspr HID1,r0 #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 + mfspr r3,977 + oris r3,r3,0x0100 + mtspr 977,r3 +#endif + /* Enable Branch Prediction */ #if defined(CONFIG_BTB) lis r0,BUCSR_ENABLE@h diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 424ab79..dba9eda 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -316,6 +316,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB138 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P2041) #define CONFIG_MAX_CPUS 4 @@ -335,6 +336,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB138 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -354,6 +356,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB138 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P3060) #define CONFIG_MAX_CPUS 8 @@ -369,6 +372,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -379,6 +383,7 @@ #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -407,6 +412,7 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES9 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) -- 1.7.3.4

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[U-Boot] [PATCH v4 1/4] tegra2: Move MMC clock initialization into MMC driver
by Stephen Warren 17 Nov '11

17 Nov '11

This centralizes knowledge of MMC clocking into the MMC driver. This also removes clock setup from the board files, which will simplify later changes that modify the Harmony board to support the correct set of MMC controllers. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> Acked-by: Simon Glass <sjg(a)chromium.org> Tested-by: Simon Glass <sjg(a)chromium.org> --- board/nvidia/common/board.c | 13 +------------ drivers/mmc/tegra2_mmc.c | 12 +++++++++--- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index d13537d..370a259 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -102,16 +102,6 @@ static void pin_mux_uart(void) #ifdef CONFIG_TEGRA2_MMC /* - * Routine: clock_init_mmc - * Description: init the PLL and clocks for the SDMMC controllers - */ -static void clock_init_mmc(void) -{ - clock_start_periph_pll(PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH, 20000000); - clock_start_periph_pll(PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH, 20000000); -} - -/* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ @@ -157,8 +147,7 @@ int board_init(void) int board_mmc_init(bd_t *bd) { debug("board_mmc_init called\n"); - /* Enable clocks, muxes, etc. for SDMMC controllers */ - clock_init_mmc(); + /* Enable muxes, etc. for SDMMC controllers */ pin_mux_mmc(); gpio_config_mmc(); diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c index 9e741f2..78b1190 100644 --- a/drivers/mmc/tegra2_mmc.c +++ b/drivers/mmc/tegra2_mmc.c @@ -435,14 +435,22 @@ static int mmc_core_init(struct mmc *mmc) static int tegra2_mmc_initialize(int dev_index, int bus_width) { + struct mmc_host *host; struct mmc *mmc; debug(" mmc_initialize called\n"); + host = &mmc_host[dev_index]; + + host->clock = 0; + tegra2_get_setup(host, dev_index); + + clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); + mmc = &mmc_dev[dev_index]; sprintf(mmc->name, "Tegra2 SD/MMC"); - mmc->priv = &mmc_host[dev_index]; + mmc->priv = host; mmc->send_cmd = mmc_send_cmd; mmc->set_ios = mmc_set_ios; mmc->init = mmc_core_init; @@ -465,8 +473,6 @@ static int tegra2_mmc_initialize(int dev_index, int bus_width) mmc->f_min = 375000; mmc->f_max = 48000000; - mmc_host[dev_index].clock = 0; - tegra2_get_setup(&mmc_host[dev_index], dev_index); mmc_register(mmc); return 0; -- 1.7.0.4

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[U-Boot] [PATCH v2 1/3] tegra2: Add common Avionic Design Tamonten support.
by Thierry Reding 17 Nov '11

17 Nov '11

Tamonten is an NVIDIA Tegra2-based SO-DIMM processor module that is derived from the Harmony reference design. Signed-off-by: Thierry Reding <thierry.reding(a)avionic-design.de> --- board/avionic-design/common/tamonten.c | 164 ++++++++++++++++++++++++++++++++ board/avionic-design/common/tamonten.h | 34 +++++++ 2 files changed, 198 insertions(+), 0 deletions(-) create mode 100644 board/avionic-design/common/tamonten.c create mode 100644 board/avionic-design/common/tamonten.h diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c new file mode 100644 index 0000000..05f9021 --- /dev/null +++ b/board/avionic-design/common/tamonten.c @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011 + * Avionic Design GmbH <www.avionic-design.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/sys_proto.h> + +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/uart.h> +#include "tamonten.h" + +#ifdef CONFIG_TEGRA2_MMC +#include <mmc.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct tegra2_sysinfo sysinfo = { + CONFIG_TEGRA2_BOARD_STRING +}; + +/* + * Routine: timer_init + * Description: init the timestamp and lastinc value + */ +int timer_init(void) +{ + return 0; +} + +static void enable_uart(enum periph_id pid) +{ + /* Assert UART reset and enable clock */ + reset_set_enable(pid, 1); + clock_enable(pid); + clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */ + + /* wait for 2us */ + udelay(2); + + /* De-assert reset to UART */ + reset_set_enable(pid, 0); +} + +/* + * Routine: clock_init_uart + * Description: init the PLL and clock for the UART(s) + */ +static void clock_init_uart(void) +{ +#if defined(CONFIG_TEGRA2_ENABLE_UARTD) + enable_uart(PERIPH_ID_UART4); +#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ +} + +/* + * Routine: pin_mux_uart + * Description: setup the pin muxes/tristate values for the UART(s) + */ +static void pin_mux_uart(void) +{ +#if defined(CONFIG_TEGRA2_ENABLE_UARTD) + pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); + + pinmux_tristate_disable(PINGRP_GMC); +#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ +} + +#ifdef CONFIG_TEGRA2_MMC +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + /* SDMMC4: config 3, x8 on 2nd set of pins */ + pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); + pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4); + pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4); + + pinmux_tristate_disable(PINGRP_ATB); + pinmux_tristate_disable(PINGRP_GMA); + pinmux_tristate_disable(PINGRP_GME); +} +#endif + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + clock_init(); + clock_verify(); + + /* boot param addr */ + gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); + + return 0; +} + +#ifdef CONFIG_TEGRA2_MMC +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("board_mmc_init called\n"); + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + gpio_config_mmc(); + + debug("board_mmc_init: init eMMC\n"); + /* init dev 0, eMMC chip, with 4-bit bus */ + tegra2_mmc_init(0, 4); + + return 0; +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + /* Initialize essential common plls */ + clock_early_init(); + + /* Initialize UART clocks */ + clock_init_uart(); + + /* Initialize periph pinmuxes */ + pin_mux_uart(); + + /* Initialize periph GPIOs */ + gpio_config_uart(); + + /* Init UART, scratch regs, and start CPU */ + tegra2_start(); + return 0; +} +#endif /* EARLY_INIT */ diff --git a/board/avionic-design/common/tamonten.h b/board/avionic-design/common/tamonten.h new file mode 100644 index 0000000..802bc51 --- /dev/null +++ b/board/avionic-design/common/tamonten.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011 + * Avionic Design GmbH <www.avionic-design.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TAMONTEN_H_ +#define _TAMONTEN_H_ + +void tegra2_start(void); +void gpio_config_uart(void); +void gpio_config_mmc(void); +int tegra2_mmc_init(int dev_index, int bus_width); + +#endif /* TAMONTEN_H */ -- 1.7.7.3

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Re: [U-Boot] [PATCH v2] arm:exynos4:samsung:nuri Support for NURI target.
by Minkyu Kang 17 Nov '11

17 Nov '11

Dear Lukasz Majewski, On 10 November 2011 17:39, Lukasz Majewski <l.majewski(a)samsung.com> wrote: > This patch adds support for Samsung's Exynos4 Nuri reference > board. > > New exynos4_nuri board has been added to boards.cfg > > Signed-off-by: Lukasz Majewski <l.majewski(a)samsung.com> > Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> > Cc: Minkyu Kang <mk7.kang(a)samsung.com> > --- > Changes for v2: > - MAINTAINERS file updated > - CONFIG_MACH_TYPE added > - hw_revision routine rewritten > > tools/checkpatch.pl - > total: 0 errors, 0 warnings, 869 lines checked > > NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX MULTISTATEMENT_MACRO_USE_DO_WHILE > > --- > MAINTAINERS | 4 + > board/samsung/nuri/Makefile | 45 ++++ > board/samsung/nuri/lowlevel_init.S | 395 ++++++++++++++++++++++++++++++++++++ > board/samsung/nuri/nuri.c | 202 ++++++++++++++++++ > boards.cfg | 1 + > include/configs/exynos4_nuri.h | 210 +++++++++++++++++++ > 6 files changed, 857 insertions(+), 0 deletions(-) > create mode 100644 board/samsung/nuri/Makefile > create mode 100644 board/samsung/nuri/lowlevel_init.S > create mode 100644 board/samsung/nuri/nuri.c > create mode 100644 include/configs/exynos4_nuri.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 576fea8..de2bcc0 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -686,6 +686,10 @@ Minkyu Kang <mk7.kang(a)samsung.com> > s5p_goni ARM ARMV7 (S5PC110 SoC) > s5pc210_universal ARM ARMV7 (S5PC210 SoC) > > +Łukasz Majewski <l.majewski(a)samsung.com> > + > + exynos4_nuri ARM ARMV7 (S5PC210 SoC) > + Please keep this list to alphabetically. > Chander Kashyap <k.chander(a)samsung.com> > > origen ARM ARMV7 (S5PC210 SoC) > diff --git a/board/samsung/nuri/nuri.c b/board/samsung/nuri/nuri.c > new file mode 100644 > index 0000000..7edd1ed > --- /dev/null > +++ b/board/samsung/nuri/nuri.c > @@ -0,0 +1,202 @@ > +#ifdef CONFIG_GENERIC_MMC > +int board_mmc_init(bd_t *bis) > +{ > + int i, err; > + > + /* MASSMEMORY_EN: GPL[1] -> output LOW */ > + s5p_gpio_direction_output(&gpio2->l1, 1, 0); > + s5p_gpio_set_pull(&gpio2->l1, 1, GPIO_PULL_NONE); > + > + /* > + * eMMC GPIO: > + * SDR 8-bit@48MHz at MMC0 > + * GPK0[0] SD_0_CLK(2) > + * GPK0[1] SD_0_CMD(2) > + * GPK0[2] SD_0_CDn -> Not used > + * GPK0[3:6] SD_0_DATA[0:3](2) > + * GPK1[3:6] SD_0_DATA[0:3](3) > + * > + * DDR 4-bit@26MHz at MMC4 > + * GPK0[0] SD_4_CLK(3) > + * GPK0[1] SD_4_CMD(3) > + * GPK0[2] SD_4_CDn -> Not used > + * GPK0[3:6] SD_4_DATA[0:3](3) > + * GPK1[3:6] SD_4_DATA[4:7](4) > + */ > + for (i = 0; i < 7; i++) { > + if (i == 2) > + continue; > + /* GPK0[0:6] special function 2 */ > + s5p_gpio_cfg_pin(&gpio2->k0, i, GPIO_FUNC(0x2)); > + /* GPK0[0:6] pull disable */ > + s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); > + /* GPK0[0:6] drv 4x */ > + s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); > + } > + > + for (i = 3; i < 7; i++) { > + /* GPK1[3:6] special function 3 */ > + s5p_gpio_cfg_pin(&gpio2->k1, i, GPIO_FUNC(0x3)); > + /* GPK1[3:6] pull disable */ > + s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); > + /* GPK1[3:6] drv 4x */ > + s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); > + } > + > + /* > + * MMC device init > + * mmc0 : eMMC (8-bit buswidth) > + * mmc2 : SD card (4-bit buswidth) > + */ > + err = s5p_mmc_init(0, 8); > + > + /* T-flash detect */ > + s5p_gpio_cfg_pin(&gpio2->x3, 3, GPIO_IRQ); > + s5p_gpio_set_pull(&gpio2->x3, 3, GPIO_PULL_UP); > + > + /* > + * Check the T-flash detect pin > + * GPX3[3] T-flash detect pin > + */ > + if (!s5p_gpio_get_value(&gpio2->x3, 3)) { > + /* > + * SD card GPIO: > + * GPK2[0] SD_2_CLK(2) > + * GPK2[1] SD_2_CMD(2) > + * GPK2[2] SD_2_CDn -> Not used > + * GPK2[3:6] SD_2_DATA[0:3](2) > + */ > + for (i = 0; i < 7; i++) { > + if (i == 2) > + continue; > + /* GPK2[0:6] special function 2 */ > + s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); > + /* GPK2[0:6] pull disable */ > + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); > + /* GPK2[0:6] drv 4x */ > + s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); > + } > + err = s5p_mmc_init(2, 4); > + } > + > + return err; > + please remove dead space. > +} > +#endif > diff --git a/include/configs/exynos4_nuri.h b/include/configs/exynos4_nuri.h > new file mode 100644 > index 0000000..35858ec > --- /dev/null > +++ b/include/configs/exynos4_nuri.h > @@ -0,0 +1,210 @@ > +/* > + * Copyright (C) 2011 Samsung Electronics > + * Łukasz Majewski <l.majewski(a)samsung.com> > + * > + * Configuation settings for the SAMSUNG Universal (s5pc100) board. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +/* > + * High Level Configuration Options > + * > + */ > +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ > +#define CONFIG_S5P /* which is in a S5P Family */ > +#define CONFIG_S5PC210 /* which is in a S5PC210 */ > +#define CONFIG_NURI /* working with NURI */ > + > +#define MACH_TYPE_NURI 3379 Why you redefine the mach_type? > +#define CONFIG_MACH_TYPE MACH_TYPE_NURI /* NURI mach type */ Thanks Minkyu Kang -- from. prom. www.promsoft.net

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[U-Boot] [PATCH] powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sata
by Chang-Ming.Huang＠freescale.com 17 Nov '11

17 Nov '11

From: Jerry Huang <Chang-Ming.Huang(a)freescale.com> In the current u-boot code, the value of these fields are the reserved value (0b100), through the signal integrity measurement on freescale's board with these reserved setting, the signal eye is out of the recommended spec for non-transition amplitude at 500mV nominal. According to the errata for MPC8379E, we should make a change to the recommended setting from essentially nothing at this time to 0b001 for SATA. Signed-off-by: Jerry Huang <Chang-Ming.Huang(a)freescale.com> CC: Kim Phillips <kim.phillips(a)freescale.com> --- arch/powerpc/cpu/mpc83xx/serdes.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index fecfc80..13b2fd1 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -1,7 +1,7 @@ /* * Freescale SerDes initialization routine * - * Copyright (C) 2007 Freescale Semicondutor, Inc. + * Copyright (C) 2007,2011 Freescale Semicondutor, Inc. * Copyright (C) 2008 MontaVista Software, Inc. * * Author: Li Yang <leoli(a)freescale.com> @@ -20,6 +20,10 @@ /* SerDes registers */ #define FSL_SRDSCR0_OFFS 0x0 #define FSL_SRDSCR0_DPP_1V2 0x00008800 +#define FSL_SRDSCR0_TXEQA_MASK 0x00007000 +#define FSL_SRDSCR0_TXEQA_SATA 0x00001000 +#define FSL_SRDSCR0_TXEQE_MASK 0x00000700 +#define FSL_SRDSCR0_TXEQE_SATA 0x00000100 #define FSL_SRDSCR1_OFFS 0x4 #define FSL_SRDSCR1_PLLBW 0x00000040 #define FSL_SRDSCR2_OFFS 0x8 @@ -71,6 +75,14 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) tmp &= ~FSL_SRDSRSTCTL_SATA_RESET; out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + /* Configure SRDSCR0 */ + tmp = in_be32(regs + FSL_SRDSCR0_OFFS); + tmp &= ~FSL_SRDSCR0_TXEQA_MASK; + tmp |= FSL_SRDSCR0_TXEQA_SATA; + tmp &= ~FSL_SRDSCR0_TXEQE_MASK; + tmp |= FSL_SRDSCR0_TXEQE_SATA; + out_be32(regs + FSL_SRDSCR0_OFFS, tmp); + /* Configure SRDSCR1 */ tmp = in_be32(regs + FSL_SRDSCR1_OFFS); tmp &= ~FSL_SRDSCR1_PLLBW; -- 1.6.4

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Re: [U-Boot] Financial Loan Offer Apply Now.
by Stacey Militello 17 Nov '11

17 Nov '11

________________________________ From: Stacey Militello Sent: Wednesday, November 16, 2011 1:11 PM To: INFO(a)LOAN.ORG Subject: Financial Loan Offer Apply Now. Financial Loan Offer Apply Now. Contact Email:financialloanoffer@financier.com Good day, I am Mr Barry Smith a financial loan lender, I am willing to lend out loans with the interest rate of 2%, and with in the amount 2,000.00 to 450,000,000 as the loan offer in any currency,I offer loan to all categories of people ,firms, companies, all kinds of business organizations, private individuals and real estate investors and many more I need your urgent response if you are interested. You are to contact me with this Email: financialloanoffer(a)financier.com<mailto:financialloanoffer@financier.com> and also you are require to get back to us with this Information stated below: Your Full Name: Amount Needed as the loan: Duration To Pay Back The Loan: purpose of loan: Phone Number: Country: State: Occupation: Address: Services Rendered include: Refinance Loan,Home Improvement,Investment Loan,Auto Loans,Debt Consolidation,Line of Credit,Second Mortgage,Business Loans,Personal Loans,Car Loan,Auto Loan. Please write back if interested.Contact Via Email: financialloanoffer(a)financier.com<mailto:financialloanoffer@financier.com> Thanks

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