October 2011 - U-Boot

[U-Boot] [PATCH] fm-eth: Add ability for board code to disable a port
by Kumar Gala 03 Oct '11

03 Oct '11

The SoC configuration may have more ports enabled than a given board actually can utilize. Add a routinue that allows the board code to disable a port that it knows isn't being used. fm_disable_port() needs to be called before cpu_eth_init(). Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- drivers/net/fm/fm.h | 1 + drivers/net/fm/init.c | 8 ++++++++ drivers/net/fm/p1023.c | 6 ++++++ drivers/net/fm/p4080.c | 6 ++++++ drivers/net/fm/p5020.c | 6 ++++++ include/fm_eth.h | 1 + 6 files changed, 28 insertions(+), 0 deletions(-) diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index be6714f..228df33 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -110,6 +110,7 @@ u32 fm_muram_base(int fm_idx); int fm_init_common(int index, struct ccsr_fman *reg); int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info); phy_interface_t fman_port_enet_if(enum fm_port port); +void fman_disable_port(enum fm_port port); struct fsl_enet_mac { void *base; /* MAC controller registers base address */ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 5f05ab1..512d7dd 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -123,6 +123,14 @@ void fman_enet_init(void) return ; } +void fm_disable_port(enum fm_port port) +{ + int i = fm_port_to_index(port); + + fm_info[i].enabled = 0; + fman_disable_port(port); +} + void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus) { int i = fm_port_to_index(port); diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c index c196e79..b17dc40 100644 --- a/drivers/net/fm/p1023.c +++ b/drivers/net/fm/p1023.c @@ -36,6 +36,12 @@ static int is_device_disabled(enum fm_port port) return port_to_devdisr[port] & devdisr; } +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + setbits_be32(&gur->devdisr, port_to_devdisr[port]); +} + phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c index 6761a2f..791caab 100644 --- a/drivers/net/fm/p4080.c +++ b/drivers/net/fm/p4080.c @@ -44,6 +44,12 @@ static int is_device_disabled(enum fm_port port) return port_to_devdisr[port] & devdisr2; } +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c index 59638eb..69c27d2 100644 --- a/drivers/net/fm/p5020.c +++ b/drivers/net/fm/p5020.c @@ -40,6 +40,12 @@ static int is_device_disabled(enum fm_port port) return port_to_devdisr[port] & devdisr2; } +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/include/fm_eth.h b/include/fm_eth.h index 2ca584a..c7c6882 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -110,5 +110,6 @@ void fdt_fixup_fman_ethernet(void *fdt); phy_interface_t fm_info_get_enet_if(enum fm_port port); void fm_info_set_phy_address(enum fm_port port, int address); void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus); +void fm_disable_port(enum fm_port port); #endif -- 1.7.3.4

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[U-Boot] [PATCH] powerpc/85xx: Refactor some defines out of corenet_ds.h
by Kumar Gala 03 Oct '11

03 Oct '11

Move some SoC/board specific defines out of corenet_ds.h and into the corresponding P3041DS/P4080DS/P5020.h. We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060 SoC/reference board does not have these devices and it will share the same board code. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/configs/P3041DS.h | 5 +++++ include/configs/P4080DS.h | 5 +++++ include/configs/P5020DS.h | 5 +++++ include/configs/corenet_ds.h | 9 +-------- 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index d9e8f51..e4d1fe5 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -28,7 +28,12 @@ #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P3041 +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_MMC +#define CONFIG_NAND_FSL_ELBC #define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 49f7c53..4a2e475 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -27,6 +27,11 @@ #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P4080 +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_MMC +#define CONFIG_PCIE3 + #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 2c7beba..618d1a4 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -28,7 +28,12 @@ #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P5020 +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_MMC +#define CONFIG_NAND_FSL_ELBC #define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_FSL_RAID_ENGINE diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index d5fc19b..4bbca88 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -56,7 +56,6 @@ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ @@ -199,7 +198,6 @@ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull @@ -230,8 +228,6 @@ #endif /* Nand Flash */ -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) -#define CONFIG_NAND_FSL_ELBC #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT @@ -272,11 +268,10 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #endif -#endif /* CONFIG_NAND_FSL_ELBC */ #else #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ -#endif +#endif /* CONFIG_NAND_FSL_ELBC */ #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 @@ -587,8 +582,6 @@ #define CONFIG_CMD_EXT2 #define CONFIG_HAS_FSL_DR_USB -#define CONFIG_MMC - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -- 1.7.3.4

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[U-Boot] [PATCH v2] powerpc/85xx: Add support for setting up RAID engine liodns on P5020
by Kumar Gala 03 Oct '11

03 Oct '11

Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- * Removed typedef arch/powerpc/cpu/mpc85xx/liodn.c | 25 ++++++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/p5020_ids.c | 13 +++++++++++++ arch/powerpc/include/asm/fsl_liodn.h | 11 ++++++++++- arch/powerpc/include/asm/fsl_portals.h | 3 +++ arch/powerpc/include/asm/immap_85xx.h | 19 +++++++++++++++++++ include/configs/P5020DS.h | 1 + 6 files changed, 70 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index bd19094..e0ea502 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -120,6 +120,19 @@ static void setup_pme_liodn_base(void) #endif } +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +static void setup_raide_liodn_base(void) +{ + struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR; + + /* setup raid engine liodn base for data/desc ; both set to 47 */ + u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0]; + + out_be32(&raide->liodnbr, base); +} +#endif + void set_liodns(void) { /* setup general liodn offsets */ @@ -145,6 +158,12 @@ void set_liodns(void) #endif /* setup PME liodn base */ setup_pme_liodn_base(); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + /* raid engine ccr addr code for liodn */ + set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz); + setup_raide_liodn_base(); +#endif } static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) @@ -184,4 +203,8 @@ void fdt_fixup_liodn(void *blob) #endif #endif fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + fdt_fixup_liodn_tbl(blob, raide_liodn_tbl, raide_liodn_tbl_sz); +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 9836588..2911c13 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -97,6 +97,16 @@ struct liodn_id_table sec_liodn_tbl[] = { }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +struct liodn_id_table raide_liodn_tbl[] = { + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63), +}; +int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); +#endif + struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), #ifdef CONFIG_SYS_DPAA_FMAN @@ -105,4 +115,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_PME [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), #endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47), +#endif }; diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 801571f..9ad104e 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -147,9 +147,18 @@ extern void fdt_fixup_liodn(void *blob); offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, 0) +#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \ + SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \ + liodnA, \ + offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \ + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \ + offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \ + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) + extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; +extern struct liodn_id_table raide_liodn_tbl[]; extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; -extern int liodn_tbl_sz, sec_liodn_tbl_sz; +extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz; extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz; #endif diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index e1c1212..8c3ea0b 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -35,6 +35,9 @@ enum fsl_dpaa_dev { #ifdef CONFIG_SYS_DPAA_PME FSL_HW_PORTAL_PME, #endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + FSL_HW_PORTAL_RAID_ENGINE, +#endif }; struct qportal_info { diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 135e2d8..769ca85 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2318,6 +2318,22 @@ typedef struct ccsr_usb_phy { } ccsr_usb_phy_t; #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +struct ccsr_raide { + u8 res0[0x543]; + u32 liodnbr; /* LIODN Base Register */ + u8 res1[0xab8]; + struct { + struct { + u32 cfg0; /* cfg register 0 */ + u32 cfg1; /* cfg register 1 */ + u8 res1[0x3f8]; + } ring[2]; + u8 res[0x800]; + } jq[2]; +}; +#endif + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2348,6 +2364,7 @@ typedef struct ccsr_usb_phy { #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 @@ -2418,6 +2435,8 @@ typedef struct ccsr_usb_phy { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) +#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index dd8d442..2c7beba 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -30,6 +30,7 @@ #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 +#define CONFIG_SYS_FSL_RAID_ENGINE #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -- 1.7.3.4

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[U-Boot] [PATCH v2] powerpc/mpc85xxcds: Fix PCI speed
by Zhao Chenhui 03 Oct '11

03 Oct '11

From: chenhui zhao <chenhui.zhao(a)freescale.com> The CDS uses PCICLK as SYSCLK. The PCICLK should be 33333333Hz or 66666666Hz. Signed-off-by: Ebony Zhu <ebony.zhu(a)freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao(a)freescale.com> --- Changes for v2: -rewrite the description. -use strmhz(). board/freescale/common/cadmus.c | 8 ++++---- board/freescale/mpc8541cds/mpc8541cds.c | 6 +++--- board/freescale/mpc8548cds/mpc8548cds.c | 4 ++-- board/freescale/mpc8555cds/mpc8555cds.c | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c index db54bc4..50b6e9f 100644 --- a/board/freescale/common/cadmus.c +++ b/board/freescale/common/cadmus.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -61,12 +61,12 @@ get_clock_freq(void) uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ if (pci1_speed == 0) { - return 33000000; + return 33333333; } else if (pci1_speed == 1) { - return 66000000; + return 66666666; } else { /* Really, unknown. Be safe? */ - return 33000000; + return 33333333; } } diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 0d3752d..d127137 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * (C) Copyright 2002 Scott McNutt <smcnutt(a)artesyncp.com> * @@ -200,6 +200,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + char buf[32]; /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -222,8 +223,7 @@ int checkboard (void) printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", + strmhz(buf, pci1_speed), pci1_clk_sel ? "sync" : "async"); if (pci_dual) { diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 8ab9752..3bcaac4 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -214,6 +214,7 @@ void pci_init_board(void) u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; + char buf[32]; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); @@ -238,8 +239,7 @@ void pci_init_board(void) pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", + strmhz(buf, pci_speed), pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 60d1758..48ede98 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -198,6 +198,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + char buf[32]; /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -220,8 +221,7 @@ int checkboard (void) printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, - (pci1_speed == 33000000) ? "33" : - (pci1_speed == 66000000) ? "66" : "unknown", + strmhz(buf, pci1_speed), pci1_clk_sel ? "sync" : "async"); if (pci_dual) { -- 1.6.4.1

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[U-Boot] [PATCH 0/3] Add secure boot support on P4080/P3041/P5020 & P1010 boards.
by Ruchika Gupta 03 Oct '11

03 Oct '11

Boot Flow in secure systems: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. On system reset, BOOt ROM code executes first. It validates the u-boot image, and then passes control to u-boot The patch set adds the changes for u-boot to execute after BOOT ROM code in secure systems. Kumar Gala (2): powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards P1010RDB :Secure Boot support added for NOR , NAND and SPIFLASH Ruchika Gupta (1): powerpc/p4080: Add support for secure boot flow arch/powerpc/cpu/mpc85xx/cpu_init.c | 11 +++++- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 10 +++++- arch/powerpc/cpu/mpc85xx/start.S | 55 +++++++++++++++++++++++++++- arch/powerpc/include/asm/fsl_secure_boot.h | 43 ++++++++++++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 2 + boards.cfg | 9 +++++ include/configs/P1010RDB.h | 15 +++++++- include/configs/corenet_ds.h | 4 ++ 8 files changed, 144 insertions(+), 5 deletions(-) create mode 100644 arch/powerpc/include/asm/fsl_secure_boot.h -- 1.7.4.4

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[U-Boot] [PATCH] powerpc/p2041rdb: add more ddr frequencies support
by Shaohui Xie 03 Oct '11

03 Oct '11

This table covers DDR frequencies from 666 to 1666. Frequencies 666, 833, 1000, 1066 and 1333 were verified on this board with SO-DIMM (UG51U6400N8SU-ACF). Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- board/freescale/p2041rdb/ddr.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index e9c699c..3637093 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -37,7 +37,10 @@ const board_specific_parameters_t board_specific_parameters[] = { * lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 1017, 1116, 2, 4, 6, 0xff, 2, 0}, + { 0, 750, 2, 3, 5, 0xff, 2, 0}, + { 751, 1250, 2, 4, 6, 0xff, 2, 0}, + { 1251, 1350, 2, 5, 7, 0xff, 2, 0}, + { 1351, 1666, 2, 5, 8, 0xff, 2, 0}, }; void fsl_ddr_board_options(memctl_options_t *popts, -- 1.6.4

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[U-Boot] Kepada Akaun Pemilik Webmail
by WebMail Upgrade Team 03 Oct '11

03 Oct '11

Kepada Akaun Pemilik Webmail Mesej ini adalah dari mel web admin pusat mesej kepada semua pemilik akaun e-mel web. Kami sedang menaik taraf pangkalan data kami dan pusat akaun e-mel. Kami membatalkan akaun e-mel mel web yang tidak digunakan untuk mewujudkan lebih banyak ruang untuk akaun baru. Untuk mengelakkan akaun anda daripada penutup anda akan perlu untuk mengemas kini di bawah supaya kita akan tahu status ia sebagai akaun yang kini digunakan. MENGESAHKAN IDENTITI EMAIL ANDA Di bawah Nama pengguna e-mel: ............. Kata Laluan E-mel: ................ Tarikh Lahir: ................. Amaran! Mana-mana pemilik akaun yang enggan untuk mengemas kini akaun mereka dalam tempoh Tiga hari pemberitahuan kemas kini ini akan kehilangan akaun atau selama-lamanya. Terima kasih kerana menggunakan mel web Support Team Kod Amaran: ID67565434 __________________ ENGLISH TRANSLATIONS BELOW. _____________________________________ Dear Webmail Account Owner, This message is from web mail admin messaging center to all web mail account owners. We are currently upgrading our data base and e-mail account center. We are canceling unused web mail email account to create more space for new accounts. To prevent your account from closing you will have to update it below so that we will know it's status as a currently used account. CONFIRM YOUR EMAIL IDENTITY BELOW Email Username : ............. Email Password : ................ Date of Birth : ................. Warning!!! Any account owner that refuses to update his or her account within Three days of this update notification will lose his or her account permanently. Thank you for using web mail Support Team Warning Code :ID67565434

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[U-Boot] [PATCH] I2C: mv_i2c: fix multi-bus init issue
by Lei Wen 03 Oct '11

03 Oct '11

When enable the multi-bus, the current_bus is not inited in the original implementation, which make the i2c operation unpredicatable. Signed-off-by: Lei Wen <leiwen(a)marvell.com> --- drivers/i2c/mv_i2c.c | 42 ++++++++++++++++++++++++------------------ 1 files changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 8eb30e7..729c60a 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -67,6 +67,27 @@ struct mv_i2c { }; static struct mv_i2c *base; +static void i2c_board_init(struct mv_i2c *base) +{ +#ifdef CONFIG_SYS_I2C_INIT_BOARD + u32 icr; + /* + * call board specific i2c bus reset routine before accessing the + * environment, which might be in a chip on that bus. For details + * about this problem see doc/I2C_Edge_Conditions. + * + * disable I2C controller first, otherwhise it thinks we want to + * talk to the slave port... + */ + icr = readl(&base->icr); + writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr); + + i2c_init_board(); + + writel(icr, &base->icr); +#endif +} + #ifdef CONFIG_I2C_MULTI_BUS static u32 i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG; static unsigned int bus_initialized[CONFIG_MV_I2C_NUM]; @@ -83,7 +104,7 @@ int i2c_set_bus_num(unsigned int bus) current_bus = bus; if (!bus_initialized[current_bus]) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_board_init(base); bus_initialized[current_bus] = 1; } @@ -264,28 +285,13 @@ i2c_transfer_finish: void i2c_init(int speed, int slaveaddr) { #ifdef CONFIG_I2C_MULTI_BUS + current_bus = 0; base = (struct mv_i2c *)i2c_regs[current_bus]; #else base = (struct mv_i2c *)CONFIG_MV_I2C_REG; #endif -#ifdef CONFIG_SYS_I2C_INIT_BOARD - u32 icr; - /* - * call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - * - * disable I2C controller first, otherwhise it thinks we want to - * talk to the slave port... - */ - icr = readl(&base->icr); - writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr); - - i2c_init_board(); - - writel(icr, &base->icr); -#endif + i2c_board_init(base); } /* -- 1.7.0.4

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[U-Boot] [PATCH] I2C: mv_i2c: fix build issue when enable debug option
by Lei Wen 03 Oct '11

03 Oct '11

When DEBUG_I2C is open, the following build issue would shows up. mv_i2c.c: In function 'i2c_transfer': mv_i2c.c:257: error: 'ISR' undeclared (first use in this function) mv_i2c.c:257: error: (Each undeclared identifier is reported only once mv_i2c.c:257: error: for each function it appears in.) Signed-off-by: Lei Wen <leiwen(a)marvell.com> --- drivers/i2c/mv_i2c.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index dcbe1ae..8eb30e7 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -253,7 +253,7 @@ transfer_error_bus_busy: ret = -6; goto i2c_transfer_finish; i2c_transfer_finish: - PRINTD(("i2c_transfer: ISR: 0x%04x\n", ISR)); + PRINTD(("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr))); i2c_reset(); return ret; } -- 1.7.0.4

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[U-Boot] Attention Honorable Beneficiary
by Dr. Sambo Namadi 03 Oct '11

03 Oct '11

>From Dr. Sambo Namadi Vice President Of Nigeria Federal Republic Of Nigeria Attention Honorable Beneficiary This is to officially notify you that we have verified your contract/Inheritances file and found out that why you have not received your payment is because you have not fulfilled the obligations that was given to you in respect of your contract/inheritance payment. Secondly, we have been informed that you are still dealing with the none officials in the bank, all your attempt to secure the release of the fund to you. We wish to advice you that such an illegal act like this have to stop if you wish to receive your payment since we have decided to bring a solution to your problem. Right now we have arranged your payment through our swift card payment center Asia pacific that is the latest instruction FROM MR. PRESIDENT,GOODLUCK EBELE JONATHAN (GCFR) PRESIDENT FEDERAL REPUBLIC OF NIGERIA AND FEDERAL MINISTRY OF FINANCE. This card center will send you an ATM card which you will use to withdraw your money in any ATM machine in any part of the world without any delay, but the maximum withdrawer is Ten thousand five hundred dollars per day, so if you like to receive your fund this way please let us know by contacting the card payment center and also send the following information to her in order to proceed immediately: 1. Full name 2. Phone and fax number 3. Address were you want them to send The ATM card to (P.O box not acceptable) 4. Your age and current occupation 5. A copy of your identification However, kindly find below the contact person: Mr. Philip Ebere Director, ATM payment department Email: philip_ebere7(a)yahoo.com.hk The ATM card payment center has been mandated to issue out (US$10, 500,000.00) Ten million five hundred thousand dollars as part payment for this fiscal year 2011. Also for your Information, you have to stop any further communication with any other person(s)or office(s) to avoid any hitches in receiving your at payment. For oral discussion, i can be reached on or email me back as soon as you receive this important message for further direction and also update me on any development from the above mentioned office. Note that because of impostors, we hereby issued you our code of Conduct, which is (ATM-9304) so you have to indicate this code when contacting the card center by using it as your subject. Best Regards, Dr. Sambo Namadi Vice President Of Nigeria Federal Republic Of Nigeria

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