January 2011 - U-Boot

[U-Boot] [U-BOOT] [PATCH 1/6] Armada100: change the definition place for apb and mpmu
by Lei Wen 06 Jan '11

06 Jan '11

cpu.h should be better place to hold the structure definiton. Our intend is to make <soc>.h as a place only hold register base address. Signed-off-by: Lei Wen <leiwen(a)marvell.com> --- arch/arm/include/asm/arch-armada100/armada100.h | 57 ----------------------- arch/arm/include/asm/arch-armada100/cpu.h | 57 +++++++++++++++++++++++ 2 files changed, 57 insertions(+), 57 deletions(-) diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index d5d125a..5b709ba 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -60,62 +60,5 @@ #define ARMD1_APMU_BASE 0xD4282800 #define ARMD1_CPU_BASE 0xD4282C00 -/* - * Main Power Management (MPMU) Registers - * Refer Datasheet Appendix A.8 - */ -struct armd1mpmu_registers { - u8 pad0[0x08 - 0x00]; - u32 fccr; /*0x0008*/ - u32 pocr; /*0x000c*/ - u32 posr; /*0x0010*/ - u32 succr; /*0x0014*/ - u8 pad1[0x030 - 0x014 - 4]; - u32 gpcr; /*0x0030*/ - u8 pad2[0x200 - 0x030 - 4]; - u32 wdtpcr; /*0x0200*/ - u8 pad3[0x1000 - 0x200 - 4]; - u32 apcr; /*0x1000*/ - u32 apsr; /*0x1004*/ - u8 pad4[0x1020 - 0x1004 - 4]; - u32 aprr; /*0x1020*/ - u32 acgr; /*0x1024*/ - u32 arsr; /*0x1028*/ -}; - -/* - * APB1 Clock Reset/Control Registers - * Refer Datasheet Appendix A.10 - */ -struct armd1apb1_registers { - u32 uart1; /*0x000*/ - u32 uart2; /*0x004*/ - u32 gpio; /*0x008*/ - u32 pwm1; /*0x00c*/ - u32 pwm2; /*0x010*/ - u32 pwm3; /*0x014*/ - u32 pwm4; /*0x018*/ - u8 pad0[0x028 - 0x018 - 4]; - u32 rtc; /*0x028*/ - u32 twsi0; /*0x02c*/ - u32 kpc; /*0x030*/ - u32 timers; /*0x034*/ - u8 pad1[0x03c - 0x034 - 4]; - u32 aib; /*0x03c*/ - u32 sw_jtag; /*0x040*/ - u32 timer1; /*0x044*/ - u32 onewire; /*0x048*/ - u8 pad2[0x050 - 0x048 - 4]; - u32 asfar; /*0x050 AIB Secure First Access Reg*/ - u32 assar; /*0x054 AIB Secure Second Access Reg*/ - u8 pad3[0x06c - 0x054 - 4]; - u32 twsi1; /*0x06c*/ - u32 uart3; /*0x070*/ - u8 pad4[0x07c - 0x070 - 4]; - u32 timer2; /*0x07C*/ - u8 pad5[0x084 - 0x07c - 4]; - u32 ac97; /*0x084*/ -}; - #endif /* CONFIG_ARMADA100 */ #endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h index 0518a6a..b07ba91 100644 --- a/arch/arm/include/asm/arch-armada100/cpu.h +++ b/arch/arm/include/asm/arch-armada100/cpu.h @@ -50,4 +50,61 @@ struct armd1cpu_registers { u32 armd1_sdram_base(int); u32 armd1_sdram_size(int); +/* + * Main Power Management (MPMU) Registers + * Refer Datasheet Appendix A.8 + */ +struct armd1mpmu_registers { + u8 pad0[0x08 - 0x00]; + u32 fccr; /*0x0008*/ + u32 pocr; /*0x000c*/ + u32 posr; /*0x0010*/ + u32 succr; /*0x0014*/ + u8 pad1[0x030 - 0x014 - 4]; + u32 gpcr; /*0x0030*/ + u8 pad2[0x200 - 0x030 - 4]; + u32 wdtpcr; /*0x0200*/ + u8 pad3[0x1000 - 0x200 - 4]; + u32 apcr; /*0x1000*/ + u32 apsr; /*0x1004*/ + u8 pad4[0x1020 - 0x1004 - 4]; + u32 aprr; /*0x1020*/ + u32 acgr; /*0x1024*/ + u32 arsr; /*0x1028*/ +}; + +/* + * APB1 Clock Reset/Control Registers + * Refer Datasheet Appendix A.10 + */ +struct armd1apb1_registers { + u32 uart1; /*0x000*/ + u32 uart2; /*0x004*/ + u32 gpio; /*0x008*/ + u32 pwm1; /*0x00c*/ + u32 pwm2; /*0x010*/ + u32 pwm3; /*0x014*/ + u32 pwm4; /*0x018*/ + u8 pad0[0x028 - 0x018 - 4]; + u32 rtc; /*0x028*/ + u32 twsi0; /*0x02c*/ + u32 kpc; /*0x030*/ + u32 timers; /*0x034*/ + u8 pad1[0x03c - 0x034 - 4]; + u32 aib; /*0x03c*/ + u32 sw_jtag; /*0x040*/ + u32 timer1; /*0x044*/ + u32 onewire; /*0x048*/ + u8 pad2[0x050 - 0x048 - 4]; + u32 asfar; /*0x050 AIB Secure First Access Reg*/ + u32 assar; /*0x054 AIB Secure Second Access Reg*/ + u8 pad3[0x06c - 0x054 - 4]; + u32 twsi1; /*0x06c*/ + u32 uart3; /*0x070*/ + u8 pad4[0x07c - 0x070 - 4]; + u32 timer2; /*0x07C*/ + u8 pad5[0x084 - 0x07c - 4]; + u32 ac97; /*0x084*/ +}; + #endif /* _ARMADA100CPU_H */ -- 1.7.0.4

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[U-Boot] -a -e values for initrd on s3c2440
by Gigin Jose 06 Jan '11

06 Jan '11

Hi , What is the value of -a , -e argument for creating the initrd image on s3c2440. The base address of my RAM is 0x30000000 and the kernel (zImage) is loaded to to 0x30008000. The total RAM size is 64 MB. I am uisng uboot version 1.1.6 and linux kernel 2.6.30.4. thanks & regardsGIGIN

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[U-Boot] [PATCH] ftpmu010: fix relocation and enhance features
by Macpaul Lin 06 Jan '11

06 Jan '11

1. ftpmu010.h: fix and add definitions Enhanced for more features and asm related support according to datasheet. Note: - FTPMU010_PDLLCR0_HCLKOUTDIS is "incorrect" in datasheet. - FTPMU010_PDLLCR0_DLLFRANG is only 1 bit at bit #19. (not 20-19) - FTPMU010_PDLLCR0_HCLKOUTDIS is 4 bits at bit #20. (not 24-21) 2. ftpmu010.c: enhance features and fix relocation - The following functions is added for pmu features. ftpmu010_mfpsr_select_dev() ftpmu010_sdramhtc_set() - This patch also fix the declare statement for relocation. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Note: This patch was based on previous patch: [Patch v2 1/2] ftpmu010: support faraday ftpmu010 driver drivers/power/ftpmu010.c | 39 +++++++++++++++++++++++++++++++++++++-- drivers/power/ftpmu010.h | 38 +++++++++++++++++++++++++++++++++++--- 2 files changed, 72 insertions(+), 5 deletions(-) diff --git a/drivers/power/ftpmu010.c b/drivers/power/ftpmu010.c index 7924ac1..b072519 100644 --- a/drivers/power/ftpmu010.c +++ b/drivers/power/ftpmu010.c @@ -25,10 +25,10 @@ #include <asm/io.h> #include "ftpmu010.h" -static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - +/* OSCC: OSC Control Register */ void ftpmu010_32768osc_enable(void) { + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; unsigned int oscc; /* enable the 32768Hz oscillator */ @@ -46,8 +46,31 @@ void ftpmu010_32768osc_enable(void) writel(oscc, &pmu->OSCC); } +/* MFPSR: Multi-Function Port Setting Register */ +void ftpmu010_mfpsr_select_dev(unsigned int dev) +{ + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + unsigned int mfpsr; + + mfpsr = readl(&pmu->MFPSR); + mfpsr |= dev; + writel(mfpsr, &pmu->MFPSR); +} + +void ftpmu010_mfpsr_diselect_dev(unsigned int dev) +{ + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + unsigned int mfpsr; + + mfpsr = readl(&pmu->MFPSR); + mfpsr &= ~dev; + writel(mfpsr, &pmu->MFPSR); +} + +/* PDLLCR0: PLL/DLL Control Register 0 */ void ftpmu010_dlldis_disable(void) { + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; unsigned int pdllcr0; pdllcr0 = readl(&pmu->PDLLCR0); @@ -57,9 +80,21 @@ void ftpmu010_dlldis_disable(void) void ftpmu010_sdram_clk_disable(unsigned int cr0) { + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; unsigned int pdllcr0; pdllcr0 = readl(&pmu->PDLLCR0); pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0); writel(pdllcr0, &pmu->PDLLCR0); } + +/* SDRAMHTC: SDRAM Signal Hold Time Control */ +void ftpmu010_sdramhtc_set(unsigned int val) +{ + static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + unsigned int sdramhtc; + + sdramhtc = readl(&pmu->SDRAMHTC); + sdramhtc |= val; + writel(sdramhtc, &pmu->SDRAMHTC); +} diff --git a/drivers/power/ftpmu010.h b/drivers/power/ftpmu010.h index 8ef7a37..58c862b 100644 --- a/drivers/power/ftpmu010.h +++ b/drivers/power/ftpmu010.h @@ -126,21 +126,53 @@ struct ftpmu010 { /* * Multi-Function Port Setting Register */ +#define FTPMU010_MFPSR_DEBUGSEL (1 << 17) +#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) +#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) #define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) #define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) +#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) +#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) +#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) +#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) +#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) +#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) #define FTPMU010_MFPSR_AC97PINSEL (1 << 3) +#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) +#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) /* * PLL/DLL Control Register 0 + * Note: + * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: + * Datasheet indicated it starts at bit #21 which was wrong. + * 2. FTPMU010_PDLLCR0_DLLFRAG: + * Datasheet indicated it has 2 bit which was wrong. */ -#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf) -#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19) +#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) +#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) #define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) #define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) #define FTPMU010_PDLLCR0_DLLDIS (1 << 16) -#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff) +#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) +#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) #define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) #define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) #define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) +/* + * SDRAM Signal Hold Time Control Register + */ +#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) +#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) +#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) +#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) +#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) +#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) +#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) +#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) +#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) +#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) + #endif /* __FTPMU010_H */ -- 1.7.3.2

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Re: [U-Boot] MMC initialisation
by Reinhard Meyer 06 Jan '11

06 Jan '11

Arghhh.... Didn't see the original message was not sent to the list... So my reply was neither... On 06.01.2011 04:46, Reinhard Meyer wrote: > Dear �ڻ�, Please, dear Henry, ALL u-boot related questions MUST go to the mailing list, too. >> I will porting U-Boot mmc part to my own board, still use U-Boot as bootloader. >> First, I should research the source code of mmc part in U-Boot. >> I found top9000eval_xe board support mmc, and SoC same with mine, (arm926ejs) >> Mr. Reinhard Meyer is enthusiastic working here, Thanks a lot! >> Let me describe mmc driver init process: (version: u-boot.2010.12) >> 1. arch/arm/lib/board.c -> board_init_r() -> mmc_initialize(bd); >> 2. drivers/mmc/mmc.c -> int mmc_initialize(bd_t *bis) >> 3. board/emk/top9000/top9000.c -> int board_mmc_init(bd_t *bd) >> -> return atmel_mci_init((void *)AT91_BASE_MCI); >> 4. drivers/mmc/gen_atmel_mci.c -> int atmel_mci_init(void *regs) > ... >> mmc->init = mci_init; >> // mmc->init(mmc); // How it Implementation >> /* need to be able to pass these in on a board by board basis */ > ... > > I am not sure what your question/problem is here. > > If you wonder how and when mmc->init() is called, it is only called when the > command "mmcinfo" is given. > > This is sure not perfect, and discussions have been around about this. > "common/cmd_mmc.c" would need some rework there... > > However discussions are left open on how exactly changes should be done. > > Best Regards, > Reinhard

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[U-Boot] [PATCH 1/2] sh: Fix of shmin board
by Nobuhiro Iwamatsu 06 Jan '11

06 Jan '11

Change lib$(BOARD).a to lib$(BOARD).o Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- board/shmin/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/shmin/Makefile b/board/shmin/Makefile index be04e2c..06888cd 100644 --- a/board/shmin/Makefile +++ b/board/shmin/Makefile @@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = lib$(BOARD).o OBJS := shmin.o SOBJS := lowlevel_init.o -- 1.7.2.3

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[U-Boot] Please pull u-boot-ti/master
by s-paulraj＠ti.com 05 Jan '11

05 Jan '11

Albert, Please pull u-boot-ti/master Regards, Sandeep The following changes since commit b722e646f9a6e2ebcae4845afc596b4dad4f7bcb: Sandeep Paulraj (1): DaVinci DM6467: Enhance board Support are available in the git repository at: git://git.denx.de/u-boot-ti.git master Sandeep Paulraj (3): DaVinci DM6467: Fix Build Error DaVinci Sonata: Fix Build Error DaVinci: Remove incorrect CONFIG option arch/arm/cpu/arm926ejs/davinci/cpu.c | 14 ++++++++++++-- include/configs/davinci_sonata.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-)

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[U-Boot] How do I boot VxWorks (6.3) image with u-boot PXA320
by GCh_Niron 05 Jan '11

05 Jan '11

Hi I'm Genady Chapovetsky - s/w developer. For new project - base on Toradex Colibri SBC (PXA320 ) I should turn-on VxWorks 6.x. I have successful Uboot running. Can I ask Your recommendation for modify/customized VxWorks for loud and boot? GenaChap BR Genady Chapovetsky

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[U-Boot] Uninterruptible start
by Andrew Holt (SE) 05 Jan '11

05 Jan '11

Hi, I want disable the ability to interrupt the boot process. Setting bootdelay to 0 speeds the start, but if I hit a key at the right (or wrong, depending on point of view) I can still break out into the U-Boot command line. Any hints/tips on how to do this ? Thanks, Andrew ============================= Andrew Holt Senior Software Engineer Email: andrew.holt(a)electrans.com Phone: 0151 347 2270 Mobile: 07841 340608 Skype: andrewtholt De Omnibus Dubitandum =============================

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[U-Boot] Power-on Self Test - is it working?
by DUNDA Matthias 05 Jan '11

05 Jan '11

Hi all- I've got some issues with getting POST to work with my board (mpc85xx architecture): In my config I set #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | ..._CPU | ..._UART | ..._ETHER) I also implemented the stubs for uart_post_test and ether_post_test, as these are not covered by default. I see no output from the tests - so I can't tell, if they were even run. From my understanding, post_output_backlog should dump some results like PASSED or FAILED right after running from relocated code, but I see nothing. Another thing is the POST word address. So far I left it at the default which should locate it at CONFIG_SYS_IMMR ( = CCSRBAR = E000_0000 ) + CPM_POST_WORD_ADDR (= 80FC) which results into an address at E000_80FC, which is a reserved area in PCI configuration space - according to PowerQUICC memory map. (???) The POST documentation (README.POST) seems a little outdated - even the struct post has eight fields in the meantime - and it describes more or less the framework itself. >From what I understood from that document, the steps I did should be sufficient, but I am still missing/needing something. Cheers Matthias

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[U-Boot] [PATCH 1/2] ftpmu010: support faraday ftpmu010 driver
by Macpaul Lin 05 Jan '11

05 Jan '11

Faraday's ftpmu010 is a power managemnet unit which support cpu sleep and frequency scaling. It has been integrated into many SoC. This patch also move ftpmu010 to a proper place for later enhancement. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Note: This patch is the correct design with writing a new driver and enhanced features. Previous incorrect patch "ftpmu010: move ftpmu010 power controller to drivers/power folder" will be remove in patchwork since this is a patch moves header files without driver implementation. arch/arm/include/asm/arch-a320/ftpmu010.h | 146 ----------------------------- drivers/power/Makefile | 1 + drivers/power/ftpmu010.c | 65 +++++++++++++ drivers/power/ftpmu010.h | 146 +++++++++++++++++++++++++++++ 4 files changed, 212 insertions(+), 146 deletions(-) delete mode 100644 arch/arm/include/asm/arch-a320/ftpmu010.h create mode 100644 drivers/power/ftpmu010.c create mode 100644 drivers/power/ftpmu010.h diff --git a/arch/arm/include/asm/arch-a320/ftpmu010.h b/arch/arm/include/asm/arch-a320/ftpmu010.h deleted file mode 100644 index 8ef7a37..0000000 --- a/arch/arm/include/asm/arch-a320/ftpmu010.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert(a)faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Power Management Unit - */ -#ifndef __FTPMU010_H -#define __FTPMU010_H - -struct ftpmu010 { - unsigned int IDNMBR0; /* 0x00 */ - unsigned int reserved0; /* 0x04 */ - unsigned int OSCC; /* 0x08 */ - unsigned int PMODE; /* 0x0C */ - unsigned int PMCR; /* 0x10 */ - unsigned int PED; /* 0x14 */ - unsigned int PEDSR; /* 0x18 */ - unsigned int reserved1; /* 0x1C */ - unsigned int PMSR; /* 0x20 */ - unsigned int PGSR; /* 0x24 */ - unsigned int MFPSR; /* 0x28 */ - unsigned int MISC; /* 0x2C */ - unsigned int PDLLCR0; /* 0x30 */ - unsigned int PDLLCR1; /* 0x34 */ - unsigned int AHBMCLKOFF; /* 0x38 */ - unsigned int APBMCLKOFF; /* 0x3C */ - unsigned int DCSRCR0; /* 0x40 */ - unsigned int DCSRCR1; /* 0x44 */ - unsigned int DCSRCR2; /* 0x48 */ - unsigned int SDRAMHTC; /* 0x4C */ - unsigned int PSPR0; /* 0x50 */ - unsigned int PSPR1; /* 0x54 */ - unsigned int PSPR2; /* 0x58 */ - unsigned int PSPR3; /* 0x5C */ - unsigned int PSPR4; /* 0x60 */ - unsigned int PSPR5; /* 0x64 */ - unsigned int PSPR6; /* 0x68 */ - unsigned int PSPR7; /* 0x6C */ - unsigned int PSPR8; /* 0x70 */ - unsigned int PSPR9; /* 0x74 */ - unsigned int PSPR10; /* 0x78 */ - unsigned int PSPR11; /* 0x7C */ - unsigned int PSPR12; /* 0x80 */ - unsigned int PSPR13; /* 0x84 */ - unsigned int PSPR14; /* 0x88 */ - unsigned int PSPR15; /* 0x8C */ - unsigned int AHBDMA_RACCS; /* 0x90 */ - unsigned int reserved2; /* 0x94 */ - unsigned int reserved3; /* 0x98 */ - unsigned int JSS; /* 0x9C */ - unsigned int CFC_RACC; /* 0xA0 */ - unsigned int SSP1_RACC; /* 0xA4 */ - unsigned int UART1TX_RACC; /* 0xA8 */ - unsigned int UART1RX_RACC; /* 0xAC */ - unsigned int UART2TX_RACC; /* 0xB0 */ - unsigned int UART2RX_RACC; /* 0xB4 */ - unsigned int SDC_RACC; /* 0xB8 */ - unsigned int I2SAC97_RACC; /* 0xBC */ - unsigned int IRDATX_RACC; /* 0xC0 */ - unsigned int reserved4; /* 0xC4 */ - unsigned int USBD_RACC; /* 0xC8 */ - unsigned int IRDARX_RACC; /* 0xCC */ - unsigned int IRDA_RACC; /* 0xD0 */ - unsigned int ED0_RACC; /* 0xD4 */ - unsigned int ED1_RACC; /* 0xD8 */ -}; - -/* - * ID Number 0 Register - */ -#define FTPMU010_ID_A320A 0x03200000 -#define FTPMU010_ID_A320C 0x03200010 -#define FTPMU010_ID_A320D 0x03200030 - -/* - * OSC Control Register - */ -#define FTPMU010_OSCC_OSCH_TRI (1 << 11) -#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) -#define FTPMU010_OSCC_OSCH_OFF (1 << 8) - -#define FTPMU010_OSCC_OSCL_TRI (1 << 3) -#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) -#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) -#define FTPMU010_OSCC_OSCL_OFF (1 << 0) - -/* - * Power Mode Register - */ -#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) -#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) -#define FTPMU010_PMODE_FCS (1 << 2) -#define FTPMU010_PMODE_TURBO (1 << 1) -#define FTPMU010_PMODE_SLEEP (1 << 0) - -/* - * Power Manager Status Register - */ -#define FTPMU010_PMSR_SMR (1 << 10) - -#define FTPMU010_PMSR_RDH (1 << 2) -#define FTPMU010_PMSR_PH (1 << 1) -#define FTPMU010_PMSR_CKEHLOW (1 << 0) - -/* - * Multi-Function Port Setting Register - */ -#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) -#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) -#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) - -/* - * PLL/DLL Control Register 0 - */ -#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf) -#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19) -#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) -#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) -#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) -#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff) -#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) -#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) -#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) - -#endif /* __FTPMU010_H */ diff --git a/drivers/power/Makefile b/drivers/power/Makefile index c9ba1ae..ead00f8 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libpower.o +COBJS-$(CONFIG_FTPMU010_POWER) += ftpmu010.o COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o COBJS-$(CONFIG_TWL6030_POWER) += twl6030.o diff --git a/drivers/power/ftpmu010.c b/drivers/power/ftpmu010.c new file mode 100644 index 0000000..d4bc0f7 --- /dev/null +++ b/drivers/power/ftpmu010.c @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * Copyright (C) 2010 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro(a)andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/io.h> +#include "ftpmu010.h" + +static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + +void ftpmu010_32768osc_enable(void) +{ + unsigned int oscc; + + /* enable the 32768Hz oscillator */ + oscc = readl(&pmu->OSCC); + oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); + writel(oscc, &pmu->OSCC); + + /* wait until ready */ + while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) + ; + + /* select 32768Hz oscillator */ + oscc = readl(&pmu->OSCC); + oscc |= FTPMU010_OSCC_OSCL_RTCLSEL; + writel(oscc, &pmu->OSCC); +} + +void ftpmu010_dlldis_disable(void) +{ + unsigned int pdllcr0; + + pdllcr0 = readl(&pmu->PDLLCR0); + pdllcr0 |= FTPMU010_PDLLCR0_DLLDIS; + writel(pdllcr0, &pmu->PDLLCR0); +} + +void ftpmu010_sdram_clk_disable(unsigned int cr0) +{ + unsigned int pdllcr0; + + pdllcr0 = readl(&pmu->PDLLCR0); + pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0); + writel(pdllcr0, &pmu->PDLLCR0); +} diff --git a/drivers/power/ftpmu010.h b/drivers/power/ftpmu010.h new file mode 100644 index 0000000..8ef7a37 --- /dev/null +++ b/drivers/power/ftpmu010.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Power Management Unit + */ +#ifndef __FTPMU010_H +#define __FTPMU010_H + +struct ftpmu010 { + unsigned int IDNMBR0; /* 0x00 */ + unsigned int reserved0; /* 0x04 */ + unsigned int OSCC; /* 0x08 */ + unsigned int PMODE; /* 0x0C */ + unsigned int PMCR; /* 0x10 */ + unsigned int PED; /* 0x14 */ + unsigned int PEDSR; /* 0x18 */ + unsigned int reserved1; /* 0x1C */ + unsigned int PMSR; /* 0x20 */ + unsigned int PGSR; /* 0x24 */ + unsigned int MFPSR; /* 0x28 */ + unsigned int MISC; /* 0x2C */ + unsigned int PDLLCR0; /* 0x30 */ + unsigned int PDLLCR1; /* 0x34 */ + unsigned int AHBMCLKOFF; /* 0x38 */ + unsigned int APBMCLKOFF; /* 0x3C */ + unsigned int DCSRCR0; /* 0x40 */ + unsigned int DCSRCR1; /* 0x44 */ + unsigned int DCSRCR2; /* 0x48 */ + unsigned int SDRAMHTC; /* 0x4C */ + unsigned int PSPR0; /* 0x50 */ + unsigned int PSPR1; /* 0x54 */ + unsigned int PSPR2; /* 0x58 */ + unsigned int PSPR3; /* 0x5C */ + unsigned int PSPR4; /* 0x60 */ + unsigned int PSPR5; /* 0x64 */ + unsigned int PSPR6; /* 0x68 */ + unsigned int PSPR7; /* 0x6C */ + unsigned int PSPR8; /* 0x70 */ + unsigned int PSPR9; /* 0x74 */ + unsigned int PSPR10; /* 0x78 */ + unsigned int PSPR11; /* 0x7C */ + unsigned int PSPR12; /* 0x80 */ + unsigned int PSPR13; /* 0x84 */ + unsigned int PSPR14; /* 0x88 */ + unsigned int PSPR15; /* 0x8C */ + unsigned int AHBDMA_RACCS; /* 0x90 */ + unsigned int reserved2; /* 0x94 */ + unsigned int reserved3; /* 0x98 */ + unsigned int JSS; /* 0x9C */ + unsigned int CFC_RACC; /* 0xA0 */ + unsigned int SSP1_RACC; /* 0xA4 */ + unsigned int UART1TX_RACC; /* 0xA8 */ + unsigned int UART1RX_RACC; /* 0xAC */ + unsigned int UART2TX_RACC; /* 0xB0 */ + unsigned int UART2RX_RACC; /* 0xB4 */ + unsigned int SDC_RACC; /* 0xB8 */ + unsigned int I2SAC97_RACC; /* 0xBC */ + unsigned int IRDATX_RACC; /* 0xC0 */ + unsigned int reserved4; /* 0xC4 */ + unsigned int USBD_RACC; /* 0xC8 */ + unsigned int IRDARX_RACC; /* 0xCC */ + unsigned int IRDA_RACC; /* 0xD0 */ + unsigned int ED0_RACC; /* 0xD4 */ + unsigned int ED1_RACC; /* 0xD8 */ +}; + +/* + * ID Number 0 Register + */ +#define FTPMU010_ID_A320A 0x03200000 +#define FTPMU010_ID_A320C 0x03200010 +#define FTPMU010_ID_A320D 0x03200030 + +/* + * OSC Control Register + */ +#define FTPMU010_OSCC_OSCH_TRI (1 << 11) +#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) +#define FTPMU010_OSCC_OSCH_OFF (1 << 8) + +#define FTPMU010_OSCC_OSCL_TRI (1 << 3) +#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) +#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) +#define FTPMU010_OSCC_OSCL_OFF (1 << 0) + +/* + * Power Mode Register + */ +#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) +#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) +#define FTPMU010_PMODE_FCS (1 << 2) +#define FTPMU010_PMODE_TURBO (1 << 1) +#define FTPMU010_PMODE_SLEEP (1 << 0) + +/* + * Power Manager Status Register + */ +#define FTPMU010_PMSR_SMR (1 << 10) + +#define FTPMU010_PMSR_RDH (1 << 2) +#define FTPMU010_PMSR_PH (1 << 1) +#define FTPMU010_PMSR_CKEHLOW (1 << 0) + +/* + * Multi-Function Port Setting Register + */ +#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) + +/* + * PLL/DLL Control Register 0 + */ +#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf) +#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19) +#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) +#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) +#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) +#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff) +#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) +#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) +#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) + +#endif /* __FTPMU010_H */ -- 1.7.3.2

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