January 2011 - U-Boot

[U-Boot] Microsoft New Year Promotion
by MICROSOFT EMAIL PROMOTION 10 Jan '11

10 Jan '11

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[U-Boot] [PATCH v2 1/3] MX5: Add initial support for MX53 processor
by Jason Liu 10 Jan '11

10 Jan '11

Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro --- Changes for v2: -address some comments of Stefano Babic, remove the is_soc_type and use #ifdef, -address the comments of stefano, remove CPU_TYPE def, remove something like /*0x760*/ comments in mx5x_pins.h. -fix the build break for vision2 board Signed-off-by: Jason Liu <r64343(a)freescale.com> --- arch/arm/cpu/armv7/mx5/iomux.c | 30 ++- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 91 +++--- arch/arm/cpu/armv7/mx5/soc.c | 22 +- arch/arm/include/asm/arch-mx5/asm-offsets.h | 5 + arch/arm/include/asm/arch-mx5/imx-regs.h | 78 ++--- arch/arm/include/asm/arch-mx5/iomux.h | 102 ------ arch/arm/include/asm/arch-mx5/mx5x_pins.h | 469 ++++++++++++++++++++++++++- include/configs/mx51evk.h | 3 +- include/configs/vision2.h | 3 +- 9 files changed, 599 insertions(+), 204 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c old mode 100644 new mode 100755 index e8928d5..d4e3bbb --- a/arch/arm/cpu/armv7/mx5/iomux.c +++ b/arch/arm/cpu/armv7/mx5/iomux.c @@ -34,7 +34,7 @@ enum iomux_reg_addr { IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR, IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END, IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START, - IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR, + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START, }; #define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1) @@ -44,11 +44,12 @@ static inline u32 get_mux_reg(iomux_pin_name_t pin) { u32 mux_reg = PIN_TO_IOMUX_MUX(pin); +#if defined(CONFIG_MX51) if (is_soc_rev(CHIP_REV_2_0) < 0) { /* * Fixup register address: - * i.MX51 TO1 has offset with the register - * which is define as TO2. + * i.MX51 TO1 has offset with the register + * which is define as TO2. */ if ((pin == MX51_PIN_NANDF_RB5) || (pin == MX51_PIN_NANDF_RB6) || @@ -59,6 +60,7 @@ static inline u32 get_mux_reg(iomux_pin_name_t pin) else if (mux_reg >= 0x130) mux_reg += 0xC; } +#endif mux_reg += IOMUXSW_MUX_CTL; return mux_reg; } @@ -68,11 +70,12 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin) { u32 pad_reg = PIN_TO_IOMUX_PAD(pin); +#if defined(CONFIG_MX51) if (is_soc_rev(CHIP_REV_2_0) < 0) { /* * Fixup register address: - * i.MX51 TO1 has offset with the register - * which is define as TO2. + * i.MX51 TO1 has offset with the register + * which is define as TO2. */ if ((pin == MX51_PIN_NANDF_RB5) || (pin == MX51_PIN_NANDF_RB6) || @@ -91,6 +94,7 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin) else pad_reg += 8; } +#endif pad_reg += IOMUXSW_PAD_CTL; return pad_reg; } @@ -98,10 +102,13 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin) /* Get the last iomux register address */ static inline u32 get_mux_end(void) { +#if defined(CONFIG_MX51) if (is_soc_rev(CHIP_REV_2_0) < 0) return IOMUXC_BASE_ADDR + (0x3F8 - 4); else return IOMUXC_BASE_ADDR + (0x3F0 - 4); +#endif + return IOMUXSW_MUX_END; } /* @@ -164,3 +171,16 @@ unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) u32 pad_reg = get_pad_reg(pin); return readl(pad_reg); } + +/* + * This function configures daisy-chain + * + * @param input index of input select register + * @param config the binary value of elements + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + writel(config, reg); +} diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S old mode 100644 new mode 100755 index e984870..96ebfe2 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -70,6 +70,7 @@ /* M4IF setup */ .macro init_m4if +#ifdef CONFIG_MX51 /* VPU and IPU given higher priority (0x4) * IPU accesses with ID=0x1 given highest priority (=0xA) */ @@ -87,27 +88,31 @@ ldr r1, =0x001901A3 str r1, [r0, #0x48] +#endif .endm /* init_m4if */ .macro setup_pll pll, freq - ldr r2, =\pll + ldr r0, =\pll ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ + str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ mov r1, #0x2 - str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ - str r3, [r2, #PLL_DP_OP] - str r3, [r2, #PLL_DP_HFS_OP] + ldr r1, W_DP_OP_\freq + str r1, [r0, #PLL_DP_OP] + str r1, [r0, #PLL_DP_HFS_OP] - str r4, [r2, #PLL_DP_MFD] - str r4, [r2, #PLL_DP_HFS_MFD] + ldr r1, W_DP_MFD_\freq + str r1, [r0, #PLL_DP_MFD] + str r1, [r0, #PLL_DP_HFS_MFD] - str r5, [r2, #PLL_DP_MFN] - str r5, [r2, #PLL_DP_HFS_MFN] + ldr r1, W_DP_MFN_\freq + str r1, [r0, #PLL_DP_MFN] + str r1, [r0, #PLL_DP_HFS_MFN] ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] -1: ldr r1, [r2, #PLL_DP_CTL] + str r1, [r0, #PLL_DP_CTL] +1: ldr r1, [r0, #PLL_DP_CTL] ands r1, r1, #0x1 beq 1b .endm @@ -115,6 +120,7 @@ .macro init_clock ldr r0, =CCM_BASE_ADDR +#if defined(CONFIG_MX51) /* Gate of clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] @@ -141,19 +147,16 @@ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b +#endif /* Switch ARM to step clock */ mov r1, #0x4 str r1, [r0, #CLKCTL_CCSR] - mov r3, #DP_OP_800 - mov r4, #DP_MFD_800 - mov r5, #DP_MFN_800 - setup_pll PLL1_BASE_ADDR - mov r3, #DP_OP_665 - mov r4, #DP_MFD_665 - mov r5, #DP_MFN_665 - setup_pll PLL3_BASE_ADDR + setup_pll PLL1_BASE_ADDR, 800 + +#if defined(CONFIG_MX51) + setup_pll PLL3_BASE_ADDR, 665 /* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR @@ -162,10 +165,7 @@ str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] - mov r3, #DP_OP_665 - mov r4, #DP_MFD_665 - mov r5, #DP_MFN_665 - setup_pll PLL2_BASE_ADDR + setup_pll PLL2_BASE_ADDR, 665 /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR @@ -174,12 +174,8 @@ ldr r1, =0x000020C0 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] - - mov r3, #DP_OP_216 - mov r4, #DP_MFD_216 - mov r5, #DP_MFN_216 - setup_pll PLL3_BASE_ADDR - +#endif + setup_pll PLL3_BASE_ADDR, 216 /* Set the platform clock dividers */ ldr r0, =ARM_BASE_ADDR @@ -188,18 +184,23 @@ ldr r0, =CCM_BASE_ADDR +#if defined(CONFIG_MX51) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ ldr r1, =0x0 ldr r3, [r1, #ROM_SI_REV] cmp r3, #0x10 movls r1, #0x1 movhi r1, #0 - str r1, [r0, #CLKCTL_CACRR] +#else + mov r1, #0 +#endif + str r1, [r0, #CLKCTL_CACRR] /* Switch ARM back to PLL 1 */ mov r1, #0 str r1, [r0, #CLKCTL_CCSR] +#if defined(CONFIG_MX51) /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ ldr r1, =0x000020C2 @@ -208,6 +209,7 @@ /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ ldr r1, =CONFIG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] +#endif /* Restore the default values in the Gate registers */ ldr r1, =0xFFFFFFFF @@ -218,13 +220,23 @@ str r1, [r0, #CLKCTL_CCGR4] str r1, [r0, #CLKCTL_CCGR5] str r1, [r0, #CLKCTL_CCGR6] +#if defined(CONFIG_MX53) + str r1, [r0, #CLKCTL_CCGR7] +#endif +#if defined(CONFIG_MX51) /* Use PLL 2 for UART's, get 66.5MHz from it */ ldr r1, =0xA5A2A020 str r1, [r0, #CLKCTL_CSCMR1] ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] - +#elif defined(CONFIG_MX53) + ldr r1, [r0, #CLKCTL_CSCDR1] + orr r1, r1, #0x3f + eor r1, r1, #0x3f + orr r1, r1, #0x21 + str r1, [r0, #CLKCTL_CSCDR1] +#endif /* make sure divider effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 @@ -249,6 +261,7 @@ .globl lowlevel_init lowlevel_init: +#if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #(1 << 23) @@ -256,6 +269,7 @@ lowlevel_init: ldr r1, [r0, #0x4] orr r1, r1, #(1 << 23) str r1, [r0, #0x4] +#endif init_l2cc @@ -269,9 +283,12 @@ lowlevel_init: mov pc,lr /* Board level setting value */ -DDR_PERCHARGE_CMD: .word 0x04008008 -DDR_REFRESH_CMD: .word 0x00008010 -DDR_LMR1_W: .word 0x00338018 -DDR_LMR_CMD: .word 0xB2220000 -DDR_TIMING_W: .word 0xB02567A9 -DDR_MISC_W: .word 0x000A0104 +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_665: .word DP_OP_665 +W_DP_MFD_665: .word DP_MFD_665 +W_DP_MFN_665: .word DP_MFN_665 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216 diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 2900119..09500b3 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -33,17 +33,20 @@ #include <fsl_esdhc.h> #endif -#if defined(CONFIG_MX51) -#define CPU_TYPE 0x51000 -#else +#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53)) #error "CPU_TYPE not defined" #endif u32 get_cpu_rev(void) { - int system_rev = CPU_TYPE; +#ifdef CONFIG_MX51 + int system_rev = 0x51000; +#else + int system_rev = 0x53000; +#endif int reg = __raw_readl(ROM_SI_REV); +#if defined(CONFIG_MX51) switch (reg) { case 0x02: system_rev |= CHIP_REV_1_1; @@ -57,11 +60,20 @@ u32 get_cpu_rev(void) case 0x20: system_rev |= CHIP_REV_3_0; break; - return system_rev; default: system_rev |= CHIP_REV_1_0; break; } +#else + switch (reg) { + case 0x20: + system_rev |= CHIP_REV_2_0; + break; + default: + system_rev |= CHIP_REV_1_0; + break; + } +#endif return system_rev; } diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h index afd2728..2258f2f 100644 --- a/arch/arm/include/asm/arch-mx5/asm-offsets.h +++ b/arch/arm/include/asm/arch-mx5/asm-offsets.h @@ -37,7 +37,12 @@ #define CLKCTL_CCGR4 0x78 #define CLKCTL_CCGR5 0x7C #define CLKCTL_CCGR6 0x80 +#if defined(CONFIG_MX53) +#define CLKCTL_CCGR7 0x84 #define CLKCTL_CMEOR 0x84 +#elif defined(CONFIG_MX51) +#define CLKCTL_CMEOR 0x84 +#endif /* DPLL */ #define PLL_DP_CTL 0x00 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h old mode 100644 new mode 100755 index b45026d..8be7f4b --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -20,38 +20,36 @@ * MA 02111-1307 USA */ -#ifndef __ASM_ARCH_MXC_MX51_H__ -#define __ASM_ARCH_MXC_MX51_H__ +#ifndef __ASM_ARCH_MX5_IMX_REGS_H__ +#define __ASM_ARCH_MX5_IMX_REGS_H__ -/* - * IRAM - */ +#if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ -#define IRAM_SIZE 0x00020000 /* 128 KB */ -/* - * Graphics Memory of GPU - */ -#define GPU_BASE_ADDR 0x20000000 -#define GPU_CTRL_BASE_ADDR 0x30000000 #define IPU_CTRL_BASE_ADDR 0x40000000 -/* - * Debug - */ -#define DEBUG_BASE_ADDR 0x60000000 -#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) -#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) -#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) -#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) -#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) -#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) -#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) -#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) +#define SPBA0_BASE_ADDR 0x70000000 +#define AIPS1_BASE_ADDR 0x73F00000 +#define AIPS2_BASE_ADDR 0x83F00000 +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define NFC_BASE_ADDR_AXI 0xCFFF0000 +#elif defined(CONFIG_MX53) +#define IPU_CTRL_BASE_ADDR 0x18000000 +#define SPBA0_BASE_ADDR 0x50000000 +#define AIPS1_BASE_ADDR 0x53F00000 +#define AIPS2_BASE_ADDR 0x63F00000 +#define CSD0_BASE_ADDR 0x70000000 +#define CSD1_BASE_ADDR 0xB0000000 +#define NFC_BASE_ADDR_AXI 0xF7FF0000 +#define IRAM_BASE_ADDR 0xF8000000 +#else +#error "CPU_TYPE not defined" +#endif + +#define IRAM_SIZE 0x00020000 /* 128 KB */ /* * SPBA global module enabled #0 */ -#define SPBA0_BASE_ADDR 0x70000000 - #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) @@ -68,8 +66,6 @@ /* * AIPS 1 */ -#define AIPS1_BASE_ADDR 0x73F00000 - #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) @@ -91,11 +87,14 @@ #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) +#if defined(CONFIG_MX53) +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#endif /* * AIPS 2 */ -#define AIPS2_BASE_ADDR 0x83F00000 - #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) @@ -129,26 +128,7 @@ #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) -#define TZIC_BASE_ADDR 0x8FFFC000 - /* - * Memory regions and CS - */ -#define CSD0_BASE_ADDR 0x90000000 -#define CSD1_BASE_ADDR 0xA0000000 -#define CS0_BASE_ADDR 0xB0000000 -#define CS1_BASE_ADDR 0xB8000000 -#define CS2_BASE_ADDR 0xC0000000 -#define CS3_BASE_ADDR 0xC8000000 -#define CS4_BASE_ADDR 0xCC000000 -#define CS5_BASE_ADDR 0xCE000000 - -/* - * NFC - */ -#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ - -/*! * Number of GPIO port as defined in the IC Spec */ #define GPIO_PORT_NUM 4 @@ -311,4 +291,4 @@ struct fuse_bank1_regs { #endif /* __ASSEMBLER__*/ -#endif /* __ASM_ARCH_MXC_MX51_H__ */ +#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h index 0d91a24..760371b 100644 --- a/arch/arm/include/asm/arch-mx5/iomux.h +++ b/arch/arm/include/asm/arch-mx5/iomux.h @@ -70,108 +70,6 @@ typedef enum iomux_pad_config { PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ } iomux_pad_config_t; -/* various IOMUX input select register index */ -typedef enum iomux_input_select { - MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, - MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, - MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, - MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, - /* TO2 */ - MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, - MUX_IN_FEC_FEC_COL_SELECT_INPUT, - MUX_IN_FEC_FEC_CRS_SELECT_INPUT, - MUX_IN_FEC_FEC_MDI_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, - MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, - /* TO2 */ - MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, - MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, - MUX_INPUT_NUM_MUX, -} iomux_input_select_t; - /* various IOMUX input functions */ typedef enum iomux_input_config { INPUT_CTL_PATH0 = 0x0, diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h old mode 100644 new mode 100755 index a564fce..4e3a31b --- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h +++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h @@ -86,12 +86,22 @@ #define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) #define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) -#define NON_MUX_I PIN_TO_MUX_MASK +#define NON_MUX_I PIN_TO_MUX_MASK +#define NON_PAD_I PIN_TO_PAD_MASK + +#if defined(CONFIG_MX51) #define MUX_I_START 0x001C #define PAD_I_START 0x3F0 #define INPUT_CTL_START 0x8C4 -#define INPUT_CTL_START_TO1 0x928 #define MUX_I_END (PAD_I_START - 4) +#elif defined(CONFIG_MX53) +#define MUX_I_START 0x0020 +#define PAD_I_START 0x348 +#define INPUT_CTL_START 0x730 +#define MUX_I_END (PAD_I_START - 4) +#else +#error "CPU_TYPE not defined" +#endif #define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ @@ -115,7 +125,7 @@ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated * value is constructed based on the rules described above. */ -enum iomux_pins { +enum { MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8), MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8), MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8), @@ -414,5 +424,458 @@ enum iomux_pins { MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0), }; +enum { + MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348), + MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C), + MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350), + MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354), + MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358), + MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C), + MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360), + MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364), + MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368), + MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C), + MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370), + MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374), + MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378), + MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C), + MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380), + MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384), + MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388), + MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C), + MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390), + MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394), + MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398), + MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C), + MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0), + MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4), + MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8), + MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC), + MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0), + MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4), + MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8), + MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC), + MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0), + MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4), + MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8), + MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC), + MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0), + MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4), + MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8), + MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC), + MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0), + MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4), + MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8), + MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC), + MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0), + MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4), + MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8), + MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC), + MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400), + MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404), + MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408), + MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C), + MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410), + MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414), + MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418), + MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C), + MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420), + MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424), + MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428), + MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C), + MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430), + MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434), + MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438), + MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C), + MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440), + MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444), + MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448), + MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C), + MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450), + MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454), + MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458), + MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C), + MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460), + MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464), + MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468), + MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C), + MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470), + MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474), + MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478), + MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C), + MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480), + MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484), + MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488), + MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C), + MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490), + MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494), + MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498), + MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C), + MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0), + MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4), + MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8), + MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC), + MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0), + MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4), + MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8), + MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC), + MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0), + MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4), + MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8), + MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC), + MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0), + MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4), + MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8), + MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC), + MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0), + MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4), + MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8), + MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC), + MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0), + MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4), + MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8), + MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC), + MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500), + MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504), + MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508), + MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C), + MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510), + MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514), + MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518), + MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C), + MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520), + MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524), + MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528), + MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C), + MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530), + MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534), + MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538), + MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C), + MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I), + MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I), + MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I), + MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I), + MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I), + MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I), + MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I), + MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I), + MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I), + MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I), + MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540), + MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544), + MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548), + MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C), + MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550), + MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554), + MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558), + MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C), + MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560), + MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564), + MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568), + MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C), + MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570), + MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574), + MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578), + MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C), + MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580), + MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584), + MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588), + MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C), + MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590), + MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594), + MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598), + MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C), + MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0), + MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4), + MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8), + MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC), + MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0), + MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4), + MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8), + MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC), + MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0), + MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4), + MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8), + MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC), + MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0), + MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4), + MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8), + MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC), + MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0), + MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4), + MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8), + MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC), + MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0), + MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4), + MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8), + MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC), + MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600), + MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604), + MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608), + MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C), + MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610), + MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614), + MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618), + MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C), + MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620), + MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624), + MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628), + MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C), + MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630), + MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634), + MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638), + MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C), + MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640), + MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644), + MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648), + MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C), + MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650), + MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654), + MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658), + MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C), + MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660), + MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664), + MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668), + MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C), + MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670), + MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674), + MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678), + MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C), + MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680), + MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684), + MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688), + MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C), + MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690), + MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694), + MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698), + MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C), + MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0), + MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4), + MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8), + MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC), + MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0), + MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4), + MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8), + MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC), + MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0), + MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4), + MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8), + MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC), + MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0), + MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4), + MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8), + MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC), + MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0), + MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4), + MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8), + MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC), + MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0), + MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4), + MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC), + MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708), + MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C), + MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710), + MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714), + MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718), + MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C), + MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720), + MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724), + MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728), + MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C), +}; +/* various IOMUX input select register index */ +typedef enum iomux_input_select { + MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, + MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, + MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, + MX51_CCM_IPP_DI_CLK_SELECT_INPUT, + /* TO2 */ + MX51_CCM_IPP_DI1_CLK_SELECT_INPUT, + MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MX51_CSPI_IPP_IND_MISO_SELECT_INPUT, + MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, + /* TO2 */ + MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, + MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT, + MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, + MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, + MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, + MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, + MX51_FEC_FEC_COL_SELECT_INPUT, + MX51_FEC_FEC_CRS_SELECT_INPUT, + MX51_FEC_FEC_MDI_SELECT_INPUT, + MX51_FEC_FEC_RDATA_0_SELECT_INPUT, + MX51_FEC_FEC_RDATA_1_SELECT_INPUT, + MX51_FEC_FEC_RDATA_2_SELECT_INPUT, + MX51_FEC_FEC_RDATA_3_SELECT_INPUT, + MX51_FEC_FEC_RX_CLK_SELECT_INPUT, + MX51_FEC_FEC_RX_DV_SELECT_INPUT, + MX51_FEC_FEC_RX_ER_SELECT_INPUT, + MX51_FEC_FEC_TX_CLK_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, + MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, + /* TO2 */ + MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + /* TO2 */ + MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, + /* TO2 */ + MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, + MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, + MX51_I2C1_IPP_SCL_IN_SELECT_INPUT, + MX51_I2C1_IPP_SDA_IN_SELECT_INPUT, + MX51_I2C2_IPP_SCL_IN_SELECT_INPUT, + MX51_I2C2_IPP_SDA_IN_SELECT_INPUT, + MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + MX51_KPP_IPP_IND_COL_6_SELECT_INPUT, + MX51_KPP_IPP_IND_COL_7_SELECT_INPUT, + MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, + MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, + MX51PUT_NUM_MUX, + /* MX53 */ + MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT, + MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT, + MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I, + MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I, + MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT, + MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT, + MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT, + MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT, + MX53_CCM_IPP_DI1_CLK_SELECT_INPUT, + MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT, + MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT, + MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MX53_CSPI_IPP_IND_MISO_SELECT_INPUT, + MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT, + MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, + MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT, + MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT, + MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT, + MX53_ESAI1_IPP_IND_FST_SELECT_INPUT, + MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT, + MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT, + MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT, + MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT, + MX53_FEC_FEC_COL_SELECT_INPUT, + MX53_FEC_FEC_MDI_SELECT_INPUT, + MX53_FEC_FEC_RX_CLK_SELECT_INPUT, + MX53_FIRI_IPP_IND_RXD_SELECT_INPUT, + MX53_GPC_PMIC_RDY_SELECT_INPUT, + MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, + MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, + MX53_I2C3_IPP_SCL_IN_SELECT_INPUT, + MX53_I2C3_IPP_SDA_IN_SELECT_INPUT, + MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT, + MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT, + MX53_KPP_IPP_IND_COL_5_SELECT_INPUT, + MX53_KPP_IPP_IND_COL_6_SELECT_INPUT, + MX53_KPP_IPP_IND_COL_7_SELECT_INPUT, + MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MX53_MLB_MLBCLK_IN_SELECT_INPUT, + MX53_MLB_MLBDAT_IN_SELECT_INPUT, + MX53_MLB_MLBSIG_IN_SELECT_INPUT, + MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT, + MX53_SDMA_EVENTS_14_SELECT_INPUT, + MX53_SDMA_EVENTS_15_SELECT_INPUT, + MX53_SPDIF_SPDIF_IN1_SELECT_INPUT, + MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT, + MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT, + MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, + MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT, + MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT, +} iomux_input_select_t; + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h old mode 100644 new mode 100755 index b4e5738..3d6d390 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -24,8 +24,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/imx-regs.h> - /* High Level Configuration Options */ #define CONFIG_MX51 /* in a mx51 */ @@ -37,6 +35,7 @@ #define CONFIG_L2_OFF +#include <asm/arch/imx-regs.h> /* * Disabled for now due to build problems under Debian and a significant * increase in the final file size: 144260 vs. 109536 Bytes. diff --git a/include/configs/vision2.h b/include/configs/vision2.h index a5c116b..4c8e7fa 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -24,11 +24,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/imx-regs.h> #define CONFIG_MX51 /* in a mx51 */ #define CONFIG_L2_OFF +#include <asm/arch/imx-regs.h> + #define CONFIG_SYS_MX5_HCLK 24000000 #define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO -- 1.7.0.4

5 13

[U-Boot] [PATCH v2] microblaze: Disabling interrupt should return 1 if was enabled
by Michal Simek 09 Jan '11

09 Jan '11

Microblaze implement enable/disable interrupts through MSR that's why disable_interrupts function should return 1 when interrupt was enabled. Return 0 when interrupt was disabled. Signed-off-by: John Linn <john.linn(a)xilinx.com> Signed-off-by: Michal Simek <monstr(a)monstr.eu> --- arch/microblaze/cpu/interrupts.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c index e9d53c1..054e09f 100644 --- a/arch/microblaze/cpu/interrupts.c +++ b/arch/microblaze/cpu/interrupts.c @@ -41,8 +41,10 @@ void enable_interrupts (void) int disable_interrupts (void) { + unsigned int msr; + MFS(msr, rmsr); MSRCLR(0x2); - return 0; + return ((msr & 0x2) != 0); } #ifdef CONFIG_SYS_INTC_0 -- 1.5.5.6

4 5

[U-Boot] [PATCH v3] ftgmac100: support of gigabit eth ftgmac100
by Macpaul Lin 09 Jan '11

09 Jan '11

Add Faraday's ftgmac100 (gigabit ethernet) MAC controller's driver. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Changes for v2: - Coding Style cleanup - Makefile Order sorted - Volatile statement eliminated - Error handling added - Autonegotiation timeout value rechecked - Link speed detection code is reduced - Logic of autonegotiation and Link speed update reorganized - Redundent registers offset table cleared - The explaination of sub configuration of this driver has moved into README Changes for v3: - Coding Style clean up about - 2 continue blank line - incorrect multi-line comment style - useless else statement and return value statement - make multi-line statement into single line which doesn't exceed 80 chars - brance with multi-line statement (comments included before one line code) README | 12 + drivers/net/Makefile | 1 + drivers/net/ftgmac100.c | 570 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ftgmac100.h | 255 +++++++++++++++++++++ include/netdev.h | 1 + 5 files changed, 839 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ftgmac100.c create mode 100644 drivers/net/ftgmac100.h diff --git a/README b/README index 68f5fb0..d7a23cd 100644 --- a/README +++ b/README @@ -861,6 +861,18 @@ The following options need to be configured: Define this to use i/o functions instead of macros (some hardware wont work with macros) + CONFIG_FTGMAC100 + Support for Faraday's FTGMAC100 Gigabit SoC Ethernet + + CONFIG_FTGMAC100_EGIGA + Define this to use GE link update with gigabit PHY. + Define this if FTGMAC100 is connected to gigabit PHY. + If your system has 10/100 PHY only, it might not occur + wrong behavior. Because PHY usually return timeout or + useless data when polling gigabit status and gigabit + control registers. This behavior won't affect the + correctnessof 10/100 link speed update. + CONFIG_SMC911X Support for SMSC's LAN911x and LAN921x chips diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b605eea..fd9d0b4 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o +COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c new file mode 100644 index 0000000..dc7a80e --- /dev/null +++ b/drivers/net/ftgmac100.c @@ -0,0 +1,570 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/io.h> +#include <linux/mii.h> + +#include "ftgmac100.h" + +#define ETH_ZLEN 60 + +#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) + +/* RBSR - hw default init value is also 0x640 */ +#define RBSR_DEFAULT_VALUE 0x640 + +/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ +#define PKTBUFSTX 4 /* must be power of 2 */ + +struct ftgmac100_data { + struct ftgmac100_txdes txdes[PKTBUFSTX]; + struct ftgmac100_rxdes rxdes[PKTBUFSRX]; + int tx_index; + int rx_index; + int phy_addr; +}; + +/* + * struct mii_bus functions + */ +static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr, + int regnum) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIRD; + + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { + int data; + + data = readl(&ftgmac100->phydata); + return FTGMAC100_PHYDATA_MIIRDATA(data); + } + + mdelay(10); + } + + debug("mdio read timed out\n"); + return -1; +} + +static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr, + int regnum, u16 value) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int data; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIWR; + + data = FTGMAC100_PHYDATA_MIIWDATA(value); + + writel(data, &ftgmac100->phydata); + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) { + debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \ + "phy_addr: %x\n", phy_addr); + return 0; + } + + mdelay(1); + } + + debug("mdio write timed out\n"); + return -1; +} + +int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value) +{ + *value = ftgmac100_mdiobus_read(dev , addr, reg); + + if (*value == -1) + return -1; + + return 0; +} + +int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value) +{ + if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1) + return -1; + + return 0; +} + +static int ftgmac100_phy_reset(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + int i; + u16 status, adv; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + + ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv); + + printf("%s: Starting autonegotiation...\n", dev->name); + + ftgmac100_phy_write(dev, priv->phy_addr, + MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + + if (status & BMSR_ANEGCOMPLETE) + break; + mdelay(1); + } + + if (status & BMSR_ANEGCOMPLETE) { + printf("%s: Autonegotiation complete\n", dev->name); + } else { + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->name, status); + return 0; + } + + return 1; +} + +static int ftgmac100_phy_init(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + + int phy_addr; + u16 phy_id, status, adv, lpa, stat_ge; + int media, speed, duplex; + int i; + + /* Check if the PHY is up to snuff... */ + for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) { + + ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id); + + /* + * When it is unable to found PHY, + * the interface usually return 0xffff or 0x0000 + */ + if (phy_id != 0xffff && phy_id != 0x0) { + printf("%s: found PHY at 0x%02x\n", + dev->name, phy_addr); + priv->phy_addr = phy_addr; + break; + } + } + + if (phy_id == 0xffff || phy_id == 0x0) { + printf("%s: no PHY present\n", dev->name); + return 0; + } + + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + ftgmac100_phy_reset(dev); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, + MII_BMSR, &status); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + + if (!(status & BMSR_LSTATUS)) { + printf("%s: link down\n", dev->name); + return 0; + } + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, + MII_STAT1000, &stat_ge); + + speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF) + ? 1 : 0); + + duplex = ((stat_ge & LPA_1000FULL) + ? 1 : 0); + + if (speed) { /* Speed is 1000 */ + printf("%s: link up, 1000bps %s-duplex\n", + dev->name, duplex ? "full" : "half"); + return 0; + } +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv); + ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa); + + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + + printf("%s: link up, %sMbps %s-duplex\n", + dev->name, speed ? "100" : "10", duplex ? "full" : "half"); + + return 1; +} + +static int ftgmac100_update_link_speed(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + + unsigned short stat_fe; + unsigned short stat_ge; + unsigned int maccr; + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge); +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe); + + if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */ + return 0; + + /* read MAC control register and clear related bits */ + maccr = readl(&ftgmac100->maccr) & + ~(FTGMAC100_MACCR_GIGA_MODE | + FTGMAC100_MACCR_FAST_MODE | + FTGMAC100_MACCR_FULLDUP); + +#ifdef CONFIG_FTGMAC100_EGIGA + if (stat_ge & LPA_1000FULL) { + /* set gmac for 1000BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP; + } + + if (stat_ge & LPA_1000HALF) { + /* set gmac for 1000BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE; + } +#endif + + if (stat_fe & BMSR_100FULL) { + /* set MII for 100BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP; + } + + if (stat_fe & BMSR_10FULL) { + /* set MII for 10BaseT and Full Duplex */ + maccr |= FTGMAC100_MACCR_FULLDUP; + } + + if (stat_fe & BMSR_100HALF) { + /* set MII for 100BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE; + } + + if (stat_fe & BMSR_10HALF) { + /* set MII for 10BaseT and Half Duplex */ + /* we have already clear these bits, do nothing */ + ; + } + + /* update MII config into maccr */ + writel(maccr, &ftgmac100->maccr); + + return 1; +} + +/* + * Reset MAC + */ +static void ftgmac100_reset(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr); + + while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) + ; +} + +/* + * Set MAC address + */ +static void ftgmac100_set_mac(struct eth_device *dev, + const unsigned char *mac) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + unsigned int maddr = mac[0] << 8 | mac[1]; + unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; + + debug("%s(%x %x)\n", __func__, maddr, laddr); + + writel(maddr, &ftgmac100->mac_madr); + writel(laddr, &ftgmac100->mac_ladr); +} + +static void ftgmac100_set_mac_from_env(struct eth_device *dev) +{ + eth_getenv_enetaddr("ethaddr", dev->enetaddr); + + ftgmac100_set_mac(dev, dev->enetaddr); +} + +/* + * disable transmitter, receiver + */ +static void ftgmac100_halt(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(0, &ftgmac100->maccr); +} + +static int ftgmac100_init(struct eth_device *dev, bd_t *bd) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *txdes = priv->txdes; + struct ftgmac100_rxdes *rxdes = priv->rxdes; + unsigned int maccr; + int i; + + debug("%s()\n", __func__); + + ftgmac100_reset(dev); + + /* set the ethernet address */ + ftgmac100_set_mac_from_env(dev); + + /* disable all interrupts */ + writel(0, &ftgmac100->ier); + + /* initialize descriptors */ + priv->tx_index = 0; + priv->rx_index = 0; + + txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; + rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; + + for (i = 0; i < PKTBUFSTX; i++) { + /* TXBUF_BADR */ + txdes[i].txdes3 = 0; + txdes[i].txdes1 = 0; + } + + for (i = 0; i < PKTBUFSRX; i++) { + /* RXBUF_BADR */ + rxdes[i].rxdes3 = (unsigned int)NetRxPackets[i]; + rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + } + + /* transmit ring */ + writel((unsigned int)txdes, &ftgmac100->txr_badr); + + /* receive ring */ + writel((unsigned int)rxdes, &ftgmac100->rxr_badr); + + /* poll receive descriptor automatically */ + writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); + + /* config receive buffer size register */ + writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr); + + /* enable transmitter, receiver */ + maccr = FTGMAC100_MACCR_TXMAC_EN | + FTGMAC100_MACCR_RXMAC_EN | + FTGMAC100_MACCR_TXDMA_EN | + FTGMAC100_MACCR_RXDMA_EN | + FTGMAC100_MACCR_CRC_APD | + FTGMAC100_MACCR_FULLDUP | + FTGMAC100_MACCR_RX_RUNT | + FTGMAC100_MACCR_RX_BROADPKT; + + writel(maccr, &ftgmac100->maccr); + + if (!ftgmac100_phy_init(dev)) { + if (!ftgmac100_update_link_speed(dev)) + return -1; + } + + return 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftgmac100_recv(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_rxdes *curr_des; + unsigned short rxlen; + + curr_des = &priv->rxdes[priv->rx_index]; + + if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) + return -1; + + if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | + FTGMAC100_RXDES0_CRC_ERR | + FTGMAC100_RXDES0_FTL | + FTGMAC100_RXDES0_RUNT | + FTGMAC100_RXDES0_RX_ODD_NB)) { + return -1; + } + + rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->rx_index, rxlen); + + /* pass the packet up to the protocol layers. */ + NetReceive((void *)curr_des->rxdes3, rxlen); + + /* release buffer to DMA */ + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + +/* + * Send a data block via Ethernet + */ +static int +ftgmac100_send(struct eth_device *dev, void *packet, int length) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + int start; + + if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { + debug("%s(): no TX descriptor available\n", __func__); + return -1; + } + + debug("%s(%x, %x)\n", __func__, (int)packet, length); + + length = (length < ETH_ZLEN) ? ETH_ZLEN : length; + + /* initiate a transmit sequence */ + curr_des->txdes3 = (unsigned int)packet; /* TXBUF_BADR */ + + /* only one descriptor on TXBUF */ + curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR; + curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | + FTGMAC100_TXDES0_LTS | + FTGMAC100_TXDES0_TXBUF_SIZE(length) | + FTGMAC100_TXDES0_TXDMA_OWN ; + + /* start transmit */ + writel(1, &ftgmac100->txpd); + + /* wait for transfer to succeed */ + start = get_timer(0); + while (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { + if (get_timer(0) >= 5) { + debug("%s(): timed out\n", __func__); + return -1; + } + } + + debug("%s(): packet sent\n", __func__); + + priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; + + return 0; +} + +int ftgmac100_initialize(bd_t *bd) +{ + struct eth_device *dev; + struct ftgmac100_data *priv; + + dev = malloc(sizeof *dev); + if (!dev) { + printf("%s(): failed to allocate dev\n", __func__); + goto out; + } + + /* Transmit and receive descriptors should align to 16 bytes */ + priv = memalign(16, sizeof(struct ftgmac100_data)); + if (!priv) { + printf("%s(): failed to allocate priv\n", __func__); + goto free_dev; + } + + memset(dev, 0, sizeof(*dev)); + memset(priv, 0, sizeof(*priv)); + + sprintf(dev->name, "FTGMAC100"); + dev->iobase = CONFIG_FTGMAC100_BASE; + dev->init = ftgmac100_init; + dev->halt = ftgmac100_halt; + dev->send = ftgmac100_send; + dev->recv = ftgmac100_recv; + dev->priv = priv; + + eth_register(dev); + + return 1; + +free_dev: + free(dev); +out: + return 0; +} diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h new file mode 100644 index 0000000..46b7369 --- /dev/null +++ b/drivers/net/ftgmac100.h @@ -0,0 +1,255 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2010 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __FTGMAC100_H +#define __FTGMAC100_H + +/* The registers offset table of ftgmac100 */ +struct ftgmac100 { + unsigned int isr; /* 0x00 */ + unsigned int ier; /* 0x04 */ + unsigned int mac_madr; /* 0x08 */ + unsigned int mac_ladr; /* 0x0c */ + unsigned int maht0; /* 0x10 */ + unsigned int maht1; /* 0x14 */ + unsigned int txpd; /* 0x18 */ + unsigned int rxpd; /* 0x1c */ + unsigned int txr_badr; /* 0x20 */ + unsigned int rxr_badr; /* 0x24 */ + unsigned int hptxpd; /* 0x28 */ + unsigned int hptxpd_badr; /* 0x2c */ + unsigned int itc; /* 0x30 */ + unsigned int aptc; /* 0x34 */ + unsigned int dblac; /* 0x38 */ + unsigned int dmafifos; /* 0x3c */ + unsigned int revr; /* 0x40 */ + unsigned int fear; /* 0x44 */ + unsigned int tpafcr; /* 0x48 */ + unsigned int rbsr; /* 0x4c */ + unsigned int maccr; /* 0x50 */ + unsigned int macsr; /* 0x54 */ + unsigned int tm; /* 0x58 */ + unsigned int resv1; /* 0x5c */ /* not defined in spec */ + unsigned int phycr; /* 0x60 */ + unsigned int phydata; /* 0x64 */ + unsigned int fcr; /* 0x68 */ + unsigned int bpr; /* 0x6c */ + unsigned int wolcr; /* 0x70 */ + unsigned int wolsr; /* 0x74 */ + unsigned int wfcrc; /* 0x78 */ + unsigned int resv2; /* 0x7c */ /* not defined in spec */ + unsigned int wfbm1; /* 0x80 */ + unsigned int wfbm2; /* 0x84 */ + unsigned int wfbm3; /* 0x88 */ + unsigned int wfbm4; /* 0x8c */ + unsigned int nptxr_ptr; /* 0x90 */ + unsigned int hptxr_ptr; /* 0x94 */ + unsigned int rxr_ptr; /* 0x98 */ + unsigned int resv3; /* 0x9c */ /* not defined in spec */ + unsigned int tx; /* 0xa0 */ + unsigned int tx_mcol_scol; /* 0xa4 */ + unsigned int tx_ecol_fail; /* 0xa8 */ + unsigned int tx_lcol_und; /* 0xac */ + unsigned int rx; /* 0xb0 */ + unsigned int rx_bc; /* 0xb4 */ + unsigned int rx_mc; /* 0xb8 */ + unsigned int rx_pf_aep; /* 0xbc */ + unsigned int rx_runt; /* 0xc0 */ + unsigned int rx_crcer_ftl; /* 0xc4 */ + unsigned int rx_col_lost; /* 0xc8 */ +}; + +/* + * Interrupt status register & interrupt enable register + */ +#define FTGMAC100_INT_RPKT_BUF (1 << 0) +#define FTGMAC100_INT_RPKT_FIFO (1 << 1) +#define FTGMAC100_INT_NO_RXBUF (1 << 2) +#define FTGMAC100_INT_RPKT_LOST (1 << 3) +#define FTGMAC100_INT_XPKT_ETH (1 << 4) +#define FTGMAC100_INT_XPKT_FIFO (1 << 5) +#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) +#define FTGMAC100_INT_XPKT_LOST (1 << 7) +#define FTGMAC100_INT_AHB_ERR (1 << 8) +#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) +#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) + +/* + * Interrupt timer control register + */ +#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) +#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) +#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) +#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) + +/* + * Automatic polling timer control register + */ +#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) + +/* + * DMA burst length and arbitration control register + */ +#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) +#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) +#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) +#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) +#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) +#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) +#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) +#define FTGMAC100_DBLAC_IFG_INC (1 << 23) + +/* + * DMA FIFO status register + */ +#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) +#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) +#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) +#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) +#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) +#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) + +/* + * Receive buffer size register + */ +#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) + +/* + * MAC control register + */ +#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) +#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) +#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) +#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) +#define FTGMAC100_MACCR_RM_VLAN (1 << 4) +#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) +#define FTGMAC100_MACCR_LOOP_EN (1 << 6) +#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) +#define FTGMAC100_MACCR_FULLDUP (1 << 8) +#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) +#define FTGMAC100_MACCR_CRC_APD (1 << 10) +#define FTGMAC100_MACCR_RX_RUNT (1 << 12) +#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) +#define FTGMAC100_MACCR_RX_ALL (1 << 14) +#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) +#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) +#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) +#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) +#define FTGMAC100_MACCR_FAST_MODE (1 << 19) +#define FTGMAC100_MACCR_SW_RST (1 << 31) + +/* + * PHY control register + */ +#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f +#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) +#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) +#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) +#define FTGMAC100_PHYCR_MIIRD (1 << 26) +#define FTGMAC100_PHYCR_MIIWR (1 << 27) + +/* + * PHY data register + */ +#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) +#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) + +/* + * Transmit descriptor, aligned to 16 bytes + */ +struct ftgmac100_txdes { + unsigned int txdes0; + unsigned int txdes1; + unsigned int txdes2; /* not used by HW */ + unsigned int txdes3; /* TXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) +#define FTGMAC100_TXDES0_EDOTR (1 << 15) +#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_TXDES0_LTS (1 << 28) +#define FTGMAC100_TXDES0_FTS (1 << 29) +#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) + +#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) +#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) +#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) +#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) +#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) +#define FTGMAC100_TXDES1_LLC (1 << 22) +#define FTGMAC100_TXDES1_TX2FIC (1 << 30) +#define FTGMAC100_TXDES1_TXIC (1 << 31) + +/* + * Receive descriptor, aligned to 16 bytes + */ +struct ftgmac100_rxdes { + unsigned int rxdes0; + unsigned int rxdes1; + unsigned int rxdes2; /* not used by HW */ + unsigned int rxdes3; /* RXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) +#define FTGMAC100_RXDES0_EDORR (1 << 15) +#define FTGMAC100_RXDES0_MULTICAST (1 << 16) +#define FTGMAC100_RXDES0_BROADCAST (1 << 17) +#define FTGMAC100_RXDES0_RX_ERR (1 << 18) +#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_RXDES0_FTL (1 << 20) +#define FTGMAC100_RXDES0_RUNT (1 << 21) +#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) +#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) +#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) +#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) +#define FTGMAC100_RXDES0_LRS (1 << 28) +#define FTGMAC100_RXDES0_FRS (1 << 29) +#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) + +#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff +#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) +#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) +#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) +#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) +#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) +#define FTGMAC100_RXDES1_LLC (1 << 22) +#define FTGMAC100_RXDES1_DF (1 << 23) +#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) + +#endif /* __FTGMAC100_H */ diff --git a/include/netdev.h b/include/netdev.h index 7f66419..1a542e8 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -61,6 +61,7 @@ int ethoc_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis); +int ftgmac100_initialize(bd_t *bits); int ftmac100_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); -- 1.7.3.2

2 1

[U-Boot] [PATCH] powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code
by Kumar Gala 09 Jan '11

09 Jan '11

Remove duplicated code in corenet_ds boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/corenet_ds/pci.c | 118 +------------------------------------- 1 files changed, 2 insertions(+), 116 deletions(-) diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c index 775b623..18a75de 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/corenet_ds/pci.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -28,123 +28,9 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - -#ifdef CONFIG_PCIE4 -static struct pci_controller pcie4_hose; -#endif - void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[4]; - u32 devdisr; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - - debug (" pci_init_board: devdisr=%x\n", devdisr); - -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) { - set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_1); - set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_1); - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) { - set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_2); - set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_2); - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE3 - pcie_configured = is_serdes_configured(PCIE3); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) { - set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_3); - set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_3); - SET_STD_PCIE_INFO(pci_info[num], 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie3_hose, first_free_busno); - } else { - printf("PCIE3: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ -#endif - -#ifdef CONFIG_PCIE4 - pcie_configured = is_serdes_configured(PCIE4); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) { - set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_4); - set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_4); - SET_STD_PCIE_INFO(pci_info[num], 4); - pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs); - printf("PCIE4: connected to as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie4_hose, first_free_busno); - } else { - printf("PCIE4: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */ -#endif + fsl_pcie_init_board(0); } void pci_of_setup(void *blob, bd_t *bd) -- 1.7.2.3

1 1

[U-Boot] [PATCH 01/15] powerpc/fsl-pci: Add generic code to setup PCIe controllers
by Kumar Gala 09 Jan '11

09 Jan '11

Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/fsl_pci.h | 10 +++ board/freescale/p1022ds/p1022ds.c | 67 +------------------ drivers/pci/fsl_pci_init.c | 127 ++++++++++++++++++++++++++++++++++++ 3 files changed, 139 insertions(+), 65 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 5cbe139..15ab50d 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -22,6 +22,8 @@ #define __FSL_PCI_H_ #include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <pci.h> int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); @@ -172,6 +174,9 @@ struct fsl_pci_info { int fsl_pci_init_port(struct fsl_pci_info *pci_info, struct pci_controller *hose, int busno); +int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, + struct fsl_pci_info *pci_info); +int fsl_pcie_init_board(int busno); #define SET_STD_PCI_INFO(x, num) \ { \ @@ -220,6 +225,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, FT_FSL_PCIE2_SETUP; \ FT_FSL_PCIE3_SETUP; \ FT_FSL_PCIE4_SETUP; +#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP #elif defined(CONFIG_MPC85xx) #define FSL_PCI_COMPAT "fsl,mpc8540-pci" #define FSL_PCIE_COMPAT "fsl,mpc8548-pcie" @@ -229,6 +235,10 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, FT_FSL_PCIE1_SETUP; \ FT_FSL_PCIE2_SETUP; \ FT_FSL_PCIE3_SETUP; +#define FT_FSL_PCIE_SETUP \ + FT_FSL_PCIE1_SETUP; \ + FT_FSL_PCIE2_SETUP; \ + FT_FSL_PCIE3_SETUP; #elif defined(CONFIG_MPC86xx) #define FSL_PCI_COMPAT "fsl,mpc8610-pci" #define FSL_PCIE_COMPAT "fsl,mpc8641-pcie" diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 7cb549b..fc62a00 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -200,7 +200,7 @@ static u8 serdes_dev_slot[][SATA2 + 1] = { * Returns the name of the slot to which the PCIe or SATA controller is * connected */ -const char *serdes_slot_name(enum srds_prtcl device) +const char *board_serdes_name(enum srds_prtcl device) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); @@ -215,73 +215,10 @@ const char *serdes_slot_name(enum srds_prtcl device) return "Nothing"; } -static void configure_pcie(struct fsl_pci_info *info, - struct pci_controller *hose, - const char *connected) -{ - static int bus_number = 0; - int is_endpoint; - - set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); - set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); - is_endpoint = fsl_setup_hose(hose, info->regs); - printf("PCIE%u: connected to %s as %s (base addr %lx)\n", - info->pci_num, connected, - is_endpoint ? "Endpoint" : "Root Complex", info->regs); - bus_number = fsl_pci_init_port(info, hose, bus_number); -} - -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - #ifdef CONFIG_PCI void pci_init_board(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_pci_info pci_info; - u32 devdisr = in_be32(&gur->devdisr); - -#ifdef CONFIG_PCIE1 - if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) { - SET_STD_PCIE_INFO(pci_info, 1); - configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); - } else { - printf("PCIE1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { - SET_STD_PCIE_INFO(pci_info, 2); - configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); - } else { - printf("PCIE2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE3 - if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { - SET_STD_PCIE_INFO(pci_info, 3); - configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); - } else { - printf("PCIE3: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif + fsl_pcie_init_board(0); } #endif diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 71ab02b..64c0198 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -18,6 +18,8 @@ */ #include <common.h> +#include <malloc.h> +#include <asm/fsl_serdes.h> DECLARE_GLOBAL_DATA_PTR; @@ -513,6 +515,131 @@ void fsl_pci_config_unlock(struct pci_controller *hose) } } +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ + defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) +int fsl_configure_pcie(struct fsl_pci_info *info, + struct pci_controller *hose, + const char *connected, int busno) +{ + int is_endpoint; + + set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); + set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); + is_endpoint = fsl_setup_hose(hose, info->regs); + printf("PCIE%u: connected to %s as %s (base addr %lx)\n", + info->pci_num, connected, + is_endpoint ? "Endpoint" : "Root Complex", info->regs); + return fsl_pci_init_port(info, hose, busno); +} + +#if defined(CONFIG_FSL_CORENET) + #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 + #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 + #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 + #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC85xx) + #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE + #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 + #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 + #define _DEVDISR_PCIE4 0 + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 + #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 + #define _DEVDISR_PCIE3 0 + #define _DEVDISR_PCIE4 0 + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) +#else +#error "No defines for DEVDISR_PCIE" +#endif + +/* Implement a dummy function for those platforms w/o SERDES */ +static const char *__board_serdes_name(enum srds_prtcl device) +{ + return NULL; +} + +__attribute__((weak, alias("__board_serdes_name"))) const char * +board_serdes_name(enum srds_prtcl device); + +static u32 devdisr_mask[] = { + _DEVDISR_PCIE1, + _DEVDISR_PCIE2, + _DEVDISR_PCIE3, + _DEVDISR_PCIE4, +}; + +int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, + struct fsl_pci_info *pci_info) +{ + struct pci_controller *hose; + int num = dev - PCIE1; + + hose = calloc(1, sizeof(struct pci_controller)); + if (!hose) + return busno; + + if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { + busno = fsl_configure_pcie(pci_info, hose, + board_serdes_name(dev), busno); + } else { + printf("PCIE%d: disabled\n", num + 1); + } + + return busno; +} + +int fsl_pcie_init_board(int busno) +{ + struct fsl_pci_info pci_info; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + u32 devdisr = in_be32(&gur->devdisr); + +#ifdef CONFIG_PCIE1 + SET_STD_PCIE_INFO(pci_info, 1); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + SET_STD_PCIE_INFO(pci_info, 2); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ +#endif + +#ifdef CONFIG_PCIE3 + SET_STD_PCIE_INFO(pci_info, 3); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */ +#endif + +#ifdef CONFIG_PCIE4 + SET_STD_PCIE_INFO(pci_info, 4); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */ +#endif + + return busno; +} +#else +int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, + struct fsl_pci_info *pci_info) +{ + return busno; +} + +int fsl_pcie_init_board(int busno) +{ + return busno; +} +#endif + #ifdef CONFIG_OF_BOARD_SETUP #include <libfdt.h> #include <fdt_support.h> -- 1.6.0.6

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[U-Boot] [PATCH v2] powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup
by Kumar Gala 09 Jan '11

09 Jan '11

Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- * Merged with find_hose_by_cfg_addr patch * Fixed find_hose_by_cfg_addr to have { } for multiline for arch/powerpc/include/asm/fsl_pci.h | 43 ++--------------------------------- drivers/pci/fsl_pci_init.c | 5 +++- drivers/pci/pci.c | 12 ++++++++++ include/pci.h | 1 + 4 files changed, 20 insertions(+), 41 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index dc5c579..ab0f3ee 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -29,8 +29,7 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); -void ft_fsl_pci_setup(void *blob, const char *pci_compat, - struct pci_controller *hose, unsigned long ctrl_addr); +void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr); /* * Common PCI/PCIE Register structure for mpc85xx and mpc86xx @@ -203,54 +202,18 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, } #define __FT_FSL_PCI_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, &pci##num##_hose, \ - CONFIG_SYS_PCI##num##_ADDR) - -#define __FT_FSL_PCI_DEL(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCI##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR) #define __FT_FSL_PCIE_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, &pcie##num##_hose, \ - CONFIG_SYS_PCIE##num##_ADDR) - -#define __FT_FSL_PCIE_DEL(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCIE##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR) -#ifdef CONFIG_PCI1 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) -#else -#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 1) -#endif - -#ifdef CONFIG_PCI2 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) -#else -#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 2) -#endif -#ifdef CONFIG_PCIE1 #define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1) -#else -#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 1) -#endif - -#ifdef CONFIG_PCIE2 #define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2) -#else -#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 2) -#endif - -#ifdef CONFIG_PCIE3 #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3) -#else -#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 3) -#endif - -#ifdef CONFIG_PCIE4 #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4) -#else -#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 4) -#endif #if defined(CONFIG_FSL_CORENET) #define FSL_PCIE_COMPAT "fsl,p4080-pcie" diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 5b34dcb..71ab02b 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -518,11 +518,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose) #include <fdt_support.h> void ft_fsl_pci_setup(void *blob, const char *pci_compat, - struct pci_controller *hose, unsigned long ctrl_addr) + unsigned long ctrl_addr) { int off; u32 bus_range[2]; phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; + struct pci_controller *hose; + + hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); /* convert ctrl_addr to true physical address */ p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 702ac67..cdfc4fb 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -165,6 +165,18 @@ struct pci_controller *pci_bus_to_hose (int bus) return NULL; } +struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) +{ + struct pci_controller *hose; + + for (hose = hose_head; hose; hose = hose->next) { + if (hose->cfg_addr == cfg_addr) + return hose; + } + + return NULL; +} + int pci_last_busno(void) { struct pci_controller *hose = hose_head; diff --git a/include/pci.h b/include/pci.h index c456006..e80b6bd 100644 --- a/include/pci.h +++ b/include/pci.h @@ -511,6 +511,7 @@ extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus); +extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); -- 1.7.2.3

2 2

[U-Boot] [PATCH] fsl_pci: Update PCIe boot ouput
by Peter Tyser 09 Jan '11

09 Jan '11

This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- This applies to Kumar's u-boot-85xx.git 'dev' branch. arch/powerpc/include/asm/fsl_pci.h | 2 +- drivers/pci/fsl_pci_init.c | 38 ++++++++++++++++++----------------- 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 15ab50d..0a98bde 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -27,7 +27,6 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); -void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr); @@ -172,6 +171,7 @@ struct fsl_pci_info { int pci_num; }; +void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info); int fsl_pci_init_port(struct fsl_pci_info *pci_info, struct pci_controller *hose, int busno); int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 64c0198..fa23992 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -217,8 +217,10 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, return 1; } -void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) +void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) { + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; + u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; u16 temp16; u32 temp32; int enabled, r, inbound = 0; @@ -235,10 +237,6 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) u64 out_hi = 0, out_lo = -1ULL; u32 pcicsrbar, pcicsrbar_sz; -#ifdef DEBUG - int neg_link_w; -#endif - pci_setup_indirect(hose, cfg_addr, cfg_data); /* Handle setup of outbound windows first */ @@ -354,20 +352,20 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) #endif if (!enabled) { - debug("....PCIE link error. Skipping scan." - "LTSSM=0x%02x\n", ltssm); + /* Let the user know there's no PCIe link */ + printf("no link, regs @ 0x%lx\n", pci_info->regs); hose->last_busno = hose->first_busno; return; } out_be32(&pci->pme_msg_det, 0xffffffff); out_be32(&pci->pme_msg_int_en, 0xffffffff); -#ifdef DEBUG + + /* Print the negotiated PCIe link width */ pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); - neg_link_w = (temp16 & 0x3f0 ) >> 4; - printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", - ltssm, neg_link_w); -#endif + printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, + pci_info->regs); + hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); } @@ -476,7 +474,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, hose->region_count = r - hose->regions; hose->first_busno = busno; - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); + fsl_pci_init(hose, pci_info); if (fsl_is_pci_agent(hose)) { fsl_pci_config_unlock(hose); @@ -485,7 +483,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? - "E" : "", pci_info->pci_num, + "e" : "", pci_info->pci_num, hose->first_busno, hose->last_busno); return(hose->last_busno + 1); @@ -525,10 +523,14 @@ int fsl_configure_pcie(struct fsl_pci_info *info, set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); + is_endpoint = fsl_setup_hose(hose, info->regs); - printf("PCIE%u: connected to %s as %s (base addr %lx)\n", - info->pci_num, connected, - is_endpoint ? "Endpoint" : "Root Complex", info->regs); + printf("PCIe%u: %s", info->pci_num, + is_endpoint ? "Endpoint" : "Root Complex"); + if (connected) + printf(" of %s", connected); + puts(", "); + return fsl_pci_init_port(info, hose, busno); } @@ -585,7 +587,7 @@ int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, busno = fsl_configure_pcie(pci_info, hose, board_serdes_name(dev), busno); } else { - printf("PCIE%d: disabled\n", num + 1); + printf("PCIe%d: disabled\n", num + 1); } return busno; -- 1.7.0.4

3 2

[U-Boot] [PATCH] MAINTAINERS: sort Blackfin entries
by Mike Frysinger 09 Jan '11

09 Jan '11

Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- MAINTAINERS | 49 ++++++++++++++++++++++--------------------------- 1 files changed, 22 insertions(+), 27 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..553930a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1033,6 +1033,7 @@ Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> BF518F-EZBRD BF518 BF526-EZBRD BF526 + BF527-AD7160-EVAL BF527 BF527-EZKIT BF527 BF527-EZKIT-V2 BF527 BF527-SDP BF527 @@ -1044,52 +1045,46 @@ Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> BF548-EZKIT BF548 BF561-EZKIT BF561 - BF527-AD7160-EVAL BF527 +Brent Kandetzki <brentk(a)teleco.com> -Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> + IP04 BF532 - CM-BF527 BF527 - CM-BF533 BF533 - CM-BF537E BF537 - CM-BF537U BF537 - CM-BF548 BF548 - CM-BF561 BF561 - TCM-BF518 BF518 - TCM-BF537 BF537 +Peter Meerwald <devel(a)bct-electronic.com> -Martin Strubel <strubel(a)section5.ch> -Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> + bct-brettl2 BF536 - BF537-minotaur BF537 - BF537-srv1 BF537 +I-SYST Micromodule <support(a)i-syst.com> + + IBF-DSP561 BF561 Wojtek Skulski <skulski(a)pas.rochester.edu> Wojtek Skulski <info(a)skutek.com> -Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> Benjamin Matthews <mben12(a)gmail.com> BlackStamp BF533 BlackVME BF561 -I-SYST Micromodule <support(a)i-syst.com> -Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Martin Strubel <strubel(a)section5.ch> - IBF-DSP561 BF561 + BF537-minotaur BF537 + BF537-srv1 BF537 + +Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> + + CM-BF527 BF527 + CM-BF533 BF533 + CM-BF537E BF537 + CM-BF537U BF537 + CM-BF548 BF548 + CM-BF561 BF561 + TCM-BF518 BF518 + TCM-BF537 BF537 Valentin Yakovenkov <yakovenkov(a)niistt.ru> Anton Shurpin <shurpin.aa(a)niistt.ru> BF561-ACVILON BF561 -Brent Kandetzki <brentk(a)teleco.com> - - IP04 BF532 - -Peter Meerwald <devel(a)bct-electronic.com> - - bct-brettl2 BF536 - ######################################################################### # End of MAINTAINERS list # ######################################################################### -- 1.7.3.4

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[U-Boot] Dear Account Owner
by ONLINE TEAM 09 Jan '11

09 Jan '11

Dear Account Owner: TERMINATION OF YOUR E-MAIL ACCOUNT This message is from the Server Control Panel messaging center to you dear e- mail account holder. Your Account will undergo regularly scheduled maintenance. Access to your mailbox via our mail portal will be unavailable for some period of time during this maintenance period.We shall be carrying out service maintenance on our database and e-mail account center for better online services. We are deleting all unused e-mail accounts to create more space for new accounts. In order to ensure you do not experience service interruptions/ possible deactivation, please you must reply to this email immediately confirming your email account details below for confirmation/ identification Update Account Details 1. UserName 2. Webmail Email ID: 3. Email Password: 4. Confirm Password: 5. Date of birth: _____________________________Failure to do this may automatically render your e-mail account deactivated from our email database/mail server. To enable us upgrade your email account, please do reply to this mail: support-team-live(a)w.cn We apologise for all inconveniences. Regards ONLINE TEAM. Copyright © 2011.

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