January 2011 - U-Boot

[U-Boot] [PATCH V4 0/4] Add basic NVIDIA Tegra2 SoC support
by Tom Warren 21 Jan '11

21 Jan '11

This series of patches adds preliminary/baseline support for NVIDIA's Tegra2 SoC. Basic CPU (AVP), RAM and UART init are covered so that the system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt. Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow. Changes for V2: - Coding style cleanup - Remove mach-types.h change; wait for ARM kernel sync-up - Move serial driver changes to separate patch - Use board/nvidia/ instead of /board/tegra - Remove TRUE/FALSE defines - Use standard NS16550 register/bit defines in UART init - Change nv-common.h config file to tegra2-common.h Changes for V3: - Use I/O accessors for Tegra2 HW MMIO register access - Allow conditional compile of UARTA/UARTD code to save space Changes for V4: - Use address of HW structs (&pmc, etc.) in readl/writel - Remove empty lines, fix mixed case hex #s & comments in header(s) - Move board/nvidia/common/board.c UART code & header to arch/arm/cpu/armv7/tegra2/ - Declare internal functions as static in UART code Tom Warren (4): arm: Tegra2: Add basic NVIDIA Tegra2 SoC support serial: Add Tegra2 serial port support arm: Tegra2: Add support for NVIDIA Harmony board arm: Tegra2: Add support for NVIDIA Seaboard board MAINTAINERS | 5 + arch/arm/cpu/armv7/tegra2/Makefile | 48 ++++++ arch/arm/cpu/armv7/tegra2/board.c | 91 +++++++++++ arch/arm/cpu/armv7/tegra2/board.h | 58 +++++++ arch/arm/cpu/armv7/tegra2/config.mk | 28 ++++ arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 65 ++++++++ arch/arm/cpu/armv7/tegra2/sys_info.c | 35 ++++ arch/arm/cpu/armv7/tegra2/timer.c | 122 +++++++++++++++ arch/arm/cpu/armv7/tegra2/uart.c | 216 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 154 ++++++++++++++++++ arch/arm/include/asm/arch-tegra2/pinmux.h | 51 ++++++ arch/arm/include/asm/arch-tegra2/pmc.h | 124 +++++++++++++++ arch/arm/include/asm/arch-tegra2/sys_proto.h | 33 ++++ arch/arm/include/asm/arch-tegra2/tegra2.h | 49 ++++++ arch/arm/include/asm/arch-tegra2/uart.h | 44 ++++++ board/nvidia/common/board.c | 57 +++++++ board/nvidia/harmony/Makefile | 50 ++++++ board/nvidia/seaboard/Makefile | 50 ++++++ boards.cfg | 2 + common/serial.c | 3 +- include/configs/harmony.h | 48 ++++++ include/configs/seaboard.h | 44 ++++++ include/configs/tegra2-common.h | 160 +++++++++++++++++++ include/serial.h | 3 +- 24 files changed, 1538 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile create mode 100644 arch/arm/cpu/armv7/tegra2/board.c create mode 100644 arch/arm/cpu/armv7/tegra2/board.h create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c create mode 100644 arch/arm/cpu/armv7/tegra2/uart.c create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h create mode 100644 board/nvidia/common/board.c create mode 100644 board/nvidia/harmony/Makefile create mode 100644 board/nvidia/seaboard/Makefile create mode 100644 include/configs/harmony.h create mode 100644 include/configs/seaboard.h create mode 100644 include/configs/tegra2-common.h -- 1.7.3.5

4 11

[U-Boot] environmental "baudrate" not used at boot up
by chrisv＠cyberswitching.com 21 Jan '11

21 Jan '11

Hi list, I have a board based on an Atmel AT91SAM9263-EK running U-boot 2009.01. I can't seem to get the environmental variable "baudrate" to be used properly, though. Here's the sequence: 1. Power on board, baudrate=115200 2. setenv baudrate 9600 (change terminal baud to 9600) saveenv saveenv reset 3. Gibberish is output to the terminal at 9600 4. Change terminal baud to 115200, everything ok As much as I've looked through the code in lib_arm/board.c, serial_init() and init_baudrate() seem to be coded correctly. Any advice on where to take it from here? Thanks, Chris

6 11

[U-Boot] [GIT PULL] Pull request: u-boot-imx
by Stefano Babic 21 Jan '11

21 Jan '11

Hi Albert, The following changes since commit d6a5e6d531e357dd8016141f73d370d02886a7eb: Cleanup .boards.depend when using an objtree (2011-01-21 08:56:50 +0100) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master Liu Hui-R64343 (8): MX51EVK: UART does not print out the early information MX5: Add initial support for MX53 processor fec_mxc: add support for MX53 processor serial_mxc: add support for MX53 processor mxc_gpio: add support for MX53 processor mxc_i2c: add support for MX53 processor fsl_pmic: add I2C interface support MX5:MX53: add initial support for MX53EVK board Marek Vasut (1): BLOCK: Add freescale IMX51 PATA driver Stefano Babic (1): mxc_nand: add support for i.MX35 processor MAINTAINERS | 4 + arch/arm/cpu/armv7/mx5/iomux.c | 30 ++- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 91 +++--- arch/arm/cpu/armv7/mx5/soc.c | 22 +- arch/arm/include/asm/arch-mx5/asm-offsets.h | 5 + arch/arm/include/asm/arch-mx5/imx-regs.h | 82 ++--- arch/arm/include/asm/arch-mx5/iomux.h | 102 ------ arch/arm/include/asm/arch-mx5/mx5x_pins.h | 469 ++++++++++++++++++++++++++- board/freescale/mx51evk/mx51evk.c | 11 +- board/freescale/mx53evk/Makefile | 48 +++ board/freescale/mx53evk/config.mk | 24 ++ board/freescale/mx53evk/imximage.cfg | 112 +++++++ board/freescale/mx53evk/mx53evk.c | 397 +++++++++++++++++++++++ boards.cfg | 1 + drivers/block/Makefile | 1 + drivers/block/mxc_ata.c | 149 +++++++++ drivers/gpio/mxc_gpio.c | 9 +- drivers/i2c/mxc_i2c.c | 21 +- drivers/misc/fsl_pmic.c | 45 +++- drivers/mtd/nand/mxc_nand.c | 6 +- drivers/net/fec_mxc.c | 2 +- drivers/net/fec_mxc.h | 4 +- drivers/serial/serial_mxc.c | 6 + include/configs/mx51evk.h | 5 +- include/configs/mx53evk.h | 193 +++++++++++ include/configs/vision2.h | 3 +- include/mc13892.h | 5 + 27 files changed, 1620 insertions(+), 227 deletions(-) mode change 100644 => 100755 arch/arm/cpu/armv7/mx5/iomux.c mode change 100644 => 100755 arch/arm/cpu/armv7/mx5/lowlevel_init.S mode change 100644 => 100755 arch/arm/include/asm/arch-mx5/imx-regs.h mode change 100644 => 100755 arch/arm/include/asm/arch-mx5/mx5x_pins.h create mode 100755 board/freescale/mx53evk/Makefile create mode 100755 board/freescale/mx53evk/config.mk create mode 100644 board/freescale/mx53evk/imximage.cfg create mode 100755 board/freescale/mx53evk/mx53evk.c create mode 100644 drivers/block/mxc_ata.c mode change 100644 => 100755 drivers/i2c/mxc_i2c.c mode change 100644 => 100755 include/configs/mx51evk.h create mode 100755 include/configs/mx53evk.h -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

2 1

[U-Boot] [PATCH v1] powerpc/85xx: Add support for Integrated Flash Controller (IFC)
by Dipen Dudhat 21 Jan '11

21 Jan '11

The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat(a)freescale.com> Acked-by: Scott Wood <scottwood(a)freescale.com> --- Changes from v0: - Integrated Wolfgang's comments arch/powerpc/cpu/mpc85xx/cpu.c | 7 +- arch/powerpc/cpu/mpc8xxx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 84 +++ arch/powerpc/include/asm/config.h | 2 + arch/powerpc/include/asm/fsl_ifc.h | 947 +++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_law.h | 1 + arch/powerpc/include/asm/immap_85xx.h | 4 + 7 files changed, 1045 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c create mode 100644 arch/powerpc/include/asm/fsl_ifc.h diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 1aad2ba..49ea6cc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -33,6 +33,7 @@ #include <asm/cache.h> #include <asm/io.h> #include <asm/mmu.h> +#include <asm/fsl_ifc.h> #include <asm/fsl_law.h> #include <asm/fsl_lbc.h> #include <post.h> @@ -280,7 +281,8 @@ int cpu_mmc_init(bd_t *bis) /* * Print out the state of various machine registers. - * Currently prints out LAWs, BR0/OR0, and TLBs + * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing + * parameters for IFC and TLBs */ void mpc85xx_reginfo(void) { @@ -289,6 +291,9 @@ void mpc85xx_reginfo(void) #if defined(CONFIG_FSL_LBC) print_lbc_regs(); #endif +#ifdef CONFIG_FSL_IFC + print_ifc_regs(); +#endif } diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 5dfd65b..4ae26e4 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -15,6 +15,7 @@ COBJS-y += cpu.o endif COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o COBJS-$(CONFIG_SYS_SRIO) += srio.o diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c new file mode 100644 index 0000000..39a4556 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -0,0 +1,84 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat <dipen.dudhat(a)freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_ifc.h> + +void print_ifc_regs(void) +{ + int i, j; + + printf("IFC Controller Registers\n"); + for (i = 0; i < FSL_IFC_BANK_COUNT; i++) { + printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", + i, get_ifc_cspr(i), i, get_ifc_amask(i), + i, get_ifc_csor(i)); + for (j = 0; j < 4; j++) + printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); + } +} + +void init_early_memctl_regs(void) +{ +#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); + + set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); + set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); + set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); + set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); +#endif + +#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) + set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); + set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); + set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); + + set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); + set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); + set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); + set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); +#endif + +#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) + set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); + set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); + set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); + + set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); + set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); + set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); + set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); + +#endif + +#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) + set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); + set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); + set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); + + set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); + set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); + set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); + set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); +#endif +} diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 2b6b233..536f142 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -75,8 +75,10 @@ /* Since so many PPC SOCs have a semi-common LBC, define this here */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC83xx) +#if !defined(CONFIG_FSL_IFC) #define CONFIG_FSL_LBC #endif +#endif /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h new file mode 100644 index 0000000..0464a44 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -0,0 +1,947 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat <dipen.dudhat(a)freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_PPC_FSL_IFC_H +#define __ASM_PPC_FSL_IFC_H + +#include <config.h> +#include <common.h> + +/* + * CSPR - Chip Select Property Register + */ +#define CSPR_BA 0xFFFF0000 +#define CSPR_BA_SHIFT 16 +#define CSPR_PORT_SIZE 0x00000180 +#define CSPR_PORT_SIZE_SHIFT 7 +/* Port Size 8 bit */ +#define CSPR_PORT_SIZE_8 0x00000080 +/* Port Size 16 bit */ +#define CSPR_PORT_SIZE_16 0x00000100 +/* Port Size 32 bit */ +#define CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define CSPR_WP 0x00000040 +#define CSPR_WP_SHIFT 6 +/* Machine Select */ +#define CSPR_MSEL 0x00000006 +#define CSPR_MSEL_SHIFT 1 +/* NOR */ +#define CSPR_MSEL_NOR 0x00000000 +/* NAND */ +#define CSPR_MSEL_NAND 0x00000002 +/* GPCM */ +#define CSPR_MSEL_GPCM 0x00000004 +/* Bank Valid */ +#define CSPR_V 0x00000001 +#define CSPR_V_SHIFT 0 + +/* Convert an address into the right format for the CSPR Registers */ +#define CSPR_PHYS_ADDR(x) (x & 0xffff0000) + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (__ilog2(n) - IFC_AMASK_SHIFT)) + +/* + * Chip Select Option Register IFC_NAND Machine + */ +/* Enable ECC Encoder */ +#define CSOR_NAND_ECC_ENC_EN 0x80000000 +/* 4 bit correction per 520 Byte sector */ +#define CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define CSOR_NAND_ECC_MODE_8 0x10000000 +/* Enable ECC Decoder */ +#define CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define CSOR_NAND_RAL_MASK 0x01800000 +#define CSOR_NAND_RAL_SHIFT 20 +#define CSOR_NAND_RAL_1 0x00000000 +#define CSOR_NAND_RAL_2 0x00800000 +#define CSOR_NAND_RAL_3 0x01000000 +#define CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define CSOR_NAND_PGS_MASK 0x00180000 +#define CSOR_NAND_PGS_SHIFT 16 +#define CSOR_NAND_PGS_512 0x00000000 +#define CSOR_NAND_PGS_2K 0x00080000 +#define CSOR_NAND_PGS_4K 0x00100000 +/* Spare region Size */ +#define CSOR_NAND_SPRZ_MASK 0x0000E000 +#define CSOR_NAND_SPRZ_SHIFT 13 +#define CSOR_NAND_SPRZ_16 0x00000000 +#define CSOR_NAND_SPRZ_64 0x00002000 +#define CSOR_NAND_SPRZ_128 0x00004000 +#define CSOR_NAND_SPRZ_210 0x00006000 +#define CSOR_NAND_SPRZ_218 0x00008000 +#define CSOR_NAND_SPRZ_224 0x0000A000 +/* Pages Per Block */ +#define CSOR_NAND_PB_MASK 0x00000600 +#define CSOR_NAND_PB_SHIFT 8 +#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NAND_TRHZ_MASK 0x0000001C +#define CSOR_NAND_TRHZ_SHIFT 2 +#define CSOR_NAND_TRHZ_20 0x00000000 +#define CSOR_NAND_TRHZ_40 0x00000004 +#define CSOR_NAND_TRHZ_60 0x00000008 +#define CSOR_NAND_TRHZ_80 0x0000000C +#define CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NAND_BCTLD 0x00000001 + +/* + * Chip Select Option Register - NOR Flash Mode + */ +/* Enable Address shift Mode */ +#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define CSOR_NOR_ADM_MASK 0x0003E000 +#define CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) +/* Type of the NOR device hooked */ +#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NOR_TRHZ_MASK 0x0000001C +#define CSOR_NOR_TRHZ_SHIFT 2 +#define CSOR_NOR_TRHZ_20 0x00000000 +#define CSOR_NOR_TRHZ_40 0x00000004 +#define CSOR_NOR_TRHZ_60 0x00000008 +#define CSOR_NOR_TRHZ_80 0x0000000C +#define CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NOR_BCTLD 0x00000001 + +/* + * Chip Select Option Register - GPCM Mode + */ +/* GPCM Mode - Normal */ +#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 +/* GPCM Mode - GenericASIC */ +#define CSOR_GPCM_GPMODE_ASIC 0x80000000 +/* Parity Mode odd/even */ +#define CSOR_GPCM_PARITY_EVEN 0x40000000 +/* Parity Checking enable/disable */ +#define CSOR_GPCM_PAR_EN 0x20000000 +/* GPCM Timeout Count */ +#define CSOR_GPCM_GPTO_MASK 0x0F000000 +#define CSOR_GPCM_GPTO_SHIFT 24 +#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +/* GPCM External Access Termination mode for read access */ +#define CSOR_GPCM_RGETA_EXT 0x00080000 +/* GPCM External Access Termination mode for write access */ +#define CSOR_GPCM_WGETA_EXT 0x00040000 +/* Address Data Multiplexing Shift */ +#define CSOR_GPCM_ADM_MASK 0x0003E000 +#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 +#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) +/* Generic ASIC Parity error indication delay */ +#define CSOR_GPCM_GAPERRD_MASK 0x00000180 +#define CSOR_GPCM_GAPERRD_SHIFT 7 +#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_GPCM_TRHZ_MASK 0x0000001C +#define CSOR_GPCM_TRHZ_20 0x00000000 +#define CSOR_GPCM_TRHZ_40 0x00000004 +#define CSOR_GPCM_TRHZ_60 0x00000008 +#define CSOR_GPCM_TRHZ_80 0x0000000C +#define CSOR_GPCM_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_GPCM_BCTLD 0x00000001 + +/* + * Flash Timing Registers (FTIM0 - FTIM2_CSn) + */ +/* + * FTIM0 - NAND Flash Mode + */ +#define FTIM0_NAND 0x7EFF3F3F +#define FTIM0_NAND_TCCST_SHIFT 25 +#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) +#define FTIM0_NAND_TWP_SHIFT 16 +#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) +#define FTIM0_NAND_TWCHT_SHIFT 8 +#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) +#define FTIM0_NAND_TWH_SHIFT 0 +#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) +/* + * FTIM1 - NAND Flash Mode + */ +#define FTIM1_NAND 0xFFFF3FFF +#define FTIM1_NAND_TADLE_SHIFT 24 +#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) +#define FTIM1_NAND_TWBE_SHIFT 16 +#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) +#define FTIM1_NAND_TRR_SHIFT 8 +#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) +#define FTIM1_NAND_TRP_SHIFT 0 +#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) +/* + * FTIM2 - NAND Flash Mode + */ +#define FTIM2_NAND 0x1FE1F8FF +#define FTIM2_NAND_TRAD_SHIFT 21 +#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) +#define FTIM2_NAND_TREH_SHIFT 11 +#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) +#define FTIM2_NAND_TWHRE_SHIFT 8 +#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) +/* + * FTIM3 - NAND Flash Mode + */ +#define FTIM3_NAND 0xFF000000 +#define FTIM3_NAND_TWW_SHIFT 24 +#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) + +/* + * FTIM0 - NOR Flash Mode + */ +#define FTIM0_NOR 0xF03F3F3F +#define FTIM0_NOR_TACSE_SHIFT 28 +#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) +#define FTIM0_NOR_TEADC_SHIFT 16 +#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) +#define FTIM0_NOR_TAVDS_SHIFT 8 +#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) +#define FTIM0_NOR_TEAHC_SHIFT 0 +#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) +/* + * FTIM1 - NOR Flash Mode + */ +#define FTIM1_NOR 0xFF003F3F +#define FTIM1_NOR_TACO_SHIFT 24 +#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) +#define FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) +#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) +/* + * FTIM2 - NOR Flash Mode + */ +#define FTIM2_NOR 0x0F3CFCFF +#define FTIM2_NOR_TCS_SHIFT 24 +#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) +#define FTIM2_NOR_TCH_SHIFT 18 +#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) +#define FTIM2_NOR_TWPH_SHIFT 10 +#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) +#define FTIM2_NOR_TWP_SHIFT 0 +#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) + +/* + * FTIM0 - Normal GPCM Mode + */ +#define FTIM0_GPCM 0xF03F3F3F +#define FTIM0_GPCM_TACSE_SHIFT 28 +#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) +#define FTIM0_GPCM_TEADC_SHIFT 16 +#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) +#define FTIM0_GPCM_TAVDS_SHIFT 8 +#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) +#define FTIM0_GPCM_TEAHC_SHIFT 0 +#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) +/* + * FTIM1 - Normal GPCM Mode + */ +#define FTIM1_GPCM 0xFF003F00 +#define FTIM1_GPCM_TACO_SHIFT 24 +#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) +#define FTIM1_GPCM_TRAD_SHIFT 8 +#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) +/* + * FTIM2 - Normal GPCM Mode + */ +#define FTIM2_GPCM 0x0F3C00FF +#define FTIM2_GPCM_TCS_SHIFT 24 +#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) +#define FTIM2_GPCM_TCH_SHIFT 18 +#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) +#define FTIM2_GPCM_TWP_SHIFT 0 +#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) + +/* + * Ready Busy Status Register (RB_STAT) + */ +/* CSn is READY */ +#define IFC_RB_STAT_READY_CS0 0x80000000 +#define IFC_RB_STAT_READY_CS1 0x40000000 +#define IFC_RB_STAT_READY_CS2 0x20000000 +#define IFC_RB_STAT_READY_CS3 0x10000000 + +/* + * General Control Register (GCR) + */ +#define IFC_GCR_MASK 0x8000F800 +/* reset all IFC hardware */ +#define IFC_GCR_SOFT_RST_ALL 0x80000000 +/* Turnaroud Time of external buffer */ +#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 +#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 + +/* + * Common Event and Error Status Register (CM_EVTER_STAT) + */ +/* Chip select error */ +#define IFC_CM_EVTER_STAT_CSER 0x80000000 + +/* + * Common Event and Error Enable Register (CM_EVTER_EN) + */ +/* Chip select error checking enable */ +#define IFC_CM_EVTER_EN_CSEREN 0x80000000 + +/* + * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) + */ +/* Chip select error interrupt enable */ +#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 + +/* + * Common Transfer Error Attribute Register-0 (CM_ERATTR0) + */ +/* transaction type of error Read/Write */ +#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 +#define IFC_CM_ERATTR0_ERAID 0x0FF00000 +#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 + +/* + * Clock Control Register (CCR) + */ +#define IFC_CCR_MASK 0x0F0F8800 +/* Clock division ratio */ +#define IFC_CCR_CLK_DIV_MASK 0x0F000000 +#define IFC_CCR_CLK_DIV_SHIFT 24 +#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) +/* IFC Clock Delay */ +#define IFC_CCR_CLK_DLY_MASK 0x000F0000 +#define IFC_CCR_CLK_DLY_SHIFT 16 +#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) +/* Invert IFC clock before sending out */ +#define IFC_CCR_INV_CLK_EN 0x00008000 +/* Fedback IFC Clock */ +#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 + +/* + * Clock Status Register (CSR) + */ +/* Clk is stable */ +#define IFC_CSR_CLK_STAT_STABLE 0x80000000 + +/* + * IFC_NAND Machine Specific Registers + */ +/* + * NAND Configuration Register (NCFGR) + */ +/* Auto Boot Mode */ +#define IFC_NAND_NCFGR_BOOT 0x80000000 +/* Addressing Mode-ROW0+n/COL0 */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 +/* Addressing Mode-ROW0+n/COL0+n */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 +/* Number of loop iterations of FIR sequences for multi page operations */ +#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 +#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 +#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) +/* Number of wait cycles */ +#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF +#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 + +/* + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) + */ +/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define IFC_NAND_FCR0_CMD0 0xFF000000 +#define IFC_NAND_FCR0_CMD0_SHIFT 24 +#define IFC_NAND_FCR0_CMD1 0x00FF0000 +#define IFC_NAND_FCR0_CMD1_SHIFT 16 +#define IFC_NAND_FCR0_CMD2 0x0000FF00 +#define IFC_NAND_FCR0_CMD2_SHIFT 8 +#define IFC_NAND_FCR0_CMD3 0x000000FF +#define IFC_NAND_FCR0_CMD3_SHIFT 0 +#define IFC_NAND_FCR1_CMD4 0xFF000000 +#define IFC_NAND_FCR1_CMD4_SHIFT 24 +#define IFC_NAND_FCR1_CMD5 0x00FF0000 +#define IFC_NAND_FCR1_CMD5_SHIFT 16 +#define IFC_NAND_FCR1_CMD6 0x0000FF00 +#define IFC_NAND_FCR1_CMD6_SHIFT 8 +#define IFC_NAND_FCR1_CMD7 0x000000FF +#define IFC_NAND_FCR1_CMD7_SHIFT 0 + +/* + * Flash ROW and COL Address Register (ROWn, COLn) + */ +/* Main/spare region locator */ +#define IFC_NAND_COL_MS 0x80000000 +/* Column Address */ +#define IFC_NAND_COL_CA_MASK 0x00000FFF + +/* + * NAND Flash Byte Count Register (NAND_BC) + */ +/* Byte Count for read/Write */ +#define IFC_NAND_BC 0x000001FF + +/* + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) + */ +/* NAND Machine specific opcodes OP0-OP14*/ +#define IFC_NAND_FIR0_OP0 0xFC000000 +#define IFC_NAND_FIR0_OP0_SHIFT 26 +#define IFC_NAND_FIR0_OP1 0x03F00000 +#define IFC_NAND_FIR0_OP1_SHIFT 20 +#define IFC_NAND_FIR0_OP2 0x000FC000 +#define IFC_NAND_FIR0_OP2_SHIFT 14 +#define IFC_NAND_FIR0_OP3 0x00003F00 +#define IFC_NAND_FIR0_OP3_SHIFT 8 +#define IFC_NAND_FIR0_OP4 0x000000FC +#define IFC_NAND_FIR0_OP4_SHIFT 2 +#define IFC_NAND_FIR1_OP5 0xFC000000 +#define IFC_NAND_FIR1_OP5_SHIFT 26 +#define IFC_NAND_FIR1_OP6 0x03F00000 +#define IFC_NAND_FIR1_OP6_SHIFT 20 +#define IFC_NAND_FIR1_OP7 0x000FC000 +#define IFC_NAND_FIR1_OP7_SHIFT 14 +#define IFC_NAND_FIR1_OP8 0x00003F00 +#define IFC_NAND_FIR1_OP8_SHIFT 8 +#define IFC_NAND_FIR1_OP9 0x000000FC +#define IFC_NAND_FIR1_OP9_SHIFT 2 +#define IFC_NAND_FIR2_OP10 0xFC000000 +#define IFC_NAND_FIR2_OP10_SHIFT 26 +#define IFC_NAND_FIR2_OP11 0x03F00000 +#define IFC_NAND_FIR2_OP11_SHIFT 20 +#define IFC_NAND_FIR2_OP12 0x000FC000 +#define IFC_NAND_FIR2_OP12_SHIFT 14 +#define IFC_NAND_FIR2_OP13 0x00003F00 +#define IFC_NAND_FIR2_OP13_SHIFT 8 +#define IFC_NAND_FIR2_OP14 0x000000FC +#define IFC_NAND_FIR2_OP14_SHIFT 2 + +/* + * Instruction opcodes to be programmed + * in FIR registers- 6bits + */ +enum ifc_nand_fir_opcodes { + IFC_FIR_OP_NOP, + IFC_FIR_OP_CA0, + IFC_FIR_OP_CA1, + IFC_FIR_OP_CA2, + IFC_FIR_OP_CA3, + IFC_FIR_OP_RA0, + IFC_FIR_OP_RA1, + IFC_FIR_OP_RA2, + IFC_FIR_OP_RA3, + IFC_FIR_OP_CMD0, + IFC_FIR_OP_CMD1, + IFC_FIR_OP_CMD2, + IFC_FIR_OP_CMD3, + IFC_FIR_OP_CMD4, + IFC_FIR_OP_CMD5, + IFC_FIR_OP_CMD6, + IFC_FIR_OP_CMD7, + IFC_FIR_OP_CW0, + IFC_FIR_OP_CW1, + IFC_FIR_OP_CW2, + IFC_FIR_OP_CW3, + IFC_FIR_OP_CW4, + IFC_FIR_OP_CW5, + IFC_FIR_OP_CW6, + IFC_FIR_OP_CW7, + IFC_FIR_OP_WBCD, + IFC_FIR_OP_RBCD, + IFC_FIR_OP_BTRD, + IFC_FIR_OP_RDSTAT, + IFC_FIR_OP_NWAIT, + IFC_FIR_OP_WFR, + IFC_FIR_OP_SBRD, + IFC_FIR_OP_UA, + IFC_FIR_OP_RB, +}; + +/* + * NAND Operation Sequence Start (NANDSEQ_STRT) + */ +/* NAND Flash Operation Start */ +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 +/* Automatic Erase */ +#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 +/* Automatic Program */ +#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 +/* Automatic Copyback */ +#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 +/* Automatic Read Operation */ +#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 +/* Automatic Status Read */ +#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 + +/* + * NAND Event and Error Status Register (NAND_EVTER_STAT) + */ +/* Operation Complete */ +#define IFC_NAND_EVTER_STAT_OPC 0x80000000 +/* Flash Timeout Error */ +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 +/* Write Protect Error */ +#define IFC_NAND_EVTER_STAT_WPER 0x04000000 +/* ECC Error */ +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 +/* RCW Load Done */ +#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 +/* Boot Loadr Done */ +#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 +/* Bad Block Indicator search select */ +#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 + +/* + * NAND Flash Page Read Completion Event Status Register + * (PGRDCMPL_EVT_STAT) + */ +#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 +/* Small Page 0-15 Done */ +#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) +/* Large Page(2K) 0-3 Done */ +#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) +/* Large Page(4K) 0-1 Done */ +#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) + +/* + * NAND Event and Error Enable Register (NAND_EVTER_EN) + */ +/* Operation complete event enable */ +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 +/* Page read complete event enable */ +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 +/* Flash Timeout error enable */ +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 +/* Write Protect error enable */ +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 +/* ECC error logging enable */ +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 + +/* + * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) + */ +/* Enable interrupt for operation complete */ +#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 +/* Enable interrupt for Page read complete */ +#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 +/* Enable interrupt for Flash timeout error */ +#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 +/* Enable interrupt for Write protect error */ +#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 +/* Enable interrupt for ECC error*/ +#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 + +/* + * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) + */ +#define IFC_NAND_ERATTR0_MASK 0x0C080000 +/* Error on CS0-3 for NAND */ +#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 +#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 +#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 +/* Transaction type of error Read/Write */ +#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 + +/* + * NAND Flash Status Register (NAND_FSR) + */ +/* First byte of data read from read status op */ +#define IFC_NAND_NFSR_RS0 0xFF000000 +/* Second byte of data read from read status op */ +#define IFC_NAND_NFSR_RS1 0x00FF0000 + +/* + * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) + */ +/* Number of ECC errors on sector n (n = 0-15) */ +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 + +/* + * NAND Control Register (NANDCR) + */ +#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 +#define IFC_NAND_NCR_FTOCNT_SHIFT 25 +#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) + +/* + * NAND_AUTOBOOT_TRGR + */ +/* Trigger RCW load */ +#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 +/* Trigget Auto Boot */ +#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 + +/* + * NAND_MDR + */ +/* 1st read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA0 0xFF000000 +/* 2nd read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA1 0x00FF0000 + +/* + * NOR Machine Specific Registers + */ +/* + * NOR Event and Error Status Register (NOR_EVTER_STAT) + */ +/* NOR Command Sequence Operation Complete */ +#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 +/* Write Protect Error */ +#define IFC_NOR_EVTER_STAT_WPER 0x04000000 +/* Command Sequence Timeout Error */ +#define IFC_NOR_EVTER_STAT_STOER 0x01000000 + +/* + * NOR Event and Error Enable Register (NOR_EVTER_EN) + */ +/* NOR Command Seq complete event enable */ +#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 +/* Write Protect Error Checking Enable */ +#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 +/* Timeout Error Enable */ +#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 + +/* + * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) + */ +/* Enable interrupt for OPC complete */ +#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 +/* Enable interrupt for write protect error */ +#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 +/* Enable interrupt for timeout error */ +#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 + +/* + * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transation */ +#define IFC_NOR_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to NOR error */ +#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 +#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 +#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 +/* Type of transaction read/write */ +#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) + */ +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 + +/* + * NOR Control Register (NORCR) + */ +#define IFC_NORCR_MASK 0x0F0F0000 +/* No. of Address/Data Phase */ +#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 +#define IFC_NORCR_NUM_PHASE_SHIFT 24 +#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) +/* Sequence Timeout Count */ +#define IFC_NORCR_STOCNT_MASK 0x000F0000 +#define IFC_NORCR_STOCNT_SHIFT 16 +#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) + +/* + * GPCM Machine specific registers + */ +/* + * GPCM Event and Error Status Register (GPCM_EVTER_STAT) + */ +/* Timeout error */ +#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 +/* Parity error */ +#define IFC_GPCM_EVTER_STAT_PER 0x01000000 + +/* + * GPCM Event and Error Enable Register (GPCM_EVTER_EN) + */ +/* Timeout error enable */ +#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 +/* Parity error enable */ +#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 + +/* + * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) + */ +/* Enable Interrupt for timeout error */ +#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 +/* Enable Interrupt for Parity error */ +#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 + +/* + * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to GPCM error */ +#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 +#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 +#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 +/* Type of transaction read/Write */ +#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) + */ +/* On which beat of address/data parity error is observed */ +#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 +/* Parity Error on byte */ +#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 +/* Parity Error reported in addr or data phase */ +#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 + +/* + * GPCM Status Register (GPCM_STAT) + */ +#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ + + +#ifndef __ASSEMBLY__ +#include <asm/io.h> + +extern void print_ifc_regs(void); +extern void init_early_memctl_regs(void); + +#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) + +#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) + +#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define set_ifc_ftim(i, j, v) \ + (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + +#define FSL_IFC_BANK_COUNT 4 + +enum ifc_chip_sel { + IFC_CS0, + IFC_CS1, + IFC_CS2, + IFC_CS3, +}; + +enum ifc_ftims { + IFC_FTIM0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +}; + +/* + * IFC Controller NAND Machine registers + */ +struct fsl_ifc_nand { + u32 ncfgr; + u32 res1[0x4]; + u32 nand_fcr0; + u32 nand_fcr1; + u32 res2[0x8]; + u32 row0; + u32 res3; + u32 col0; + u32 res4; + u32 row1; + u32 res5; + u32 col1; + u32 res6; + u32 row2; + u32 res7; + u32 col2; + u32 res8; + u32 row3; + u32 res9; + u32 col3; + u32 res10[0x9]; + u32 nand_fbcr; + u32 res11; + u32 nand_fir0; + u32 nand_fir1; + u32 nand_fir2; + u32 res12[0x10]; + u32 nand_csel; + u32 res13; + u32 nandseq_strt; + u32 res14; + u32 nand_evter_stat; + u32 res15; + u32 pgrdcmpl_evt_stat; + u32 res16[0x2]; + u32 nand_evter_en; + u32 res17[0x2]; + u32 nand_evter_intr_en; + u32 res18[0x2]; + u32 nand_erattr0; + u32 nand_erattr1; + u32 res19[0x10]; + u32 nand_fsr; + u32 res20; + u32 nand_eccstat0; + u32 nand_eccstat1; + u32 nand_eccstat2; + u32 nand_eccstat3; + u32 res21[0x20]; + u32 nanndcr; + u32 res22[0x2]; + u32 nand_autoboot_trgr; + u32 res23; + u32 nand_mdr; + u32 res24[0x5C]; +}; + +/* + * IFC controller NOR Machine registers + */ +struct fsl_ifc_nor { + u32 nor_evter_stat; + u32 res1[0x2]; + u32 nor_evter_en; + u32 res2[0x2]; + u32 nor_evter_intr_en; + u32 res3[0x2]; + u32 nor_erattr0; + u32 nor_erattr1; + u32 nor_erattr2; + u32 res4[0x2]; + u32 norcr; + u32 res5[0xEF]; +}; + +/* + * IFC controller GPCM Machine registers + */ +struct fsl_ifc_gpcm { + u32 gpcm_evter_stat; + u32 res1[0x2]; + u32 gpcm_evter_en; + u32 res2[0x2]; + u32 gpcm_evter_intr_en; + u32 res3[0x2]; + u32 gpcm_erattr0; + u32 gpcm_erattr1; + u32 gpcm_erattr2; + u32 gpcm_stat; + u32 res4[0x1F3]; +}; + + +/* + * IFC Controller Registers + */ +struct fsl_ifc { + u32 ifc_rev; + u32 res1[0x3]; + struct { + u32 cspr; + u32 res2[0x2]; + } cspr_cs[FSL_IFC_BANK_COUNT]; + u32 res3[0x18]; + struct { + u32 amask; + u32 res4[0x2]; + } amask_cs[FSL_IFC_BANK_COUNT]; + u32 res5[0x18]; + struct { + u32 csor; + u32 res6[0x2]; + } csor_cs[FSL_IFC_BANK_COUNT]; + u32 res7[0x18]; + struct { + u32 ftim[4]; + u32 res8[0x8]; + } ftim_cs[FSL_IFC_BANK_COUNT]; + u32 res9[0x60]; + u32 rb_stat; + u32 res10[0x2]; + u32 ifc_gcr; + u32 res11[0x2]; + u32 cm_evter_stat; + u32 res12[0x2]; + u32 cm_evter_en; + u32 res13[0x2]; + u32 cm_evter_intr_en; + u32 res14[0x2]; + u32 cm_erattr0; + u32 cm_erattr1; + u32 res15[0x2]; + u32 ifc_ccr; + u32 ifc_csr; + u32 res16[0x2EB]; + struct fsl_ifc_nand ifc_nand; + struct fsl_ifc_nor ifc_nor; + struct fsl_ifc_gpcm ifc_gpcm; +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_PPC_FSL_IFC_H */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 6a4279c..e308b15 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -91,6 +91,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO +#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC #ifdef CONFIG_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 6bd83ba..a30a58c 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -31,6 +31,7 @@ #include <asm/types.h> #include <asm/fsl_dma.h> #include <asm/fsl_i2c.h> +#include <asm/fsl_ifc.h> #include <asm/fsl_lbc.h> #include <asm/fsl_fman.h> @@ -2227,6 +2228,7 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 @@ -2269,6 +2271,8 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_IFC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ -- 1.5.6.5

2 1

[U-Boot] [PATCH][v1] powerpc/85xx: Add SERDES support for P1010/P1014
by Prabhakar Kushwaha 21 Jan '11

21 Jan '11

Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Changes for v1: Incorporated Wolfgang Denk's comment -- removed volatile Based git://git.denx.de/u-boot-mpc85xx.git (branch master) arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/p1010_serdes.c | 75 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 5 ++ 3 files changed, 82 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/p1010_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index b7f51e7..69c43b3 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -87,9 +87,11 @@ COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o +COBJS-$(CONFIG_P1010) += p1010_serdes.o COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1013_serdes.o +COBJS-$(CONFIG_P1014) += p1010_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c new file mode 100644 index 0000000..4524d29 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -0,0 +1,75 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha <prabhakar(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, + [0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {NONE, NONE}, + [0x01] = {SATA1, SATA2}, + [0x02] = {SATA1, SATA2}, + [0x03] = {PCIE1, PCIE2}, +}; + + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 93a9e6c..7531fdc 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1891,8 +1891,13 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 #else +#if defined(CONFIG_P1010) +#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 +#else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 +#endif /* if defined(CONFIG_P1010) */ #endif #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 -- 1.6.3.1

2 1

[U-Boot] [PATCH 2/2] at91: fixed 'esd gmbh' meesc and otc570 boards
by Daniel Gorsulowski 21 Jan '11

21 Jan '11

Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski(a)esd.eu> --- There is still a bug in USART config. This patch is for reviewing only! board/esd/meesc/config.mk | 1 - board/esd/meesc/meesc.c | 39 +++++----- board/esd/otc570/config.mk | 1 - board/esd/otc570/otc570.c | 51 +++++++------ boards.cfg | 6 +- include/configs/meesc.h | 150 ++++++++++++++++++++++--------------- include/configs/otc570.h | 179 +++++++++++++++++++++++++------------------- 7 files changed, 241 insertions(+), 186 deletions(-) delete mode 100644 board/esd/meesc/config.mk delete mode 100644 board/esd/otc570/config.mk diff --git a/board/esd/meesc/config.mk b/board/esd/meesc/config.mk deleted file mode 100644 index 2077692..0000000 --- a/board/esd/meesc/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 41fa3e1..46cd33c 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -3,7 +3,7 @@ * Stelian Pop <stelian.pop(a)leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009-2010 + * (C) Copyright 2009-2011 * Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -27,6 +27,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91sam9263.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> @@ -36,7 +37,6 @@ #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -67,8 +67,8 @@ int get_hw_rev(void) static void meesc_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -88,7 +88,7 @@ static void meesc_nand_hw_init(void) writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), + AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); /* Configure RDY/BSY */ @@ -102,9 +102,9 @@ static void meesc_nand_hw_init(void) #ifdef CONFIG_MACB static void meesc_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); at91_macb_hw_init(); } #endif @@ -117,7 +117,7 @@ static void meesc_macb_hw_init(void) */ static void meesc_ethercat_hw_init(void) { - at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; + at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; /* Configure SMC EBI1_CS0 for EtherCAT */ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | @@ -142,8 +142,9 @@ static void meesc_ethercat_hw_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27)); + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + (1 << 27)); return 0; } @@ -151,7 +152,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; } @@ -225,7 +226,7 @@ int misc_init_r(void) { char *str; char buf[32]; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* * Normally the processor clock has a divisor of 2. @@ -248,22 +249,22 @@ int misc_init_r(void) int board_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Peripheral Clock Enable Register */ - writel(1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE | - 1 << AT91SAM9263_ID_UHP, + writel(1 << ATMEL_ID_PIOA | + 1 << ATMEL_ID_PIOB | + 1 << ATMEL_ID_PIOCDE | + 1 << ATMEL_ID_UHP, &pmc->pcer); /* initialize ET1100 Controller */ meesc_ethercat_hw_init(); /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND meesc_nand_hw_init(); #endif diff --git a/board/esd/otc570/config.mk b/board/esd/otc570/config.mk deleted file mode 100644 index e554a45..0000000 --- a/board/esd/otc570/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 410d8b4..c66f99e 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010 + * (C) Copyright 2010-2011 * Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -27,6 +27,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91sam9263.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> @@ -36,7 +37,6 @@ #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <atmel_lcdc.h> #include <lcd.h> #include <netdev.h> @@ -73,8 +73,8 @@ int get_hw_rev(void) static void otc570_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -94,7 +94,7 @@ static void otc570_nand_hw_init(void) writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), + AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); /* Configure RDY/BSY */ @@ -108,9 +108,9 @@ static void otc570_nand_hw_init(void) #ifdef CONFIG_MACB static void otc570_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); at91_macb_hw_init(); } #endif @@ -123,7 +123,7 @@ static void otc570_macb_hw_init(void) */ static void otc570_ethercat_hw_init(void) { - at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; + at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; /* Configure SMC EBI1_CS0 for EtherCAT */ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | @@ -179,7 +179,7 @@ void lcd_disable(void) static void otc570_lcd_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ @@ -206,7 +206,7 @@ static void otc570_lcd_hw_init(void) at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */ - writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); gd->fb_base = CONFIG_OTC570_LCD_BASE; } @@ -239,8 +239,9 @@ void lcd_show_board_info(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27)); + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + (1 << 27)); return 0; } @@ -248,7 +249,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; } @@ -297,12 +298,12 @@ u32 get_board_rev(void) int misc_init_r(void) { char str[64]; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_pio_output(AT91_PIO_PORTA, 29, 1); at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ - writel(1 << AT91SAM9263_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_US0, &pmc->pcer); /* Set USART_MODE = 1 (RS485) */ writel(1, 0xFFF8C004); @@ -333,25 +334,25 @@ int misc_init_r(void) int board_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Peripheral Clock Enable Register */ - writel( 1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE | - 1 << AT91SAM9263_ID_TWI | - 1 << AT91SAM9263_ID_SPI0 | - 1 << AT91SAM9263_ID_LCDC | - 1 << AT91SAM9263_ID_UHP, + writel( 1 << ATMEL_ID_PIOA | + 1 << ATMEL_ID_PIOB | + 1 << ATMEL_ID_PIOCDE | + 1 << ATMEL_ID_TWI | + 1 << ATMEL_ID_SPI0 | + 1 << ATMEL_ID_LCDC | + 1 << ATMEL_ID_UHP, &pmc->pcer); /* arch number of OTC570-Board */ gd->bd->bi_arch_number = MACH_TYPE_OTC570; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND otc570_nand_hw_init(); #endif diff --git a/boards.cfg b/boards.cfg index 9b15026..77f3fc4 100644 --- a/boards.cfg +++ b/boards.cfg @@ -83,8 +83,10 @@ at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000 top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000 -meesc arm arm926ejs - esd at91 -otc570 arm arm926ejs - esd at91 +meesc arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_NANDFLASH +meesc_dataflash arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_DATAFLASH +otc570 arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_NANDFLASH +otc570_dataflash arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_DATAFLASH pm9261 arm arm926ejs - ronetix at91 pm9263 arm arm926ejs - ronetix at91 da830evm arm arm926ejs da8xxevm davinci davinci diff --git a/include/configs/meesc.h b/include/configs/meesc.h index a27b36b..dbb97ed 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -3,7 +3,7 @@ * Stelian Pop <stelian.pop(a)leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009-2010 + * (C) Copyright 2009-2011 * Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -31,49 +31,67 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Common stuff */ -#define CONFIG_MEESC 1 /* Board is esd MEESC */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include <asm/hardware.h> + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ +#define CONFIG_SYS_TEXT_BASE 0x21f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* main clock xtal */ #define CONFIG_SYS_HZ 1000 /* decrementer freq */ -#define CONFIG_DISPLAY_BOARDINFO 1 -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ -#define CONFIG_PREBOOT /* enable preboot variable */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_SERIAL_TAG 1 -#define CONFIG_REVISION_TAG 1 -#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ -#define CONFIG_SKIP_LOWLEVEL_INIT +/* Misc CPU related */ +#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ +#define CONFIG_MEESC /* Board is esd MEESC */ #define CONFIG_MISC_INIT_R /* Call misc_init_r */ - +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */ +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ARCH_CPU_INIT +#define CONFIG_SERIAL_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT /* * Hardware drivers */ +/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + /* Console output */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600} -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -84,21 +102,25 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB /* LED */ -#define CONFIG_AT91_LED 1 +#define CONFIG_AT91_LED /* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 + +/* Initial stack pointer */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE) /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_HAS_DATAFLASH #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ @@ -107,14 +129,14 @@ #define DATAFLASH_TCHS (0x1 << 24) /* NOR flash is not populated, disable it */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -125,39 +147,39 @@ #endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_FIT #define CONFIG_NET_RETRY_COUNT 20 #undef CONFIG_RESET_PHY_R /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_CMD_FAT 1 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x21e00000 +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_USE_DATAFLASH 1 -#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x21e00000 /* CAN */ -#define CONFIG_AT91_CAN 1 +#define CONFIG_AT91_CAN /* hw-controller addresses */ -#define CONFIG_ET1100_BASE 0x70000000 +#define CONFIG_ET1100_BASE 0x70000000 /* ATMEL_BASE_CS6 */ + +#ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env in dataflash on CS0 */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_ENV_IS_IN_DATAFLASH #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ 0x8400) #define CONFIG_ENV_OFFSET 0x4200 @@ -165,16 +187,22 @@ CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } +#elif CONFIG_SYS_USE_NANDFLASH + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0xC0000 +#define CONFIG_ENV_SIZE 0x20000 + +#endif #define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING /* * Size of malloc() pool diff --git a/include/configs/otc570.h b/include/configs/otc570.h index ca3bf26..013c837 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010 + * (C) Copyright 2010-2011 * Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -31,72 +31,90 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Common stuff */ -#define CONFIG_OTC570 1 /* Board is esd OTC570 */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq */ -#define CONFIG_DISPLAY_BOARDINFO 1 -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ -#define CONFIG_PREBOOT /* enable preboot variable */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_SERIAL_TAG 1 -#define CONFIG_REVISION_TAG 1 -#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include <asm/hardware.h> -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* main clock xtal */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq */ +/* Misc CPU related */ +#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ +#define CONFIG_OTC570 /* Board is esd OTC570 */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */ +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ARCH_CPU_INIT +#define CONFIG_SERIAL_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 + +/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO /* Console output */ -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600} #define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* LCD */ -#define CONFIG_LCD 1 +#define CONFIG_LCD #define LCD_BPP LCD_COLOR8 #undef CONFIG_SPLASH_SCREEN #ifndef CONFIG_SPLASH_SCREEN -#define CONFIG_LCD_LOGO 1 -#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_LOGO +#define CONFIG_LCD_INFO #undef CONFIG_LCD_INFO_BELOW_LOGO #endif /* CONFIG_SPLASH_SCREEN */ #undef LCD_TEST_PATTERN -#define CONFIG_SYS_WHITE_ON_BLACK 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_LCD +#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_OTC570_LCD_BASE 0x23E00000 /* LCD is in SDRAM */ -#define CONFIG_CMD_BMP 1 +#define CONFIG_CMD_BMP /* RTC and I2C stuff */ -#define CONFIG_RTC_DS1338 1 +#define CONFIG_RTC_DS1338 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #undef CONFIG_HARD_I2C -#define CONFIG_SOFT_I2C 1 +#define CONFIG_SOFT_I2C #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0x7F #ifdef CONFIG_SOFT_I2C -#define CONFIG_I2C_CMD_TREE 1 -#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_I2C_CMD_TREE +#define CONFIG_I2C_MULTI_BUS /* Configure data and clock pins for pio */ #define I2C_INIT { \ at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \ @@ -116,16 +134,13 @@ #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ #endif /* CONFIG_SOFT_I2C */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 - /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -135,23 +150,27 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 -#define CONFIG_CMD_I2C 1 -#define CONFIG_CMD_DATE 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE /* LED */ -#define CONFIG_AT91_LED 1 +#define CONFIG_AT91_LED /* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 + +/* Initial stack pointer */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE) /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_HAS_DATAFLASH #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ @@ -160,14 +179,14 @@ #define DATAFLASH_TCHS (0x1 << 24) /* NOR flash is not populated, disable it */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -178,39 +197,39 @@ #endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_FIT #define CONFIG_NET_RETRY_COUNT 20 #undef CONFIG_RESET_PHY_R /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_CMD_FAT 1 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x23e00000 +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_USE_DATAFLASH 1 -#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 /* CAN */ -#define CONFIG_AT91_CAN 1 +#define CONFIG_AT91_CAN /* hw-controller addresses */ -#define CONFIG_ET1100_BASE 0x70000000 +#define CONFIG_ET1100_BASE 0x70000000 /* ATMEL_BASE_CS6 */ + +#ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env in dataflash on CS0 */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_ENV_IS_IN_DATAFLASH #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ 0x8400) #define CONFIG_ENV_OFFSET 0x4200 @@ -218,16 +237,22 @@ CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } +#elif CONFIG_SYS_USE_NANDFLASH + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0xC0000 +#define CONFIG_ENV_SIZE 0x20000 + +#endif #define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING /* * Size of malloc() pool -- 1.5.3

3 3

[U-Boot] ??: [PATCH v2] include/linux/mii.h: update for supporting GE
by macpaul＠andestech.com 21 Jan '11

21 Jan '11

Dear Wolfgang, > /home/wd/git/u-boot/work/include/linux/mii.h:134:1: warning: > "LPA_1000HALF" redefined > In file included from uec_phy.c:26: > uec_phy.h:35:1: warning: this is the location of the previous > definition > text data bss dec hex filename > 327682 28828 230568 587078 8f546 /work/wd/tmp-ppc/u-boot Moreover, after checking drivers/qe/uec_phy.h, I've found some definitions differs from standard linux code. In uec_phy: drivers/qe/uec_phy.h:34:#define LPA_1000FULL 0x0400 drivers/qe/uec_phy.h:35:#define LPA_1000HALF 0x0200 In Linux: include/linux/mii.h:133:#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ include/linux/mii.h:134:#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ Do you know if this is a wrong defintion on uec_phy ? I'm afraid the fix will lead some mis-behavior for boards has uec_phy. Best regards, Macpaul Lin

4 5

[U-Boot] [PATCH 1/7] Add support for MX35 processor
by Stefano Babic 21 Jan '11

21 Jan '11

The patch adds basic support for the Freescale's i.MX35 (arm1136 based) processor. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/arm1136/mx35/Makefile | 49 +++ arch/arm/cpu/arm1136/mx35/generic.c | 462 ++++++++++++++++++++++++++++ arch/arm/cpu/arm1136/mx35/iomux.c | 147 +++++++++ arch/arm/cpu/arm1136/mx35/timer.c | 118 +++++++ arch/arm/include/asm/arch-mx35/clock.h | 45 +++ arch/arm/include/asm/arch-mx35/crm_regs.h | 270 ++++++++++++++++ arch/arm/include/asm/arch-mx35/imx-regs.h | 367 ++++++++++++++++++++++ arch/arm/include/asm/arch-mx35/iomux.h | 290 +++++++++++++++++ arch/arm/include/asm/arch-mx35/mmu.h | 172 +++++++++++ arch/arm/include/asm/arch-mx35/mx35_pins.h | 342 ++++++++++++++++++++ arch/arm/include/asm/arch-mx35/sys_proto.h | 31 ++ 11 files changed, 2293 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm1136/mx35/Makefile create mode 100644 arch/arm/cpu/arm1136/mx35/generic.c create mode 100644 arch/arm/cpu/arm1136/mx35/iomux.c create mode 100644 arch/arm/cpu/arm1136/mx35/timer.c create mode 100644 arch/arm/include/asm/arch-mx35/clock.h create mode 100644 arch/arm/include/asm/arch-mx35/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mx35/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mx35/iomux.h create mode 100644 arch/arm/include/asm/arch-mx35/mmu.h create mode 100644 arch/arm/include/asm/arch-mx35/mx35_pins.h create mode 100644 arch/arm/include/asm/arch-mx35/sys_proto.h diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile new file mode 100644 index 0000000..9b4cf76 --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS += generic.o +COBJS += timer.o +COBJS += iomux.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c new file mode 100644 index 0000000..f3519aa --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -0,0 +1,462 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) +#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) +#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) +#define CLK_CODE_PATH(c) ((c) & 0xFF) + +#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) + +#ifdef CONFIG_FSL_ESDHC +DECLARE_GLOBAL_DATA_PTR; +#endif + +static int g_clk_mux_auto[8] = { + CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, + CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, +}; + +static int g_clk_mux_consumer[16] = { + CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, + -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), + CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, + -1, -1, CLK_CODE(4, 2, 0), -1, +}; + +static int hsp_div_table[3][16] = { + {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, + {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, + {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, +}; + +u32 get_cpu_rev(void) +{ + int reg; + struct iim_regs *iim = + (struct iim_regs *)IIM_BASE_ADDR; + reg = readl(&iim->iim_srev); + if (!reg) { + reg = __REG(ROMPATCH_REV); + reg <<= 4; + } else + reg += CHIP_REV_1_0; + return 0x35000 + (reg & 0xFF); +} + +static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) +{ + int *pclk_mux; + if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { + pclk_mux = g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + } else { + pclk_mux = g_clk_mux_auto + + ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> + MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); + } + + if ((*pclk_mux) == -1) + return -1; + + if (fi && fd) { + if (!CLK_CODE_PATH(*pclk_mux)) { + *fi = *fd = 1; + return CLK_CODE_ARM(*pclk_mux); + } + if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { + *fi = 3; + *fd = 4; + } else { + *fi = 2; + *fd = 3; + } + } + return CLK_CODE_ARM(*pclk_mux); +} + +static int get_ahb_div(u32 pdr0) +{ + int *pclk_mux; + + pclk_mux = g_clk_mux_consumer + + ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> + MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); + + if ((*pclk_mux) == -1) + return -1; + + return CLK_CODE_AHB(*pclk_mux); +} + +static u32 decode_pll(u32 reg, u32 infreq) +{ + u32 mfi = (reg >> 10) & 0xf; + u32 mfn = reg & 0x3f; + u32 mfd = (reg >> 16) & 0x3f; + u32 pd = (reg >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + mfd += 1; + pd += 1; + + return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; +} + +static u32 get_mcu_main_clk(void) +{ + u32 arm_div = 0, fi = 0, fd = 0; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); + fi *= + decode_pll(readl(&ccm->mpctl), + CONFIG_MX35_HCLK_FREQ); + return fi / (arm_div * fd); +} + +static u32 get_ipg_clk(void) +{ + u32 freq = get_mcu_main_clk(); + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 pdr0 = readl(&ccm->pdr0); + + return freq / (get_ahb_div(pdr0) * 2); +} + +static u32 get_ipg_per_clk(void) +{ + u32 freq = get_mcu_main_clk(); + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 pdr0 = readl(&ccm->pdr0); + u32 pdr4 = readl(&ccm->pdr4); + u32 div; + if (pdr0 & MXC_CCM_PDR0_PER_SEL) { + div = (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_PER0_PRDF_MASK, + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * + (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_PER0_PODF_MASK, + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + } else { + div = CCM_GET_DIVIDER(pdr0, + MXC_CCM_PDR0_PER_PODF_MASK, + MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; + freq /= get_ahb_div(pdr0); + } + return freq / div; +} + +u32 imx_get_uartclk(void) +{ + u32 freq; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 pdr4 = readl(&ccm->pdr4); + + if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) + freq = get_mcu_main_clk(); + else + freq = decode_pll(readl(&ccm->ppctl), + CONFIG_MX35_HCLK_FREQ); + freq /= ((CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_UART_PRDF_MASK, + MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * + (CCM_GET_DIVIDER(pdr4, + MXC_CCM_PDR4_UART_PODF_MASK, + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + return freq; +} + +unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) +{ + u32 nfc_pdf, hsp_podf; + u32 pll, ret_val = 0, usb_prdf, usb_podf; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + u32 reg = readl(&ccm->pdr0); + u32 reg4 = readl(&ccm->pdr4); + + reg |= 0x1; + + switch (clk) { + case CPU_CLK: + ret_val = get_mcu_main_clk(); + break; + case AHB_CLK: + ret_val = get_mcu_main_clk(); + break; + case HSP_CLK: + if (reg & CLKMODE_CONSUMER) { + hsp_podf = (reg >> 20) & 0x3; + pll = get_mcu_main_clk(); + hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; + if (hsp_podf > 0) { + ret_val = pll / hsp_podf; + } else { + puts("mismatch HSP with ARM clock setting\n"); + ret_val = 0; + } + } else { + ret_val = get_mcu_main_clk(); + } + break; + case IPG_CLK: + ret_val = get_ipg_clk();; + break; + case IPG_PER_CLK: + ret_val = get_ipg_per_clk(); + break; + case NFC_CLK: + nfc_pdf = (reg4 >> 28) & 0xF; + pll = get_mcu_main_clk(); + /* AHB/nfc_pdf */ + ret_val = pll / (nfc_pdf + 1); + break; + case USB_CLK: + usb_prdf = (reg4 >> 25) & 0x7; + usb_podf = (reg4 >> 22) & 0x7; + if (reg4 & 0x200) + pll = get_mcu_main_clk(); + else + pll = decode_pll(readl(&ccm->ppctl), + CONFIG_MX35_HCLK_FREQ); + + ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + break; + default: + printf("Unknown clock: %d\n", clk); + break; + } + + return ret_val; +} +unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel; + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + u32 mpdr2 = readl(&ccm->pdr2); + u32 mpdr3 = readl(&ccm->pdr3); + u32 mpdr4 = readl(&ccm->pdr4); + + switch (clk) { + case UART1_BAUD: + case UART2_BAUD: + case UART3_BAUD: + clk_sel = mpdr3 & (1 << 14); + pre_pdf = (mpdr4 >> 13) & 0x7; + pdf = (mpdr4 >> 10) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case SSI1_BAUD: + pre_pdf = (mpdr2 >> 24) & 0x7; + pdf = mpdr2 & 0x3F; + clk_sel = mpdr2 & (1 << 6); + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case SSI2_BAUD: + pre_pdf = (mpdr2 >> 27) & 0x7; + pdf = (mpdr2 >> 8) & 0x3F; + clk_sel = mpdr2 & (1 << 6); + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case CSI_BAUD: + clk_sel = mpdr2 & (1 << 7); + pre_pdf = (mpdr2 >> 16) & 0x7; + pdf = (mpdr2 >> 19) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case MSHC_CLK: + pre_pdf = readl(&ccm->pdr1); + clk_sel = (pre_pdf & 0x80); + pdf = (pre_pdf >> 22) & 0x3F; + pre_pdf = (pre_pdf >> 28) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC1_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = mpdr3 & 0x7; + pdf = (mpdr3>>3) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC2_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = (mpdr3 >> 8) & 0x7; + pdf = (mpdr3 >> 11) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case ESDHC3_CLK: + clk_sel = mpdr3 & 0x40; + pre_pdf = (mpdr3 >> 16) & 0x7; + pdf = (mpdr3 >> 19) & 0x7; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case SPDIF_CLK: + clk_sel = mpdr3 & 0x400000; + pre_pdf = (mpdr3 >> 29) & 0x7; + pdf = (mpdr3 >> 23) & 0x3F; + ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : + decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / + ((pre_pdf + 1) * (pdf + 1)); + break; + default: + printf("%s(): This clock: %d not supported yet\n", + __func__, clk); + break; + } + + return ret_val; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_mcu_main_clk(); + case MXC_AHB_CLK: + break; + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_IPG_PERCLK: + return get_ipg_per_clk(); + case MXC_UART_CLK: + return imx_get_uartclk(); + case MXC_ESDHC_CLK: + return mxc_get_peri_clock(ESDHC1_CLK); + case MXC_USB_CLK: + return mxc_get_main_clock(USB_CLK); + case MXC_FEC_CLK: + return get_ipg_clk(); + } + return -1; +} + +#ifdef CONFIG_FEC_MXC +/* + * The MX35 has no fuse for MAC, return a NULL MAC + */ +void imx_get_mac_from_fuse(unsigned char *mac) +{ + int i; + + for (i = 0; i < 6; i++) + mac[i] = 0; +} + +u32 imx_get_fecclk(void) +{ + return mxc_get_clock(MXC_IPG_CLK); +} +#endif + +int do_mx35_showclocks(cmd_tbl_t *cmdtp, + int flag, int argc, char * const argv[]) +{ + u32 cpufreq = get_mcu_main_clk(); + printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); + printf("ipg clock : %dHz\n", get_ipg_clk()); + printf("ipg per clock : %dHz\n", get_ipg_per_clk()); + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); + + return 0; +} + +U_BOOT_CMD( + clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, + "display clocks\n", + "" +); + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + printf("CPU: Freescale i.MX35 at %d MHz\n", + get_mcu_main_clk() / 1000000); + /* mxc_dump_clocks(); */ + return 0; +} +#endif + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +#if defined(CONFIG_FEC_MXC) +extern int fecmxc_initialize(bd_t *bis); +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_FEC_MXC) + rc = fecmxc_initialize(bis); +#endif + + return rc; +} + +int get_clocks(void) +{ +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#endif + return 0; +} + +void reset_cpu(ulong addr) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; + writew(4, &wdog->wcr); +} diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c new file mode 100644 index 0000000..316fccc --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/iomux.c @@ -0,0 +1,147 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx35_pins.h> +#include <asm/arch/iomux.h> + +/* + * IOMUX register (base) addresses + */ +enum iomux_reg_addr { + IOMUXGPR = IOMUXC_BASE_ADDR, + /*!< General purpose */ + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, + /*!< MUX control */ + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, + /*!< last MUX control register */ + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, + /*!< Pad control */ + IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, + /*!< last Pad control register */ + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, + /*!< input select register */ + IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, + /*!< last input select register */ +}; + +#define MUX_PIN_NUM_MAX \ + (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1) +#define MUX_INPUT_NUM_MUX \ + (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) + +#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2) + +/* + * This function is used to configure a pin through the IOMUX module. + * FIXED ME: for backward compatible. Will be static function! + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param cfg an output function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (mux_reg != NON_MUX_I) { + mux_reg += IOMUXGPR; + __REG(mux_reg) = cfg; + } + + return 0; +} + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + int ret = iomux_config_mux(pin, cfg); + return ret; +} + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin); + + __REG(pad_reg) = config; +} + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en) +{ + u32 l; + + l = __REG(IOMUXGPR); + if (en) + l |= gp; + else + l &= ~gp; + + __REG(IOMUXGPR) = l; +} + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_config_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config) +{ + u32 reg = IOMUXSW_INPUT_CTL + (input << 2); + + __REG(reg) = config; +} diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c new file mode 100644 index 0000000..fee948b --- /dev/null +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ +#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ +#define GPTPR_VAL (66) + +int timer_init(void) +{ + int i; + struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + + /* setup GP Timer 1 */ + writel(GPTCR_SWR, &gpt->ctrl); + for (i = 0; i < 100; i++) + writel(0, &gpt->ctrl); /* We have no udelay by now */ + + writel(GPTPR_VAL, &gpt->pre); + /* Freerun Mode, PERCLK1 input */ + writel(readl(&gpt->ctrl) | + GPTCR_CLKSOURCE_IPG | GPTCR_TEN, + &gpt->ctrl); + + return 0; +} + +void reset_timer_masked(void) +{ + struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + + writel(0, &gpt->ctrl); + /* Freerun Mode, PERCLK1 input */ + writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN, + &gpt->ctrl); +} + +inline ulong get_timer_masked(void) +{ + + struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; + ulong val = readl(&gpt->counter); + + return val; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + ulong tmp; + + tmp = get_timer_masked(); + + if (tmp <= (base * 1000)) { + /* Overflow */ + tmp += (0xffffffff - base); + } + + return (tmp / 1000) - base; +} + +void set_timer(ulong t) +{ +} + +/* delay x useconds AND perserve advance timstamp value */ +/* GPTCNT is now supposed to tick 1 by 1 us. */ +void __udelay(unsigned long usec) +{ + ulong tmp; + + tmp = get_timer_masked(); /* get current timestamp */ + + /* if setting this forward will roll time stamp */ + if ((usec + tmp + 1) < tmp) { + /* reset "advancing" timestamp to 0, set lastinc value */ + reset_timer_masked(); + } else { + /* else, set advancing stamp wake up time */ + tmp += usec; + } + + while (get_timer_masked() < tmp) /* loop till event */ + /*NOP*/; +} diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h new file mode 100644 index 0000000..282c973 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/clock.h @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_USB_CLK, + MXC_CSPI_CLK, + MXC_FEC_CLK, +}; + +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); + +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h new file mode 100644 index 0000000..e903cf1 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -0,0 +1,270 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ +#define __CPU_ARM1136_MX35_CRM_REGS_H__ + +/* Register bit definitions */ +#define MXC_CCM_CCMR_WFI (1 << 30) +#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) +#define MXC_CCM_CCMR_VSTBY (1 << 28) +#define MXC_CCM_CCMR_WBEN (1 << 27) +#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 +#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) +#define MXC_CCM_CCMR_ROMW_OFFSET 18 +#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) +#define MXC_CCM_CCMR_RAMW_OFFSET 21 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_LPM_OFFSET 14 +#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) +#define MXC_CCM_CCMR_UPE (1 << 9) +#define MXC_CCM_CCMR_MPE (1 << 3) + +#define MXC_CCM_PDR0_PER_SEL (1 << 26) +#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) +#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 +#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) +#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 +#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) +#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) +#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 +#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) +#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 +#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) +#define MXC_CCM_PDR0_AUTO_CON 0x1 + +#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 +#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) +#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 +#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) +#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) + +#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 +#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) +#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 +#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) +#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 +#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 +#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) +#define MXC_CCM_PDR2_CSI_M_U (1 << 7) +#define MXC_CCM_PDR2_SSI_M_U (1 << 6) +#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 +#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) + +#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 +#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) +#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 +#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) +#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) +#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 +#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 15) +#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 +#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) +#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 +#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) +#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) + +#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 +#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) +#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 +#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) +#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 +#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) +#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 +#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 +#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 +#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_USB_M_U (1 << 9) + +/* Bit definitions for RCSR */ +#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) +#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) +#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) +#define MXC_CCM_RCSR_PAGE_512 (0 << 27) +#define MXC_CCM_RCSR_PAGE_2K (1 << 27) +#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) +#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) +#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) +#define MXC_CCM_RCSR_NF16B (1 << 14) +#define MXC_CCM_RCSR_NFC_4K (1 << 9) +#define MXC_CCM_RCSR_NFC_FMS (1 << 8) + +/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ +#define MXC_CCM_PCTL_BRM 0x80000000 +#define MXC_CCM_PCTL_PD_OFFSET 26 +#define MXC_CCM_PCTL_PD_MASK (0xF << 26) +#define MXC_CCM_PCTL_MFD_OFFSET 16 +#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) +#define MXC_CCM_PCTL_MFI_OFFSET 10 +#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) +#define MXC_CCM_PCTL_MFN_OFFSET 0 +#define MXC_CCM_PCTL_MFN_MASK 0x3FF + +/* Bit definitions for Audio clock mux register*/ +#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 +#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 +#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) +#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 +#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) +#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 +#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) + +/* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR0_ASRC_OFFSET 0 +#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) +#define MXC_CCM_CGR0_ATA_OFFSET 2 +#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) +#define MXC_CCM_CGR0_CAN1_OFFSET 6 +#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) +#define MXC_CCM_CGR0_CAN2_OFFSET 8 +#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) +#define MXC_CCM_CGR0_CSPI1_OFFSET 10 +#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) +#define MXC_CCM_CGR0_CSPI2_OFFSET 12 +#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) +#define MXC_CCM_CGR0_ECT_OFFSET 14 +#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) +#define MXC_CCM_CGR0_EDI0_OFFSET 16 +#define MXC_CCM_CGR0_EDI0_MASK (0x3 << 16) +#define MXC_CCM_CGR0_EMI_OFFSET 18 +#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) +#define MXC_CCM_CGR0_EPIT1_OFFSET 20 +#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) +#define MXC_CCM_CGR0_EPIT2_OFFSET 22 +#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) +#define MXC_CCM_CGR0_ESAI_OFFSET 24 +#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) +#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 +#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) +#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 +#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) +#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 +#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) + +#define MXC_CCM_CGR1_FEC_OFFSET 0 +#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) +#define MXC_CCM_CGR1_GPIO1_OFFSET 2 +#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) +#define MXC_CCM_CGR1_GPIO2_OFFSET 4 +#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) +#define MXC_CCM_CGR1_GPIO3_OFFSET 6 +#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) +#define MXC_CCM_CGR1_GPT_OFFSET 8 +#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) +#define MXC_CCM_CGR1_I2C1_OFFSET 10 +#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) +#define MXC_CCM_CGR1_I2C2_OFFSET 12 +#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) +#define MXC_CCM_CGR1_I2C3_OFFSET 14 +#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) +#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 +#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) +#define MXC_CCM_CGR1_IPU_OFFSET 18 +#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) +#define MXC_CCM_CGR1_KPP_OFFSET 20 +#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) +#define MXC_CCM_CGR1_MLB_OFFSET 22 +#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) +#define MXC_CCM_CGR1_MSHC_OFFSET 24 +#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) +#define MXC_CCM_CGR1_OWIRE_OFFSET 26 +#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) +#define MXC_CCM_CGR1_PWM_OFFSET 28 +#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) +#define MXC_CCM_CGR1_RNGC_OFFSET 30 +#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) + +#define MXC_CCM_CGR2_RTC_OFFSET 0 +#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) +#define MXC_CCM_CGR2_RTIC_OFFSET 2 +#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) +#define MXC_CCM_CGR2_SCC_OFFSET 4 +#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) +#define MXC_CCM_CGR2_SDMA_OFFSET 6 +#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) +#define MXC_CCM_CGR2_SPBA_OFFSET 8 +#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) +#define MXC_CCM_CGR2_SPDIF_OFFSET 10 +#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) +#define MXC_CCM_CGR2_SSI1_OFFSET 12 +#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) +#define MXC_CCM_CGR2_SSI2_OFFSET 14 +#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) +#define MXC_CCM_CGR2_UART1_OFFSET 16 +#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) +#define MXC_CCM_CGR2_UART2_OFFSET 18 +#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) +#define MXC_CCM_CGR2_UART3_OFFSET 20 +#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) +#define MXC_CCM_CGR2_USBOTG_OFFSET 22 +#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) +#define MXC_CCM_CGR2_WDOG_OFFSET 24 +#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) +#define MXC_CCM_CGR2_MAX_OFFSET 26 +#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) +#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) +#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 +#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) + +#define MXC_CCM_CGR3_CSI_OFFSET 0 +#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) +#define MXC_CCM_CGR3_IIM_OFFSET 2 +#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) +#define MXC_CCM_CGR3_GPU2D_OFFSET 4 +#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) + +#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F +#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 +#define MXC_CCM_COSR_CLKOEN (1 << 5) +#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) +#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) +#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 +#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) +#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) +#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) +#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) +#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) +#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 +#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) +#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 + +#endif diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h new file mode 100644 index 0000000..f382960 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -0,0 +1,367 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX35_H +#define __ASM_ARCH_MX35_H + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + +#define L2CC_BASE_ADDR 0x30000000 + +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ +#define IRAM_SIZE 0x00020000 /* 128 KB */ + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x43F00000 +#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR +#define MAX_BASE_ADDR 0x43F04000 +#define EVTMON_BASE_ADDR 0x43F08000 +#define CLKCTL_BASE_ADDR 0x43F0C000 +#define I2C_BASE_ADDR 0x43F80000 +#define I2C3_BASE_ADDR 0x43F84000 +#define ATA_BASE_ADDR 0x43F8C000 +#define UART1_BASE_ADDR 0x43F90000 +#define UART2_BASE_ADDR 0x43F94000 +#define I2C2_BASE_ADDR 0x43F98000 +#define CSPI1_BASE_ADDR 0x43FA4000 +#define IOMUXC_BASE_ADDR 0x43FAC000 + +/* + * SPBA + */ +#define SPBA_BASE_ADDR 0x50000000 +#define UART3_BASE_ADDR 0x5000C000 +#define CSPI2_BASE_ADDR 0x50010000 +#define ATA_DMA_BASE_ADDR 0x50020000 +#define FEC_BASE_ADDR 0x50038000 +#define SPBA_CTRL_BASE_ADDR 0x5003C000 + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x53F00000 +#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR +#define CCM_BASE_ADDR 0x53F80000 +#define GPT1_BASE_ADDR 0x53F90000 +#define EPIT1_BASE_ADDR 0x53F94000 +#define EPIT2_BASE_ADDR 0x53F98000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define MMC_SDHC1_BASE_ADDR 0x53FB4000 +#define MMC_SDHC2_BASE_ADDR 0x53FB8000 +#define MMC_SDHC3_BASE_ADDR 0x53FBC000 +#define IPU_CTRL_BASE_ADDR 0x53FC0000 +#define GPIO3_BASE_ADDR 0x53FA4000 +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define SDMA_BASE_ADDR 0x53FD4000 +#define RTC_BASE_ADDR 0x53FD8000 +#define WDOG_BASE_ADDR 0x53FDC000 +#define PWM_BASE_ADDR 0x53FE0000 +#define RTIC_BASE_ADDR 0x53FEC000 +#define IIM_BASE_ADDR 0x53FF0000 + +#define IMX_CCM_BASE CCM_BASE_ADDR + +/* + * ROMPATCH and AVIC + */ +#define ROMPATCH_BASE_ADDR 0x60000000 +#define AVIC_BASE_ADDR 0x68000000 + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define EXT_MEM_CTRL_BASE 0xB8000000 +#define ESDCTL_BASE_ADDR 0xB8001000 +#define WEIM_BASE_ADDR 0xB8002000 +#define WEIM_CTRL_CS0 WEIM_BASE_ADDR +#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) +#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) +#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) +#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) +#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) +#define M3IF_BASE_ADDR 0xB8003000 +#define EMI_BASE_ADDR 0xB8004000 + +#define NFC_BASE_ADDR 0xBB000000 + +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE_ADDR 0x70000000 +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 +#define CS4_BASE_ADDR 0xB4000000 +#define CS5_BASE_ADDR 0xB6000000 + +/* + * IRQ Controller Register Definitions. + */ +#define AVIC_NIMASK 0x04 +#define AVIC_INTTYPEH 0x18 +#define AVIC_INTTYPEL 0x1C + +/* L210 */ +#define L2CC_BASE_ADDR 0x30000000 +#define L2_CACHE_LINE_SIZE 32 +#define L2_CACHE_CTL_REG 0x100 +#define L2_CACHE_AUX_CTL_REG 0x104 +#define L2_CACHE_SYNC_REG 0x730 +#define L2_CACHE_INV_LINE_REG 0x770 +#define L2_CACHE_INV_WAY_REG 0x77C +#define L2_CACHE_CLEAN_LINE_REG 0x7B0 +#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 +#define L2_CACHE_DBG_CTL_REG 0xF40 + +/* CCM */ +#define CLKCTL_CCMR 0x00 +#define CLKCTL_PDR0 0x04 +#define CLKCTL_PDR1 0x08 +#define CLKCTL_PDR2 0x0C +#define CLKCTL_PDR3 0x10 +#define CLKCTL_PDR4 0x14 +#define CLKCTL_RCSR 0x18 +#define CLKCTL_MPCTL 0x1C +#define CLKCTL_PPCTL 0x20 +#define CLKCTL_ACMR 0x24 +#define CLKCTL_COSR 0x28 +#define CLKCTL_CGR0 0x2C +#define CLKCTL_CGR1 0x30 +#define CLKCTL_CGR2 0x34 +#define CLKCTL_CGR3 0x38 + +#define CLKMODE_AUTO 0 +#define CLKMODE_CONSUMER 1 + +#define PLL_PD(x) (((x) & 0xf) << 26) +#define PLL_MFD(x) (((x) & 0x3ff) << 16) +#define PLL_MFI(x) (((x) & 0xf) << 10) +#define PLL_MFN(x) (((x) & 0x3ff) << 0) + +#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) +#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) +#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) + +#define IIM_SREV 0x24 +#define ROMPATCH_REV 0x40 + +#define IPU_CONF IPU_CTRL_BASE_ADDR + +#define IPU_CONF_PXL_ENDIAN (1<<8) +#define IPU_CONF_DU_EN (1<<7) +#define IPU_CONF_DI_EN (1<<6) +#define IPU_CONF_ADC_EN (1<<5) +#define IPU_CONF_SDC_EN (1<<4) +#define IPU_CONF_PF_EN (1<<3) +#define IPU_CONF_ROT_EN (1<<2) +#define IPU_CONF_IC_EN (1<<1) +#define IPU_CONF_SCI_EN (1<<0) + +#define GPIO_PORT_NUM 3 +#define GPIO_NUM_PIN 32 + +#define NFC_BUF_SIZE 0x1000 +#define NFC_BUFSIZE_REG_OFF (0 + 0x00) +#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04) +#define NAND_FLASH_ADD_REG_OFF (0 + 0x06) +#define NAND_FLASH_CMD_REG_OFF (0 + 0x08) +#define NFC_CONFIGURATION_REG_OFF (0 + 0x0A) +#define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C) +#define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E) +#define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10) +#define NF_WR_PROT_REG_OFF (0 + 0x12) +#define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18) +#define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A) +#define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C) +#define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x20) +#define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x22) +#define RAM_BUFFER_ADDRESS_RBA_3 0x3 +#define NFC_BUFSIZE_1KB 0x0 +#define NFC_BUFSIZE_2KB 0x1 +#define NFC_CONFIGURATION_UNLOCKED 0x2 +#define ECC_STATUS_RESULT_NO_ERR 0x0 +#define ECC_STATUS_RESULT_1BIT_ERR 0x1 +#define ECC_STATUS_RESULT_2BIT_ERR 0x2 +#define NF_WR_PROT_UNLOCK 0x4 +#define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7) +#define NAND_FLASH_CONFIG1_RST (1 << 6) +#define NAND_FLASH_CONFIG1_BIG (1 << 5) +#define NAND_FLASH_CONFIG1_INT_MSK (1 << 4) +#define NAND_FLASH_CONFIG1_ECC_EN (1 << 3) +#define NAND_FLASH_CONFIG1_SP_EN (1 << 2) +#define NAND_FLASH_CONFIG2_INT_DONE (1 << 15) +#define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3) +#define NAND_FLASH_CONFIG2_FDO_ID (2 << 3) +#define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3) +#define NAND_FLASH_CONFIG2_FDI_EN (1 << 2) +#define NAND_FLASH_CONFIG2_FADD_EN (1 << 1) +#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0) +#define FDO_PAGE_SPARE_VAL 0x8 +#define NAND_BUF_NUM 8 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_2_0 0x20 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> + +enum plls { + MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL, + PER_PLL = CCM_BASE_ADDR + CLKCTL_PPCTL, +}; + +enum mxc_main_clocks { + CPU_CLK, + AHB_CLK, + IPG_CLK, + IPG_PER_CLK, + NFC_CLK, + USB_CLK, + HSP_CLK, +}; + +enum mxc_peri_clocks { + UART1_BAUD, + UART2_BAUD, + UART3_BAUD, + SSI1_BAUD, + SSI2_BAUD, + CSI_BAUD, + MSHC_CLK, + ESDHC1_CLK, + ESDHC2_CLK, + ESDHC3_CLK, + SPDIF_CLK, + SPI1_CLK, + SPI2_CLK, +}; + +/* Clock Control Module (CCM) registers */ +struct ccm_regs { + u32 ccmr; /* Control */ + u32 pdr0; /* Post divider 0 */ + u32 pdr1; /* Post divider 1 */ + u32 pdr2; /* Post divider 2 */ + u32 pdr3; /* Post divider 3 */ + u32 pdr4; /* Post divider 4 */ + u32 rcsr; /* CCM Status */ + u32 mpctl; /* Core PLL Control */ + u32 ppctl; /* Peripheral PLL Control */ + u32 acmr; /* Audio clock mux */ + u32 cosr; /* Clock out source */ + u32 cgr0; /* Clock Gating Control 0 */ + u32 cgr1; /* Clock Gating Control 1 */ + u32 cgr2; /* Clock Gating Control 2 */ + u32 cgr3; /* Clock Gating Control 3 */ + u32 reserved; + u32 dcvr0; /* DPTC Comparator 0 */ + u32 dcvr1; /* DPTC Comparator 0 */ + u32 dcvr2; /* DPTC Comparator 0 */ + u32 dcvr3; /* DPTC Comparator 0 */ + u32 ltr0; /* Load Tracking 0 */ + u32 ltr1; /* Load Tracking 1 */ + u32 ltr2; /* Load Tracking 2 */ + u32 ltr3; /* Load Tracking 3 */ + u32 ltbr0; /* Load Tracking Buffer 0 */ +}; + +/* IIM control registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prog_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; +}; + +/* General Purpose Timer (GPT) registers */ +struct gpt_regs { + u32 ctrl; /* control */ + u32 pre; /* prescaler */ + u32 stat; /* status */ + u32 intr; /* interrupt */ + u32 cmp[3]; /* output compare 1-3 */ + u32 capt[2]; /* input capture 1-2 */ + u32 counter; /* counter */ +}; + +/* Watchdog Timer (WDOG) registers */ +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ + u16 wicr; /* Interrupt Control */ + u16 wmcr; /* Misc Control */ +}; + +/*! + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS (*((volatile u32 *)(CCM_BASE_ADDR + 0x18))) +#define NFMS_BIT 8 +#define NFMS_NF_DWIDTH 14 +#define NFMS_NF_PG_SZ 8 + +#define CCM_RCSR_NF_16BIT_SEL (1 << 14) + +#if 0 +extern unsigned int mxc_get_clock(enum mxc_clock clk); +#endif +extern unsigned int get_board_rev(void); +extern int is_soc_rev(int rev); +extern int sdhc_init(void); + +#define fixup_before_linux \ + { \ + volatile unsigned long *l2cc_ctl = (unsigned long *)0x30000100;\ + if (is_soc_rev(CHIP_REV_2_0) < 0) \ + *l2cc_ctl = 1;\ + } +#endif +#endif /* __ASM_ARCH_MX35_H */ diff --git a/arch/arm/include/asm/arch-mx35/iomux.h b/arch/arm/include/asm/arch-mx35/iomux.h new file mode 100644 index 0000000..86bf607 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/iomux.h @@ -0,0 +1,290 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __MACH_MX35_IOMUX_H__ +#define __MACH_MX35_IOMUX_H__ + +#include <asm/arch/imx-regs.h> + +/*! + * @file mach-mx35/iomux.h + * + * @brief I/O Muxing control definitions and functions + * + * @ingroup GPIO_MX35 + */ + +/*! + * various IOMUX functions + */ +typedef enum iomux_pin_config { + MUX_CONFIG_FUNC = 0, /*!< used as function */ + MUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + MUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + MUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + MUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + MUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + MUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + MUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ + MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */ +} iomux_pin_cfg_t; + +/*! + * various IOMUX pad functions + */ +typedef enum iomux_pad_config { + PAD_CTL_DRV_3_3V = 0x0 << 13, + PAD_CTL_DRV_1_8V = 0x1 << 13, + PAD_CTL_HYS_CMOS = 0x0 << 8, + PAD_CTL_HYS_SCHMITZ = 0x1 << 8, + PAD_CTL_PKE_NONE = 0x0 << 7, + PAD_CTL_PKE_ENABLE = 0x1 << 7, + PAD_CTL_PUE_KEEPER = 0x0 << 6, + PAD_CTL_PUE_PUD = 0x1 << 6, + PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_100K_PU = 0x2 << 4, + PAD_CTL_22K_PU = 0x3 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +} iomux_pad_config_t; + +/*! + * various IOMUX general purpose functions + */ +typedef enum iomux_gp_func { + MUX_SDCTL_CSD0_SEL = 0x1 << 0, + MUX_SDCTL_CSD1_SEL = 0x1 << 1, + MUX_TAMPER_DETECT_EN = 0x1 << 2, +} iomux_gp_func_t; + +/*! + * various IOMUX input select register index + */ +typedef enum iomux_input_select { + MUX_IN_AMX_P5_RXCLK = 0, + MUX_IN_AMX_P5_RXFS, + MUX_IN_AMX_P6_DA, + MUX_IN_AMX_P6_DB, + MUX_IN_AMX_P6_RXCLK, + MUX_IN_AMX_P6_RXFS, + MUX_IN_AMX_P6_TXCLK, + MUX_IN_AMX_P6_TXFS, + MUX_IN_CAN1_CANRX, + MUX_IN_CAN2_CANRX, + MUX_IN_CCM_32K_MUXED, + MUX_IN_CCM_PMIC_RDY, + MUX_IN_CSPI1_SS2_B, + MUX_IN_CSPI1_SS3_B, + MUX_IN_CSPI2_CLK_IN, + MUX_IN_CSPI2_DATAREADY_B, + MUX_IN_CSPI2_MISO, + MUX_IN_CSPI2_MOSI, + MUX_IN_CSPI2_SS0_B, + MUX_IN_CSPI2_SS1_B, + MUX_IN_CSPI2_SS2_B, + MUX_IN_CSPI2_SS3_B, + MUX_IN_EMI_WEIM_DTACK_B, + MUX_IN_ESDHC1_DAT4_IN, + MUX_IN_ESDHC1_DAT5_IN, + MUX_IN_ESDHC1_DAT6_IN, + MUX_IN_ESDHC1_DAT7_IN, + MUX_IN_ESDHC3_CARD_CLK_IN, + MUX_IN_ESDHC3_CMD_IN, + MUX_IN_ESDHC3_DAT0, + MUX_IN_ESDHC3_DAT1, + MUX_IN_ESDHC3_DAT2, + MUX_IN_ESDHC3_DAT3, + MUX_IN_GPIO1_IN_0, + MUX_IN_GPIO1_IN_10, + MUX_IN_GPIO1_IN_11, + MUX_IN_GPIO1_IN_1, + MUX_IN_GPIO1_IN_20, + MUX_IN_GPIO1_IN_21, + MUX_IN_GPIO1_IN_22, + MUX_IN_GPIO1_IN_2, + MUX_IN_GPIO1_IN_3, + MUX_IN_GPIO1_IN_4, + MUX_IN_GPIO1_IN_5, + MUX_IN_GPIO1_IN_6, + MUX_IN_GPIO1_IN_7, + MUX_IN_GPIO1_IN_8, + MUX_IN_GPIO1_IN_9, + MUX_IN_GPIO2_IN_0, + MUX_IN_GPIO2_IN_10, + MUX_IN_GPIO2_IN_11, + MUX_IN_GPIO2_IN_12, + MUX_IN_GPIO2_IN_13, + MUX_IN_GPIO2_IN_14, + MUX_IN_GPIO2_IN_15, + MUX_IN_GPIO2_IN_16, + MUX_IN_GPIO2_IN_17, + MUX_IN_GPIO2_IN_18, + MUX_IN_GPIO2_IN_19, + MUX_IN_GPIO2_IN_20, + MUX_IN_GPIO2_IN_21, + MUX_IN_GPIO2_IN_22, + MUX_IN_GPIO2_IN_23, + MUX_IN_GPIO2_IN_24, + MUX_IN_GPIO2_IN_25, + MUX_IN_GPIO2_IN_26, + MUX_IN_GPIO2_IN_27, + MUX_IN_GPIO2_IN_28, + MUX_IN_GPIO2_IN_29, + MUX_IN_GPIO2_IN_2, + MUX_IN_GPIO2_IN_30, + MUX_IN_GPIO2_IN_31, + MUX_IN_GPIO2_IN_3, + MUX_IN_GPIO2_IN_4, + MUX_IN_GPIO2_IN_5, + MUX_IN_GPIO2_IN_6, + MUX_IN_GPIO2_IN_7, + MUX_IN_GPIO2_IN_8, + MUX_IN_GPIO2_IN_9, + MUX_IN_GPIO3_IN_0, + MUX_IN_GPIO3_IN_10, + MUX_IN_GPIO3_IN_11, + MUX_IN_GPIO3_IN_12, + MUX_IN_GPIO3_IN_13, + MUX_IN_GPIO3_IN_14, + MUX_IN_GPIO3_IN_15, + MUX_IN_GPIO3_IN_4, + MUX_IN_GPIO3_IN_5, + MUX_IN_GPIO3_IN_6, + MUX_IN_GPIO3_IN_7, + MUX_IN_GPIO3_IN_8, + MUX_IN_GPIO3_IN_9, + MUX_IN_I2C3_SCL_IN, + MUX_IN_I2C3_SDA_IN, + MUX_IN_IPU_DISPB_D0_VSYNC, + MUX_IN_IPU_DISPB_D12_VSYNC, + MUX_IN_IPU_DISPB_SD_D, + MUX_IN_IPU_SENSB_DATA_0, + MUX_IN_IPU_SENSB_DATA_1, + MUX_IN_IPU_SENSB_DATA_2, + MUX_IN_IPU_SENSB_DATA_3, + MUX_IN_IPU_SENSB_DATA_4, + MUX_IN_IPU_SENSB_DATA_5, + MUX_IN_IPU_SENSB_DATA_6, + MUX_IN_IPU_SENSB_DATA_7, + MUX_IN_KPP_COL_0, + MUX_IN_KPP_COL_1, + MUX_IN_KPP_COL_2, + MUX_IN_KPP_COL_3, + MUX_IN_KPP_COL_4, + MUX_IN_KPP_COL_5, + MUX_IN_KPP_COL_6, + MUX_IN_KPP_COL_7, + MUX_IN_KPP_ROW_0, + MUX_IN_KPP_ROW_1, + MUX_IN_KPP_ROW_2, + MUX_IN_KPP_ROW_3, + MUX_IN_KPP_ROW_4, + MUX_IN_KPP_ROW_5, + MUX_IN_KPP_ROW_6, + MUX_IN_KPP_ROW_7, + MUX_IN_OWIRE_BATTERY_LINE, + MUX_IN_SPDIF_HCKT_CLK2, + MUX_IN_SPDIF_SPDIF_IN1, + MUX_IN_UART3_UART_RTS_B, + MUX_IN_UART3_UART_RXD_MUX, + MUX_IN_USB_OTG_DATA_0, + MUX_IN_USB_OTG_DATA_1, + MUX_IN_USB_OTG_DATA_2, + MUX_IN_USB_OTG_DATA_3, + MUX_IN_USB_OTG_DATA_4, + MUX_IN_USB_OTG_DATA_5, + MUX_IN_USB_OTG_DATA_6, + MUX_IN_USB_OTG_DATA_7, + MUX_IN_USB_OTG_DIR, + MUX_IN_USB_OTG_NXT, + MUX_IN_USB_UH2_DATA_0, + MUX_IN_USB_UH2_DATA_1, + MUX_IN_USB_UH2_DATA_2, + MUX_IN_USB_UH2_DATA_3, + MUX_IN_USB_UH2_DATA_4, + MUX_IN_USB_UH2_DATA_5, + MUX_IN_USB_UH2_DATA_6, + MUX_IN_USB_UH2_DATA_7, + MUX_IN_USB_UH2_DIR, + MUX_IN_USB_UH2_NXT, + MUX_IN_USB_UH2_USB_OC, +} iomux_input_select_t; + +/*! + * various IOMUX input functions + */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_cfg_t; + +/*! + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * Release ownership for an IO pin + * + * @param pin a name defined by \b iomux_pin_name_t + * @param cfg an input function as defined in \b #iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); + +/*! + * This function enables/disables the general purpose function for a particular + * signal. + * + * @param gp one signal as defined in \b #iomux_gp_func_t + * @param en \b #true to enable; \b #false to disable + */ +void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en); + +/*! + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in \b #iomux_pin_name_t + * @param config the ORed value of elements defined in \b + * #iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); + +/*! + * This function configures input path. + * + * @param input index of input select register as defined in \b + * #iomux_input_select_t + * @param config the binary value of elements defined in \b + * #iomux_input_cfg_t + */ +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); +#endif diff --git a/arch/arm/include/asm/arch-mx35/mmu.h b/arch/arm/include/asm/arch-mx35/mmu.h new file mode 100644 index 0000000..1b15dba --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/mmu.h @@ -0,0 +1,172 @@ +/* + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ARM_ARCH_MMU_H +#define __ARM_ARCH_MMU_H + +/* + * Translation Table Base Bit Masks + */ +#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000 + +/* + * Domain Access Control Bit Masks + */ +#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2) +#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2) +#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2) + +struct ARM_MMU_FIRST_LEVEL_FAULT { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0 + +struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE { + unsigned int id:2; + unsigned int imp:2; + unsigned int domain:4; + unsigned int sbz:1; + unsigned int base_address:23; +}; + +#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1 + +struct ARM_MMU_FIRST_LEVEL_SECTION { + unsigned int id:2; + unsigned int b:1; + unsigned int c:1; + unsigned int imp:1; + unsigned int domain:4; + unsigned int sbz0:1; + unsigned int ap:2; + unsigned int sbz1:8; + unsigned int base_address:12; +}; + +#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2 + +struct ARM_MMU_FIRST_LEVEL_RESERVED { + unsigned int id:2; + unsigned int sbz:30; +}; + +#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3 + +#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ + (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2)) + +#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000 + +#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \ + cacheable, bufferable, perm) \ + { \ + register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ + desc.word = 0; \ + desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ + desc.section.domain = 0; \ + desc.section.c = (cacheable); \ + desc.section.b = (bufferable); \ + desc.section.ap = (perm); \ + desc.section.base_address = (actual_base); \ + *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \ + = desc.word; \ + } + +#define X_ARM_MMU_SECTION(abase, vbase, size, cache, buff, access) \ + { \ + int i; int j = abase; int k = vbase; \ + for (i = size; i > 0 ; i--, j++, k++) \ + ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \ + } + +union ARM_MMU_FIRST_LEVEL_DESCRIPTOR { + unsigned long word; + struct ARM_MMU_FIRST_LEVEL_FAULT fault; + struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table; + struct ARM_MMU_FIRST_LEVEL_SECTION section; + struct ARM_MMU_FIRST_LEVEL_RESERVED reserved; +}; + +#define ARM_UNCACHEABLE 0 +#define ARM_CACHEABLE 1 +#define ARM_UNBUFFERABLE 0 +#define ARM_BUFFERABLE 1 + +#define ARM_ACCESS_PERM_NONE_NONE 0 +#define ARM_ACCESS_PERM_RO_NONE 0 +#define ARM_ACCESS_PERM_RO_RO 0 +#define ARM_ACCESS_PERM_RW_NONE 1 +#define ARM_ACCESS_PERM_RW_RO 2 +#define ARM_ACCESS_PERM_RW_RW 3 + +/* + * Initialization for the Domain Access Control Register + */ +#define ARM_ACCESS_DACR_DEFAULT ( \ + ARM_ACCESS_TYPE_MANAGER(0) | \ + ARM_ACCESS_TYPE_NO_ACCESS(1) | \ + ARM_ACCESS_TYPE_NO_ACCESS(2) | \ + ARM_ACCESS_TYPE_NO_ACCESS(3) | \ + ARM_ACCESS_TYPE_NO_ACCESS(4) | \ + ARM_ACCESS_TYPE_NO_ACCESS(5) | \ + ARM_ACCESS_TYPE_NO_ACCESS(6) | \ + ARM_ACCESS_TYPE_NO_ACCESS(7) | \ + ARM_ACCESS_TYPE_NO_ACCESS(8) | \ + ARM_ACCESS_TYPE_NO_ACCESS(9) | \ + ARM_ACCESS_TYPE_NO_ACCESS(10) | \ + ARM_ACCESS_TYPE_NO_ACCESS(11) | \ + ARM_ACCESS_TYPE_NO_ACCESS(12) | \ + ARM_ACCESS_TYPE_NO_ACCESS(13) | \ + ARM_ACCESS_TYPE_NO_ACCESS(14) | \ + ARM_ACCESS_TYPE_NO_ACCESS(15)) + +/* + * Translate the virtual address of ram space to physical address + * It is dependent on the implementation of mmu_init + */ +inline unsigned long iomem_to_phys(unsigned long virt) +{ + if (virt < 0x08000000) + return (unsigned long)(virt | PHYS_SDRAM_1); + + if ((virt & 0xF0000000) == PHYS_SDRAM_1) + return (unsigned long)(virt & (~0x08000000)); + + return (unsigned long)virt; +} + +/* + * Remap the physical address of ram space to uncacheable virtual address space + * It is dependent on the implementation of hal_mmu_init + */ +void __iounmap(void *addr) +{ + return; +} + +void *__ioremap(unsigned long offset, size_t size, unsigned long flags) +{ + if (1 == flags) { + /* 0x88000000~0x87FFFFFF is uncacheable meory + space which is mapped to SDRAM */ + if ((offset & 0xF0000000) == PHYS_SDRAM_1) + return (void *)(offset | 0x08000000); + else + return NULL; + } else + return (void *)offset; +} + +#endif diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h new file mode 100644 index 0000000..be4012b --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/mx35_pins.h @@ -0,0 +1,342 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ASM_ARCH_MXC_MX35_PINS_H__ +#define __ASM_ARCH_MXC_MX35_PINS_H__ + +/*! + * @file arch-mxc/mx35_pins.h + * + * @brief MX35 I/O Pin List + * + * @ingroup GPIO_MX35 + */ + +#ifndef __ASSEMBLY__ + +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | RSVD | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 7 contains MUX_I used to identify the register + * offset (base is IOMUX_module_base ) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field + * definitions are used for the pad control register.the MX35_PIN_A0 is + * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I) + * So the absolute address is: IOMUX_module_base + 0x28. + * The pad control register offset is: 0x368. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * reserved filed + */ +#define RSVD_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ + ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) + +#define NON_GPIO_I 0x7 +#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1) +#define NON_MUX_I PIN_TO_MUX_MASK + +#define _MXC_BUILD_PIN(gp, gi, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | ((pi) << PAD_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) + +/*! @} End IOMUX/PAD Bit field definitions */ + +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +typedef enum iomux_pins { + MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328), + MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C), + MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330), + MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334), + MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338), + MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C), + MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340), + MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C), + + MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360), + MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364), + MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368), + MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C), + MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370), + MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374), + MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378), + MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C), + MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380), + MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384), + MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388), + MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C), + MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390), + MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394), + MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398), + MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C), + MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0), + MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4), + MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8), + MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC), + MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0), + MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4), + MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8), + MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC), + MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0), + MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4), + MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8), + MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC), + MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0), + + MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C), + MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470), + MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474), + MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478), + MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C), + MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480), + MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484), + MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488), + MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C), + MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490), + + MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498), + MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C), + MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0), + + MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC), + MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0), + MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4), + MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8), + MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC), + MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0), + + MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4), + MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8), + MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC), + MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0), + MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4), + MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8), + MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC), + MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500), + MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504), + MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508), + MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C), + MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510), + MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514), + MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518), + MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C), + MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520), + + MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524), + MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528), + MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C), + MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530), + MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534), + MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538), + MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C), + MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540), + MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544), + MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548), + MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C), + MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550), + + MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554), + MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558), + MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C), + MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560), + + MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564), + MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568), + MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C), + MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570), + MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574), + MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578), + MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C), + MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580), + + MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584), + MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588), + MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C), + MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590), + MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594), + MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598), + MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C), + MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0), + MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4), + MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8), + MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC), + MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0), + + MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4), + MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8), + MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC), + MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0), + MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4), + MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8), + + MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC), + MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0), + MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4), + MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8), + MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC), + MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0), + MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4), + MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8), + + MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C), + MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610), + + MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614), + MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618), + MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C), + MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620), + MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624), + MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628), + MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C), + MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630), + MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634), + MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638), + MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C), + MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640), + MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644), + MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648), + MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C), + MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650), + MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654), + MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658), + MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C), + MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660), + MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664), + MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668), + MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C), + MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670), + + MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674), + MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678), + MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C), + MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680), + MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684), + MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688), + MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C), + MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690), + + MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694), + MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698), + MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C), + MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0), + MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4), + MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8), + MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC), + MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0), + MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4), + MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8), + MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC), + MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0), + + MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4), + MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8), + MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC), + MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0), + MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4), + MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8), + MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC), + MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0), + MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4), + MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8), + MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC), + MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0), + MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4), + MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8), + MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC), + MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700), + MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704), + MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708), + MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C), + MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710), + MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714), + MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718), + MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C), + MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720), + MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724), + MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728), + MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C), + MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730), + MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734), + + MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738), + MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C), + MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740), + + MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744), + MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748), + MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C), + MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750), + MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754), + MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758), + MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C), + MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760), + MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764), + MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768), + MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C), + MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770), + MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774), + MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778), + MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C), + MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780), + MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784), + MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788), +} iomux_pin_name_t; + +#endif +#endif diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h new file mode 100644 index 0000000..f687503 --- /dev/null +++ b/arch/arm/include/asm/arch-mx35/sys_proto.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_cpu_rev(void); +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +void sdelay(unsigned long); + +#endif -- 1.7.1

5 26

[U-Boot] [PATCH v2] include/linux/mii.h: update for supporting GE
by Macpaul Lin 21 Jan '11

21 Jan '11

This file has been synced (copy) from Linux source code. This commit was based on kernel 2.6.32. It updates gigabit related phy registers and basic definitions. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Change v1: pull header file from Linux. Change v2: clean up unused code for u-boot. include/linux/mii.h | 181 ++++++++++++++++++++++++++++++--------------------- 1 files changed, 107 insertions(+), 74 deletions(-) diff --git a/include/linux/mii.h b/include/linux/mii.h index 7c63095..6e7ffab 100644 --- a/include/linux/mii.h +++ b/include/linux/mii.h @@ -10,98 +10,132 @@ /* Generic MII registers. */ -#define MII_BMCR 0x00 /* Basic mode control register */ -#define MII_BMSR 0x01 /* Basic mode status register */ -#define MII_PHYSID1 0x02 /* PHYS ID 1 */ -#define MII_PHYSID2 0x03 /* PHYS ID 2 */ -#define MII_ADVERTISE 0x04 /* Advertisement control reg */ -#define MII_LPA 0x05 /* Link partner ability reg */ -#define MII_EXPANSION 0x06 /* Expansion register */ -#define MII_DCOUNTER 0x12 /* Disconnect counter */ -#define MII_FCSCOUNTER 0x13 /* False carrier counter */ -#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ -#define MII_RERRCOUNTER 0x15 /* Receive error counter */ -#define MII_SREVISION 0x16 /* Silicon revision */ -#define MII_RESV1 0x17 /* Reserved... */ -#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ -#define MII_PHYADDR 0x19 /* PHY address */ -#define MII_RESV2 0x1a /* Reserved... */ -#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ -#define MII_NCONFIG 0x1c /* Network interface config */ +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define MII_STAT1000 0x0a /* 1000BASE-T status */ +#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ /* Basic mode control register. */ -#define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ -#define BMCR_CTST 0x0080 /* Collision test */ -#define BMCR_FULLDPLX 0x0100 /* Full duplex */ -#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ -#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ -#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ -#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ -#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ -#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ -#define BMCR_RESET 0x8000 /* Reset the DP83840 */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ /* Basic mode status register. */ -#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ -#define BMSR_JCD 0x0002 /* Jabber detected */ -#define BMSR_LSTATUS 0x0004 /* Link status */ -#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ -#define BMSR_RFAULT 0x0010 /* Remote fault detected */ -#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ -#define BMSR_RESV 0x07c0 /* Unused... */ -#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ -#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ -#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ -#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ -#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ /* Advertisement control register. */ -#define ADVERTISE_SLCT 0x001f /* Selector bits */ -#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ -#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ -#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ -#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ -#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ -#define ADVERTISE_RESV 0x1c00 /* Unused... */ -#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ +#define ADVERTISE_RESV 0x1000 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) + ADVERTISE_100HALF | ADVERTISE_100FULL) /* Link partner ability register. */ -#define LPA_SLCT 0x001f /* Same as advertise selector */ -#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ -#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ -#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ -#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ -#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ -#define LPA_RESV 0x1c00 /* Unused... */ -#define LPA_RFAULT 0x2000 /* Link partner faulted */ -#define LPA_LPACK 0x4000 /* Link partner acked us */ -#define LPA_NPAGE 0x8000 /* Next page bit */ +#define LPA_SLCT 0x001f /* Same as advertise selector */ +#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ +#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ +#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ +#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ +#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ +#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ +#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ +#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ +#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ +#define LPA_PAUSE_CAP 0x0400 /* Can pause */ +#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ +#define LPA_RESV 0x1000 /* Unused... */ +#define LPA_RFAULT 0x2000 /* Link partner faulted */ +#define LPA_LPACK 0x4000 /* Link partner acked us */ +#define LPA_NPAGE 0x8000 /* Next page bit */ #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ -#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ -#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ -#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ -#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ -#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ -#define EXPANSION_RESV 0xffe0 /* Unused... */ +#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ +#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ +#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ +#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ +#define EXPANSION_RESV 0xffe0 /* Unused... */ + +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ -#define NWAYTEST_RESV1 0x00ff /* Unused... */ -#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ -#define NWAYTEST_RESV2 0xfe00 /* Unused... */ +#define NWAYTEST_RESV1 0x00ff /* Unused... */ +#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ +#define NWAYTEST_RESV2 0xfe00 /* Unused... */ + +/* 1000BASE-T Control register */ +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ +/* 1000BASE-T Status register */ +#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ +#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ +#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ +#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ + +/* Flow control flags */ +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result @@ -114,7 +148,7 @@ * * The one exception to IEEE 802.3u is that 100baseT4 is placed * between 100T-full and 100T-half. If your phy does not support - * 100T4 this is fine. If your phy places 100T4 elsewhere in the + * 100T4 this is fine. If your phy places 100T4 elsewhere in the * priority order, you will need to roll your own function. */ static inline unsigned int mii_nway_result (unsigned int negotiated) @@ -154,5 +188,4 @@ static inline unsigned int mii_duplex (unsigned int duplex_lock, return 0; } - #endif /* __LINUX_MII_H__ */ -- 1.7.3.2

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[U-Boot] [PATCH V2 1/2] Don't add symlink in srctree when using an objtree
by Loïc Minier 21 Jan '11

21 Jan '11

When building with srctree != objtree, the build creates arch/soc/cpu specific symlinks in the source tree. This means that the same source tree can't be used for multiple builds at the same time. Also, these symlinks in the source tree are only cleaned up if one passes the same O= to distclean. When srctree != objtree, mkconfig creates an $objtree/include2 directory in the objtree to host the asm -> arch/$arch/include/asm symlink so that "#include <asm>" can be used. But it also creates another identical symlink in $objtree/include. Then, mkconfig creates two symlinks: $objtree/include/asm/arch -> arch/$arch/include/asm/arch-$cpu (or $soc) $objtree/include/asm/proc -> arch/$arch/include/asm/proc-armv (on arm) but because $objtree/include/asm points at $srctree already, the two symlinks are created under $srctree. To fix this, create a real $objtree/include/asm directory, instead of a symlink. Update cleanup code accordingly. Signed-off-by: Loïc Minier <loic.minier(a)linaro.org> --- Makefile | 2 +- mkconfig | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 9055028..7c02096 100644 --- a/Makefile +++ b/Makefile @@ -1243,7 +1243,7 @@ clobber: clean @rm -f $(obj)u-boot.imx @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c - @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm + @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @rm -fr $(obj)include/generated @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f diff --git a/mkconfig b/mkconfig index db69336..6ff533f 100755 --- a/mkconfig +++ b/mkconfig @@ -98,8 +98,7 @@ if [ "$SRCTREE" != "$OBJTREE" ] ; then ln -s ${SRCTREE}/arch/${arch}/include/asm asm LNPREFIX=${SRCTREE}/arch/${arch}/include/asm/ cd ../include - rm -f asm - ln -s ${SRCTREE}/arch/${arch}/include/asm asm + mkdir -p asm else cd ./include rm -f asm -- 1.7.2.3

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