August 2010 - U-Boot

[U-Boot-Users] Ethernet loopback command
by Thomas Schäfer 17 Apr '12

17 Apr '12

Hi, The patch attached provides a command called 'ethloop' which allows to perform loopback testing on the current eth device. To achieve this, a new ethernet packet type (PROT_TEST, 0x0808, AFAIK this is not used otherwise) is introduced in net/net.c. The patch is against SF CVS from 20050307. The functions EthLoopStart, EthLoopSend and EthLoopHandler generate a simple ethernet frame with NetOurEther as destination address and packet type PROT_TEST. The looped back package is compared with the original one and a message is displayed. It is necessary to set the ethernet line into loopback mode either by programming the PHY or using a loopback plug. I've tested this on our PPC405 custom board, but it should also work on all other systems because packet generation is independent of the underlying ethernet hardware. Example usage: => mii w 0 0 7100 <-- sets PHY into loopback mode => ethloop Using ppc_405x_eth0 device Got ethernet loopback frame, len=64 loopback test successfully completed => mii w 0 0 8000 <-- PHY reset after test is completed Maybe this is also useful for others.. Best regards, Thomas Schäfer ____________________________________ Kontron Modular Computers GmbH Konrad-Zuse-Str. 9 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: thomas.schaefer(a)kontron.com

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[U-Boot] [PATCH] MIPS: Add initial support for EMMA3SL/LP
by Serge Ziryukin 03 Apr '12

03 Apr '12

This patch adds initial support for EMMA3SL/LP board. Network and USB support will be added as follow up patches. Signed-off-by: Serge Ziryukin <ftrvxmtrx(a)gmail.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/emma3sllp/Makefile | 45 +++++++++ board/emma3sllp/config.mk | 28 ++++++ board/emma3sllp/emma3sllp.c | 39 ++++++++ board/emma3sllp/emma3sllp.h | 51 +++++++++++ board/emma3sllp/lowlevel_init.S | 190 +++++++++++++++++++++++++++++++++++++++ board/emma3sllp/u-boot.lds | 70 ++++++++++++++ doc/README.emma3sllp | 10 ++ include/configs/emma3sllp.h | 131 +++++++++++++++++++++++++++ 11 files changed, 572 insertions(+), 0 deletions(-) create mode 100644 board/emma3sllp/Makefile create mode 100644 board/emma3sllp/config.mk create mode 100644 board/emma3sllp/emma3sllp.c create mode 100644 board/emma3sllp/emma3sllp.h create mode 100644 board/emma3sllp/lowlevel_init.S create mode 100644 board/emma3sllp/u-boot.lds create mode 100644 doc/README.emma3sllp create mode 100644 include/configs/emma3sllp.h diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..ec5927d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -841,6 +841,10 @@ Stefan Roese <sr(a)denx.de> vct_xxx MIPS32 4Kc +Serge Ziryukin <ftrvxmtrx(a)gmail.com> + + emma3sllp MIPS32 4KEc + ######################################################################### # Nios-32 Systems: # # # diff --git a/MAKEALL b/MAKEALL index bb09627..75c07ef 100755 --- a/MAKEALL +++ b/MAKEALL @@ -741,6 +741,7 @@ LIST_arm=" \ ######################################################################### LIST_mips4kc=" \ + emma3sllp \ incaip \ qemu_mips \ vct_platinum \ diff --git a/Makefile b/Makefile index 82cbbf4..0bbbbf1 100644 --- a/Makefile +++ b/Makefile @@ -3408,6 +3408,9 @@ vct_platinumavc_onenand_small_config: unconfig fi @$(MKCONFIG) -a vct mips mips vct micronas +emma3sllp_config: unconfig + @$(MKCONFIG) $(@:_config=) mips mips emma3sllp + ######################################################################### ## MIPS32 AU1X00 ######################################################################### diff --git a/board/emma3sllp/Makefile b/board/emma3sllp/Makefile new file mode 100644 index 0000000..aa42b44 --- /dev/null +++ b/board/emma3sllp/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/emma3sllp/config.mk b/board/emma3sllp/config.mk new file mode 100644 index 0000000..d4ff9b5 --- /dev/null +++ b/board/emma3sllp/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2010 +# Serge Ziryukin, ftrvxmtrx(a)gmail.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EMMA3SL/LP +# + +TEXT_BASE = 0xbc000000 diff --git a/board/emma3sllp/emma3sllp.c b/board/emma3sllp/emma3sllp.c new file mode 100644 index 0000000..ff6e12a --- /dev/null +++ b/board/emma3sllp/emma3sllp.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2010 + * Serge Ziryukin, ftrvxmtrx(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <configs/emma3sllp.h> +#include <asm/io.h> +#include "emma3sllp.h" + +phys_size_t initdram(int board_type) +{ + return CONFIG_SYS_SDRAM_SIZE; +} + +int checkboard(void) +{ + puts("EMMA3SL/LP\n"); + + return 0; +} diff --git a/board/emma3sllp/emma3sllp.h b/board/emma3sllp/emma3sllp.h new file mode 100644 index 0000000..335f6fd --- /dev/null +++ b/board/emma3sllp/emma3sllp.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2010 + * Serge Ziryukin, ftrvxmtrx(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __EMMA3SLLP_H +#define __EMMA3SLLP_H + +/* host interface */ +#define BHIF_BASE_ADDRESS 0xb0000000 +#define BHIF_ALTERNATE0 0x28 + +/* rom interface */ +#define BROI_BASE_ADDRESS 0xb0000600 +#define BROI_ROM_MODE 0x00 +#define BROI_ROM_IF_MODE 0x08 + +/* memory interface */ +#define MIF_BASE_ADDRESS 0xb0000c00 +#define MIF_CONFIG1 0x04 +#define MIF_INIT 0x08 +#define MIF_REFCNT 0x0c +#define MIF_CONFIG2 0x10 +#define MIF_DLLSTBY 0xf0 +#define MIF_DLLCTRL 0xf4 +#define MIF_DLLOFSTW 0xf8 +#define MIF_DLLOFSTR 0xfc +#define MIF_RSTB 0xe0 +#define MIF_ODTSW 0xe4 +#define MIF_IOLHRSTB 0xe8 +#define MIF_IOLHCTRL 0xec + +#endif /* __EMMA3SLLP_H */ diff --git a/board/emma3sllp/lowlevel_init.S b/board/emma3sllp/lowlevel_init.S new file mode 100644 index 0000000..689e6dc --- /dev/null +++ b/board/emma3sllp/lowlevel_init.S @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2010 + * Serge Ziryukin, ftrvxmtrx(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include "emma3sllp.h" + +.text +.set noreorder +.set mips32 + +.macro REGWR offset, val + li t1, \val + sw t1, \offset(t0) +.endm + +#define MEM_200US (200 * CPU_CLOCK_RATE / 1000000) + +.global lowlevel_init +lowlevel_init: + + /* =================================== */ + /* enable peripherals */ + /* =================================== */ + li t0, BHIF_BASE_ADDRESS + + /* 17: usb, 18: ethernet, 19: fuart0 */ + REGWR BHIF_ALTERNATE0 0x000e0000 + + /* =================================== */ + /* set flash options */ + /* =================================== */ + li t0, BROI_BASE_ADDRESS + + /* change max size flash rom to 64Mb + to make it start from 0xbc000000 */ + lw t1, BROI_ROM_MODE(t0) + li t2, 0x08 + sub t2, zero, t2 + and t1, t1, t2 + ori t1, t1, 0x04 + sw t1, BROI_ROM_MODE(t0) + + /* enable write (for 4 possible flash chips) */ + lw t1, BROI_ROM_IF_MODE(t0) + ori t1, t1, 0x0f + sw t1, BROI_ROM_IF_MODE(t0) + + /* =================================== */ + /* DDR2 initialization */ + /* =================================== */ + li t0, MIF_BASE_ADDRESS + + /* + set wiring delay + 91-467ps @ 327.68MHz + 110-440ps @ 333.33MHz + */ + REGWR MIF_DLLOFSTW 0x0000e1e1 + REGWR MIF_DLLOFSTR 0x00002424 + + /* 316-350MHz (FSL=6) */ + REGWR MIF_DLLCTRL 0x00000020 + + /* exit from stand-by mode */ + REGWR MIF_DLLSTBY 0x00000000 + + /* clear rst */ + REGWR MIF_IOLHRSTB 0x00000001 + + /* wait until locked */ + li t2, 0x1 +1: + lw t1, MIF_DLLCTRL(t0) + and t1, t2 + bne t1, t2, 1b + nop + + /* wait until fixed */ + li t2, 0x1 +1: + lw t1, MIF_IOLHCTRL(t0) + and t1, t2 + bne t1, t2, 1b + nop + + /* clear rst */ + REGWR MIF_RSTB 0x00000001 + + /* set on-die termination to 75ohm and enable clock */ + REGWR MIF_ODTSW 0x00000101 + + /* 200us */ + li t2, MEM_200US +1: + bne t2, zero, 1b + addi t2, -1 + + /* + column 10 bits (A0 - A9), row 13 bits (A0 - A12) + CAS latency 5, 16-bit bus, 4 banks + */ + REGWR MIF_CONFIG1 0x74ba1b65 + + /* small PCB delay, one CS, 64Mb */ + REGWR MIF_CONFIG2 0x0aa20049 + + /* CKE high */ + REGWR MIF_INIT 0x00000020 + + /* 400ns */ + .rept 16 + nop + .endr + + /* precharge all banks (BA0=0, BA1=0, A10=1) */ + REGWR MIF_INIT 0x10000004 + /* EMRS(2): (BA1=1, BA0=0, Ax=0) */ + REGWR MIF_INIT 0x00020002 + /* EMRS(3): (BA0=1, BA1=1, Ax=0) */ + REGWR MIF_INIT 0x00030002 + /* EMRS(1): enable DLL (BA0=1, BA1=0, Ax=0) */ + REGWR MIF_INIT 0x00010002 + + /* + MRS: reset DLL (A8=1), BL=4 (A1=1) + CL=5 (A4=1, A6=1), WR=5 (A11=1) + */ + REGWR MIF_INIT 0x25480002 + + /* 200us */ + li t2, MEM_200US +1: + bne t2, zero, 1b + addi t2, -1 + + /* precharge all banks (BA0=0, BA1=0, A10=1) */ + REGWR MIF_INIT 0x10000004 + /* refresh */ + REGWR MIF_INIT 0x00000001 + /* refresh */ + REGWR MIF_INIT 0x00000001 + + /* 100ns */ + .rept 4 + nop + .endr + + /* + MRS: clear DLL reset flag (A8=0) + leave other parms as in earlier issued MRS + */ + REGWR MIF_INIT 0x21480002 + + /* + EMRS(1): OCD calibration + driver strength weak (A1=1), Rtt=75ohm (A2=1, A6=0) + */ + REGWR MIF_INIT 0x00590002 + + /* + set refresh interval to (0x50 * 16 * SCLK) + register = (0x50 | REFRESH_ENABLE) + REFRESH_ENABLE = 0x100 + */ + REGWR MIF_REFCNT 0x00000150 + + jr ra + nop diff --git a/board/emma3sllp/u-boot.lds b/board/emma3sllp/u-boot.lds new file mode 100644 index 0000000..73979af --- /dev/null +++ b/board/emma3sllp/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, <wd(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = .; + _gp = ALIGN(16) + 0x7ff0; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + .sdata : { *(.sdata) } + + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start ) >> 2; + + . = ALIGN(4); + .sbss (NOLOAD) : { *(.sbss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + uboot_end = .; +} diff --git a/doc/README.emma3sllp b/doc/README.emma3sllp new file mode 100644 index 0000000..dfefa9a --- /dev/null +++ b/doc/README.emma3sllp @@ -0,0 +1,10 @@ +EMMA3SL/LP + +generation: 0x02000011 (EMMA3SL/L) +product version: 0x018e +cpu: 4KEc, 288MHz +endianess: big +unified mem clock: 156MHz (SCLK = MCLK/2 = 312/2) +flash: S29GL064N90BFI04 (8Mb, 16bit, bottom boot) +memory: EDE5116AJBG-6E-E (64Mb, 16bit, 667Mbps) +ethernet: KSZ8041NL, RMII diff --git a/include/configs/emma3sllp.h b/include/configs/emma3sllp.h new file mode 100644 index 0000000..599104e --- /dev/null +++ b/include/configs/emma3sllp.h @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2010 + * Serge Ziryukin, ftrvxmtrx(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/addrspace.h> + +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_MIPS32 1 + +#define CPU_CLOCK_RATE 288000000 + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_TIMESTAMP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_BOOTARGS "" +#define CONFIG_EXTRA_ENV_SETTINGS "" +#define CONFIG_BOOTCOMMAND "" +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_SAVEENV + +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_FAT + +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_BSP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_PORTIO + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 + +/* 256Kb */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +/* 64Kb */ +#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_SIZE (64 << 20) +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_LOAD_ADDR 0x80400000 +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x80800000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +/* one flash bank */ +#define PHYS_FLASH_1 0xbc000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 135 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_FLASH_PROTECTION 1 + +/* erase/write timeouts in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +/* env on flash */ +#define CONFIG_ENV_ADDR \ + (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE + +/* cache */ +#define CONFIG_SYS_DCACHE_SIZE (8 << 10) /* 8kB */ +#define CONFIG_SYS_ICACHE_SIZE (8 << 10) /* 8kB */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +/* serial */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 4 +#define CONFIG_SYS_NS16550_CLK 18432000 +#define CONFIG_SYS_NS16550_COM1 0xb0101000 +#define CONFIG_SYS_NS16550_COM2 0xb0102000 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#endif /* __CONFIG_H */ -- 1.7.1

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[U-Boot] [PATCH] Adds driver for Xilinx' xps_spi SPI controller.
by Graeme Smecher 02 Apr '12

02 Apr '12

This code differs in only trivial ways from the altera_spi driver. It plays nice with Thomas Chou's mmc_spi driver, as well as with SPI flash. Documentation for the SPI core is available here: http://www.xilinx.com/support/documentation/ip_documentation/xps_spi.pdf Signed-off-by: Graeme Smecher <graeme.smecher(a)mail.mcgill.ca> --- drivers/spi/Makefile | 1 + drivers/spi/xilinx_spi.c | 173 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 174 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/xilinx_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index dfcbb8b..34e0f31 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.a COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o +COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c new file mode 100644 index 0000000..bda7c5b --- /dev/null +++ b/drivers/spi/xilinx_spi.c @@ -0,0 +1,173 @@ +/* + * Xilinx SPI driver + * + * based on bfin_spi.c, by way of altera_spi.c + * Copyright (c) 2005-2008 Analog Devices Inc. + * Copyright (c) 2010 Thomas Chou <thomas(a)wytron.com.tw> + * Copyright (c) 2010 Graeme Smecher <graeme.smecher(a)mail.mcgill.ca> + * + * Licensed under the GPL-2 or later. + */ +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> + +#define XILINX_SPI_RR 0x6c +#define XILINX_SPI_TR 0x68 +#define XILINX_SPI_SR 0x64 +#define XILINX_SPI_CR 0x60 +#define XILINX_SPI_SSR 0x70 + +#define XILINX_SPI_SR_RX_EMPTY_MSK 0x01 + +#define XILINX_SPI_CR_DEFAULT (0x0006) +#define XILINX_SPI_CR_MSS_MSK (0x0080) + +#if XPAR_XSPI_NUM_INSTANCES > 4 +# warning "The xilinx_spi driver will ignore some of your SPI peripherals!" +#endif + +static ulong xilinx_spi_base_list[] = { +#ifdef XPAR_SPI_0_BASEADDR + XPAR_SPI_0_BASEADDR, +#endif +#ifdef XPAR_SPI_1_BASEADDR + XPAR_SPI_1_BASEADDR, +#endif +#ifdef XPAR_SPI_2_BASEADDR + XPAR_SPI_2_BASEADDR, +#endif +#ifdef XPAR_SPI_3_BASEADDR + XPAR_SPI_3_BASEADDR, +#endif +}; + +struct xilinx_spi_slave { + struct spi_slave slave; + ulong base; +}; +#define to_xilinx_spi_slave(s) container_of(s, struct xilinx_spi_slave, slave) + +__attribute__((weak)) +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32; +} + +__attribute__((weak)) +void spi_cs_activate(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + writel(~(1 << slave->cs), xilspi->base + XILINX_SPI_SSR); + writel(XILINX_SPI_CR_DEFAULT | XILINX_SPI_CR_MSS_MSK, + xilspi->base + XILINX_SPI_CR); +} + +__attribute__((weak)) +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + + writel(XILINX_SPI_CR_DEFAULT, xilspi->base + XILINX_SPI_CR); + writel(~0, xilspi->base + XILINX_SPI_SSR); +} + +void spi_init(void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct xilinx_spi_slave *xilspi; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + xilspi = malloc(sizeof(*xilspi)); + if (!xilspi) + return NULL; + + xilspi->slave.bus = bus; + xilspi->slave.cs = cs; + xilspi->base = xilinx_spi_base_list[bus]; + debug("%s: bus:%i cs:%i base:%lx\n", __func__, + bus, cs, xilspi->base); + + return &xilspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + free(xilspi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + writel(XILINX_SPI_CR_DEFAULT, xilspi->base + XILINX_SPI_CR); + writel(~0, xilspi->base + XILINX_SPI_SSR); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + writel(~0, xilspi->base + XILINX_SPI_SSR); +} + +#ifndef CONFIG_XILINX_SPI_IDLE_VAL +# define CONFIG_XILINX_SPI_IDLE_VAL 0xff +#endif + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + /* assume spi core configured to do 8 bit transfers */ + uint bytes = bitlen / 8; + const uchar *txp = dout; + uchar *rxp = din; + + debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, + slave->bus, slave->cs, bitlen, bytes, flags); + if (bitlen == 0) + goto done; + + if (bitlen % 8) { + flags |= SPI_XFER_END; + goto done; + } + + /* empty read buffer */ + while (!(readl(xilspi->base + XILINX_SPI_SR) & + XILINX_SPI_SR_RX_EMPTY_MSK)) + readl(xilspi->base + XILINX_SPI_RR); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (bytes--) { + uchar d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; + debug("%s: tx:%x ", __func__, d); + writel(d, xilspi->base + XILINX_SPI_TR); + while (readl(xilspi->base + XILINX_SPI_SR) & + XILINX_SPI_SR_RX_EMPTY_MSK) + ; + d = readl(xilspi->base + XILINX_SPI_RR); + if (rxp) + *rxp++ = d; + debug("rx:%x\n", d); + } + done: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} -- 1.6.3.3

6 11

[U-Boot] Does U-boot supports Spansion S29GL512P NOR Flash?
by prakash bedge 10 Mar '12

10 Mar '12

Hi, In U-boot I am not seeing the support for Spansion S29GL512P NOR flash. This chip is CFI compliant so I believe the common CFI driver should work with this chip. Does U-boot supports S29GL512P NOR flash or I have to implement the functionality to support S29GL512P? If anyone has tried with S29GL512P NOR flash please share the experiecne. Thanks & Regards, Prakash

6 30

[U-Boot] U-boot running on DDR fails to detect the CFI compliant flash
by prakash bedge 15 Feb '12

15 Feb '12

Hi Stefan, In October 09 month, I had asked whether U-boot supports M29W128GH, a CFI compilant chip and I got a yes reply. Please refer below URL for reference. http://www.mail-archive.com/u-boot@lists.denx.de/msg24531.html. So I have used Uboot for my PPC440 based board. When I flashed U-boot on flash and then run the Uboot in DDR then U-boot running on DDR fails to detect CFI chip M29W128GH (16M x 8 mode). flash_detect_cfi function gives error that flash not found. I have added debug statements for temporary debug purpose. Please see the below error I am getting. The CFI query address looks different in below code and not as per ST make M29W128GH specs. PCIMW. static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { int cfi_offset; debug ("1__flash detect cfi\n"); /* We do not yet know what kind of commandset to use, so we issue the reset command in both Intel and AMD variants, in the hope that AMD flash roms ignore the Intel command. */ flash_write_cmd (info, 0, 0, AMD_CMD_RESET); flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); debug ("2__flash detect cfi\n"); for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); cfi_offset++) { flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI); debug ("3__flash detect cfi\n"); if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, sizeof(struct cfi_qry)); /* UART Output */ U-Boot 2009.08 (Jan 15 2010 - 16:44:40) DRAM: Meminfo.ptrCDBs: 0xc00174e0 512 MB (ECC is ON, 400 MHz, CL 7) Top of RAM usable for U-Boot at: 20000000 Reserving 174k for U-Boot at: 1ffd4000 Reserving 1040k for malloc() at: 1fed0000 Reserving 128 Bytes for Board Info at: 1fecff80 Reserving 64 Bytes for Global Data at: 1fecff40 Stack Pointer at: 1fecff28 New Stack Pointer is: 1fecff28 after watchdog reset after watchdog reset 2 after memcpy befor relocate addr_sp = 1fecff28, id = 1fecff40, addr = 1ffd4000 Now running in RAM - U-Boot at: 1ffd4000 FLASH: flash detect cfi 1__flash detect cfi fwc addr ff000000 cmd f0 f0 8bit x 8 bit Entering into First Write First Write is done fwc addr ff000000 cmd ff ff 8bit x 8 bit Entering into First Write First Write is done 2__flash detect cfi fwc addr ff000055 cmd 98 98 8bit x 8 bit Entering into First Write First Write is done 3__flash detect cfi is= cmd 51(Q) addr ff000010 is= ff 51 fwc addr ff000555 cmd 98 98 8bit x 8 bit Entering into First Write First Write is done 3__flash detect cfi is= cmd 51(Q) addr ff000010 is= ff 51 1__flash detect cfi fwc addr ff000000 cmd f0 f0f0 16bit x 8 bit fwc addr ff000000 cmd ff ffff 16bit x 8 bit 2__flash detect cfi fwc addr ff0000aa cmd 98 9898 16bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 5151 fwc addr ff000aaa cmd 98 9898 16bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 5151 1__flash detect cfi fwc addr ff000000 cmd f0 00f0 16bit x 16 bit fwc addr ff000000 cmd ff 00ff 16bit x 16 bit 2__flash detect cfi fwc addr ff0000aa cmd 98 0098 16bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 0051 fwc addr ff000aaa cmd 98 0098 16bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 0051 1__flash detect cfi fwc addr ff000000 cmd f0 f0f0f0f0 32bit x 8 bit fwc addr ff000000 cmd ff ffffffff 32bit x 8 bit 2__flash detect cfi fwc addr ff000154 cmd 98 98989898 32bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 51515151 fwc addr ff001554 cmd 98 98989898 32bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 51515151 1__flash detect cfi fwc addr ff000000 cmd f0 00f000f0 32bit x 16 bit fwc addr ff000000 cmd ff 00ff00ff 32bit x 16 bit 2__flash detect cfi fwc addr ff000154 cmd 98 00980098 32bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00510051 fwc addr ff001554 cmd 98 00980098 32bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00510051 1__flash detect cfi fwc addr ff000000 cmd f0 000000f0 32bit x 32 bit fwc addr ff000000 cmd ff 000000ff 32bit x 32 bit 2__flash detect cfi fwc addr ff000154 cmd 98 00000098 32bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00000051 fwc addr ff001554 cmd 98 00000098 32bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00000051 1__flash detect cfi fwrite addr ff000000 cmd f0 f0f0f0f0f0f0f0f0 64 bit x 8 bit fwrite addr ff000000 cmd ff ffffffffffffffff 64 bit x 8 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 9898989898989898 64 bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 5151515151515151 fwrite addr ff002aa8 cmd 98 9898989898989898 64 bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 5151515151515151 1__flash detect cfi fwrite addr ff000000 cmd f0 00f000f000f000f0 64 bit x 16 bit fwrite addr ff000000 cmd ff 00ff00ff00ff00ff 64 bit x 16 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 0098009800980098 64 bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0051005100510051 fwrite addr ff002aa8 cmd 98 0098009800980098 64 bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0051005100510051 1__flash detect cfi fwrite addr ff000000 cmd f0 000000f0000000f0 64 bit x 32 bit fwrite addr ff000000 cmd ff 000000ff000000ff 64 bit x 32 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 0000009800000098 64 bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000005100000051 fwrite addr ff002aa8 cmd 98 0000009800000098 64 bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000005100000051 1__flash detect cfi fwrite addr ff000000 cmd f0 00000000000000f0 64 bit x 64 bit fwrite addr ff000000 cmd ff 00000000000000ff 64 bit x 64 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 0000000000000098 64 bit x 64 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000000000000051 fwrite addr ff002aa8 cmd 98 0000000000000098 64 bit x 64 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000000000000051 not found ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB flash_protect ON: from 0xFFFC0000 to 0xFFFE8AFF flash_protect ON: from 0xFFFA0000 to 0xFFFBFFFF *** failed *** ### ERROR ### Please RESET the board ### What should be the cause. It would be really helpful if someone who have face this kind of issues can give some inputs. TIA. Regards, Prakash

6 12

[U-Boot] [RFC] CDC Ethernet support + USB Gadget in U-boot
by Remy Bohmer 19 Jan '12

19 Jan '12

Hello All, We (Thomas Smits and I) have been working on CDC Ethernet support in U-boot. We ported the Linux Gadget and CDC Ethernet driver to U-boot and added support for the Atmel AT91SAM9261-EK kit. Support for other cores can be added easily. Although it is still work in progress, it is already working stable. I also have a patch for adding RNDIS support on top of this series, but that is not finished/stable yet. The series is quite huge, and still in development, so I decided to not post this series inline. I made the tree public via the U-boot-usb tree, 'cdc' branch ( http://git.denx.de/?p=u-boot/u-boot-usb.git;a=shortlog;h=refs/heads/cdc) I would like to stabilise this code in a separate branch until it is mature enough for mainline integration, I will keep this branch always ahead mainline. So, any comments on this code are welcome! But, even more welcome are patches on top of it to make it even better and add more board support for it. Kind Regards, Remy

2 1

[U-Boot] [PATCH] arm/pxa: fix and cleanup of pxa_mem_setup macro v2
by Mikhail Kshevetskiy 17 Nov '11

17 Nov '11

WARNING: This macro do not assume the values for K0DB4, KxDB2, KxFREE, K1RUN, K2RUN and APD bits of CONFIG_SYS_MDREFR_VAL as it was done early on many pxa platforms. All pxa developers that plan to use this macro should check the validity of their MDREFR values. v1: * strict following to section 6.4.10 of Intel PXA27xx Developer's Manual. * use r7 to store CONFIG_SYS_MDREFR_VAL as r6 is used in pxa_wait_ticks. v2: * rename pxa_mem_setup macro to pxa2xx_mem_setup * setting of MDREFR[K1RUN] and MDREFR[K2RUN] bits may be optional * skip certain configuration steps if SDRAM is not present/configured * improve/fix comments Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy(a)gmail.com> --- arch/arm/include/asm/arch-pxa/macro.h | 82 ++++++++++++++++++++++----------- board/vpac270/lowlevel_init.S | 2 +- 2 files changed, 56 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 1f1759b..e2ddfe9 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -102,11 +102,15 @@ /* * This macro sets up the Memory controller of the PXA2xx CPU * - * Clobbered regs: r3, r4, r5 + * Clobbered regs: r3, r4, r5, r6, r7 + * + * See section 6.4.10 of Intel PXA2xx Processor Developer's Manual + * http://www.marvell.com/products/processors/applications/pxa_family/pxa_27x_… */ -.macro pxa_mem_setup +.macro pxa2xx_mem_setup /* This comes handy when setting MDREFR */ ldr r3, =MEMC_BASE + ldr r7, =CONFIG_SYS_MDREFR_VAL /* * 1) Initialize Asynchronous static memory controller @@ -149,51 +153,68 @@ */ /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. + * Before accessing MDREFR we need a valid DRI field. + * Also we must properly configure MDREFR[K0DB2] and MDREFR[K0DB4]. + * Optionaly we can set MDREFR[KxFREE] bits. + * So we set MDREFR to power on defaults + (DRI, K0DB2, K0DB4, KxFREE) + * fields from the config. + * + * WARNING: K0DB2 and K0DB4 bits are usually set, while KxFREE bits + * are usually unset. */ ldr r5, [r3, #MDREFR_OFFSET] - bic r5, r5, #0x0ff - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r6, r4 - lsl r4, #20 - lsr r4, #20 /* Get a valid DRI field */ - - orr r5, r5, r4 /* MDREFR user config with correct DRI */ + ldr r4, =( 0xFFF | MDREFR_K0DB4 | MDREFR_K0DB2 | \ + MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE ) + bic r5, r5, r4 /* clear DRI, K0DB2, K0DB4, KxFREE fields */ + and r4, r7, r4 + orr r5, r5, r4 /* use custom DRI, K0DB2, K0DB4, KxFREE */ orr r5, #MDREFR_K0RUN orr r5, #MDREFR_SLFRSH bic r5, #MDREFR_APD - bic r5, #MDREFR_E1PIN + + /* enable them later, if SDRAM is present */ + bic r5, #( MDREFR_E1PIN | MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) str r5, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 5) Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* Initialize SXCNFG register. Assert the enable bits. - * - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be written - * at this time. + /* Initialize SXCNFG register to enable synchronous flash memory. + * While the synchronous flash banks are being configured, the SDRAM + * banks must be disabled and MDREFR[APD] must be de-asserted. */ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL /* - * 6) Initialize SDRAM + * 6) Initialize SDRAM, + * If SDRAM present, then MDREFR[K1RUN] and/or MDREFR[K1RUN] bits + * must be set. Also we must properly configure MDREFR[K1DB2] and + * MDREFR[K2DB2] in this case. + * + * WARNING: K1DB2 and K2DB2 bits are usually set if SDRAM present */ +#if (CONFIG_SYS_MDREFR_VAL & (MDREFR_K1RUN | MDREFR_K2RUN)) + and r4, r7, #( MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) + ldr r6, [r3, #MDREFR_OFFSET] + orr r6, r6, r4 + str r6, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] + bic r6, #MDREFR_SLFRSH str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] orr r6, #MDREFR_E1PIN str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] +#endif /* * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure @@ -209,6 +230,7 @@ str r4, [r3, #MDCNFG_OFFSET] ldr r4, [r3, #MDCNFG_OFFSET] +#if (CONFIG_SYS_MDREFR_VAL & (MDREFR_K1RUN | MDREFR_K2RUN)) /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ pxa_wait_ticks 0x300 @@ -226,7 +248,7 @@ .endr /* - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). + * 9) Set custom MDCNFG[DEx] bits to enable required SDRAM partitions */ ldr r5, =CONFIG_SYS_MDCNFG_VAL @@ -238,19 +260,25 @@ ldr r4, [r3, #MDCNFG_OFFSET] /* - * 10) Write MDMRS. + * 10) Write to MDMRS register to trigger an MRS command to + * all enabled banks of SDRAM. For each SDRAM partition pair + * that has one or both partitions enabled, this forces a pass + * through the MRS state and a return to NOP. */ ldr r4, =CONFIG_SYS_MDMRS_VAL str r4, [r3, #MDMRS_OFFSET] ldr r4, [r3, #MDMRS_OFFSET] +#endif /* - * 11) Enable APD + * 11) Optionaly enable auto-power-down by setting MDREFR[APD] + * + * WARNING: APD bit is usually set. */ ldr r4, [r3, #MDREFR_OFFSET] - and r6, r6, #MDREFR_APD + and r6, r7, #MDREFR_APD orr r4, r4, r6 str r4, [r3, #MDREFR_OFFSET] ldr r4, [r3, #MDREFR_OFFSET] diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S index ec0d12c..a327ebd 100644 --- a/board/vpac270/lowlevel_init.S +++ b/board/vpac270/lowlevel_init.S @@ -32,7 +32,7 @@ lowlevel_init: pxa_gpio_setup pxa_wait_ticks 0x8000 - pxa_mem_setup + pxa2xx_mem_setup pxa_wakeup pxa_intr_setup pxa_clock_setup -- 1.7.1

2 2

[U-Boot] Uboot for Mips
by Rahanesh 13 Sep '11

13 Sep '11

Hi All, I am currently working on MIPS board. I have a 32MB RAM. The address that is shown in uboot when i type bdinfo if 0x80000000 and size is 0x1000000(16MB). I want to increase the size to 32 MB as board has 32 MB RAM. Interesting Finding: When i write any data to 0x80000000 the same data is being written into 0x81000000. Same for all address in the range (data in 0x80000000 - 0x80ffffff is same as 0x81000000 - 0x81ffffff ). It seems that there is a dual mapping . What might be the reason? Please help -- View this message in context: http://www.nabble.com/Uboot-for-Mips-tp24366921p24366921.html Sent from the Uboot - Users mailing list archive at Nabble.com.

2 1

[U-Boot] [PATCH 1/4 v3] musb: Use name based initialization for musb_config
by Ajay Kumar Gupta 06 Jul '11

06 Jul '11

Changed musb_config initialization for omap3.c, davinci.c and da8xx.c using name of structure fields. This would cause the uninitialized field to be null by default and thus would help in avoiding to init some flags required to be set only for a few selected platforms. CC: Remy Bohmer <linux(a)bohmer.net> Signed-off-by: Ajay Kumar Gupta <ajay.gupta(a)ti.com> --- No change from v2. drivers/usb/musb/da8xx.c | 6 +++--- drivers/usb/musb/davinci.c | 6 +++--- drivers/usb/musb/omap3.c | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c index 40bfe44..617d88e 100644 --- a/drivers/usb/musb/da8xx.c +++ b/drivers/usb/musb/da8xx.c @@ -27,9 +27,9 @@ /* MUSB platform configuration */ struct musb_config musb_cfg = { - (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE, - DA8XX_USB_OTG_TIMEOUT, - 0 + .regs = (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE, + .timeout = DA8XX_USB_OTG_TIMEOUT, + .musb_speed = 0, }; /* diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c index 8fbadc9..f56f2df 100644 --- a/drivers/usb/musb/davinci.c +++ b/drivers/usb/musb/davinci.c @@ -28,9 +28,9 @@ /* MUSB platform configuration */ struct musb_config musb_cfg = { - (struct musb_regs *)MENTOR_USB0_BASE, - DAVINCI_USB_TIMEOUT, - 0 + .regs = (struct musb_regs *)MENTOR_USB0_BASE, + .timeout = DAVINCI_USB_TIMEOUT, + .musb_speed = 0, }; /* MUSB module register overlay */ diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c index 3bfd0a0..785629c 100644 --- a/drivers/usb/musb/omap3.c +++ b/drivers/usb/musb/omap3.c @@ -36,9 +36,9 @@ static int platform_needs_initialization = 1; struct musb_config musb_cfg = { - (struct musb_regs *)MENTOR_USB0_BASE, - OMAP3_USB_TIMEOUT, - 0 + .regs = (struct musb_regs *)MENTOR_USB0_BASE, + .timeout = OMAP3_USB_TIMEOUT, + .musb_speed = 0, }; /* -- 1.6.2.4

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[U-Boot] convention for SPI dummy data?
by wolfgang＠leila.ping.de 13 Jun '11

13 Jun '11

Hi, I have finally got MMC/SD working on my coldfire board and would like to send some patches. However, one of the things I had to change was the dummy data sent out by SPI for read-only transactions. The original driver had all zeros, for SD/MMC all ones (0xFF) is needed. Is such a change acceptable, or is there any configuration option/flag I could use? Regards, Wolfgang

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